1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
11 #include <sys/ioctl.h>
12 #include <sys/epoll.h>
15 #include <rte_malloc.h>
16 #include <rte_devargs.h>
17 #include <rte_memcpy.h>
19 #include <rte_bus_pci.h>
20 #include <rte_kvargs.h>
21 #include <rte_alarm.h>
22 #include <rte_interrupts.h>
23 #include <rte_errno.h>
24 #include <rte_per_lcore.h>
25 #include <rte_memory.h>
26 #include <rte_memzone.h>
28 #include <rte_common.h>
29 #include <rte_bus_vdev.h>
30 #include <rte_string_fns.h>
31 #include <rte_pmd_i40e.h>
33 #include "base/opae_hw_api.h"
34 #include "base/opae_ifpga_hw_api.h"
35 #include "base/ifpga_api.h"
36 #include "rte_rawdev.h"
37 #include "rte_rawdev_pmd.h"
38 #include "rte_bus_ifpga.h"
39 #include "ifpga_common.h"
40 #include "ifpga_logs.h"
41 #include "ifpga_rawdev.h"
42 #include "ipn3ke_rawdev_api.h"
44 #define RTE_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
45 #define RTE_PCI_CFG_SPACE_SIZE 256
46 #define RTE_PCI_CFG_SPACE_EXP_SIZE 4096
47 #define RTE_PCI_EXT_CAP_ID(header) (int)(header & 0x0000ffff)
48 #define RTE_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
50 int ifpga_rawdev_logtype;
52 #define PCI_VENDOR_ID_INTEL 0x8086
54 #define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
55 #define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
56 #define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
57 #define PCIE_DEVICE_ID_PAC_N3000 0x0B30
59 #define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
60 #define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
61 #define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
62 #define PCIE_DEVICE_ID_VF_PAC_N3000 0x0B31
63 #define RTE_MAX_RAW_DEVICE 10
65 static const struct rte_pci_id pci_ifpga_map[] = {
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
74 { .vendor_id = 0, /* sentinel */ },
77 static struct ifpga_rawdev ifpga_rawdevices[IFPGA_RAWDEV_NUM];
79 static int ifpga_monitor_start;
80 static pthread_t ifpga_monitor_start_thread;
82 #define IFPGA_MAX_IRQ 12
83 /* 0 for FME interrupt, others are reserved for AFU irq */
84 static struct rte_intr_handle ifpga_irq_handle[IFPGA_MAX_IRQ];
86 static struct ifpga_rawdev *
87 ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
88 static int set_surprise_link_check_aer(
89 struct ifpga_rawdev *ifpga_rdev, int force_disable);
90 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
92 static int ifpga_pci_find_ext_capability(unsigned int fd, int cap);
95 ifpga_rawdev_get(const struct rte_rawdev *rawdev)
97 struct ifpga_rawdev *dev;
103 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
104 dev = &ifpga_rawdevices[i];
105 if (dev->rawdev == rawdev)
112 static inline uint8_t
113 ifpga_rawdev_find_free_device_index(void)
117 for (dev_id = 0; dev_id < IFPGA_RAWDEV_NUM; dev_id++) {
118 if (ifpga_rawdevices[dev_id].rawdev == NULL)
122 return IFPGA_RAWDEV_NUM;
124 static struct ifpga_rawdev *
125 ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
127 struct ifpga_rawdev *dev;
130 dev = ifpga_rawdev_get(rawdev);
132 IFPGA_RAWDEV_PMD_ERR("Event device already allocated!");
136 dev_id = ifpga_rawdev_find_free_device_index();
137 if (dev_id == IFPGA_RAWDEV_NUM) {
138 IFPGA_RAWDEV_PMD_ERR("Reached maximum number of raw devices");
142 dev = &ifpga_rawdevices[dev_id];
143 dev->rawdev = rawdev;
144 dev->dev_id = dev_id;
149 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
154 int pos = RTE_PCI_CFG_SPACE_SIZE;
157 /* minimum 8 bytes per capability */
158 ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
162 ret = pread(fd, &header, sizeof(header), pos);
167 * If we have no capabilities, this is indicated by cap ID,
168 * cap version and next pointer all being 0.
174 if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
177 pos = RTE_PCI_EXT_CAP_NEXT(header);
178 if (pos < RTE_PCI_CFG_SPACE_SIZE)
180 ret = pread(fd, &header, sizeof(header), pos);
188 static int ifpga_pci_find_ext_capability(unsigned int fd, int cap)
190 return ifpga_pci_find_next_ext_capability(fd, 0, cap);
193 static int ifpga_get_dev_vendor_id(const char *bdf,
194 uint32_t *dev_id, uint32_t *vendor_id)
201 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
202 strlcat(path, bdf, sizeof(path));
203 strlcat(path, "/config", sizeof(path));
204 fd = open(path, O_RDWR);
207 ret = pread(fd, &header, sizeof(header), 0);
212 (*vendor_id) = header & 0xffff;
213 (*dev_id) = (header >> 16) & 0xffff;
218 static int ifpga_rawdev_fill_info(struct ifpga_rawdev *ifpga_dev,
221 char path[1024] = "/sys/bus/pci/devices/0000:";
222 char link[1024], link1[1024];
223 char dir[1024] = "/sys/devices/";
226 char sub_brg_bdf[4][16];
229 struct dirent *entry;
232 unsigned int dom, bus, dev;
234 uint32_t dev_id, vendor_id;
236 strlcat(path, bdf, sizeof(path));
237 memset(link, 0, sizeof(link));
238 memset(link1, 0, sizeof(link1));
239 ret = readlink(path, link, (sizeof(link)-1));
242 strlcpy(link1, link, sizeof(link1));
243 memset(ifpga_dev->parent_bdf, 0, 16);
244 point = strlen(link);
252 rte_memcpy(ifpga_dev->parent_bdf, &link[point], 12);
254 point = strlen(link1);
262 c = strchr(link1, 'p');
265 strlcat(dir, c, sizeof(dir));
272 while ((entry = readdir(dp)) != NULL) {
275 if (entry->d_name[0] == '.')
277 if (strlen(entry->d_name) > 12)
279 if (sscanf(entry->d_name, "%x:%x:%x.%d",
280 &dom, &bus, &dev, &func) < 4)
283 strlcpy(sub_brg_bdf[i],
285 sizeof(sub_brg_bdf[i]));
291 /* get fpga and fvl */
293 for (i = 0; i < 4; i++) {
294 strlcpy(link, dir, sizeof(link));
295 strlcat(link, "/", sizeof(link));
296 strlcat(link, sub_brg_bdf[i], sizeof(link));
300 while ((entry = readdir(dp)) != NULL) {
303 if (entry->d_name[0] == '.')
306 if (strlen(entry->d_name) > 12)
308 if (sscanf(entry->d_name, "%x:%x:%x.%d",
309 &dom, &bus, &dev, &func) < 4)
312 if (ifpga_get_dev_vendor_id(entry->d_name,
313 &dev_id, &vendor_id))
315 if (vendor_id == 0x8086 &&
319 strlcpy(ifpga_dev->fvl_bdf[j],
321 sizeof(ifpga_dev->fvl_bdf[j]));
332 #define HIGH_FATAL(_sens, value)\
333 (((_sens)->flags & OPAE_SENSOR_HIGH_FATAL_VALID) &&\
334 (value > (_sens)->high_fatal))
336 #define HIGH_WARN(_sens, value)\
337 (((_sens)->flags & OPAE_SENSOR_HIGH_WARN_VALID) &&\
338 (value > (_sens)->high_warn))
340 #define LOW_FATAL(_sens, value)\
341 (((_sens)->flags & OPAE_SENSOR_LOW_FATAL_VALID) &&\
342 (value > (_sens)->low_fatal))
344 #define LOW_WARN(_sens, value)\
345 (((_sens)->flags & OPAE_SENSOR_LOW_WARN_VALID) &&\
346 (value > (_sens)->low_warn))
348 #define AUX_VOLTAGE_WARN 11400
351 ifpga_monitor_sensor(struct rte_rawdev *raw_dev,
354 struct opae_adapter *adapter;
355 struct opae_manager *mgr;
356 struct opae_sensor_info *sensor;
360 adapter = ifpga_rawdev_get_priv(raw_dev);
364 mgr = opae_adapter_get_mgr(adapter);
368 opae_mgr_for_each_sensor(mgr, sensor) {
369 if (!(sensor->flags & OPAE_SENSOR_VALID))
372 ret = opae_mgr_get_sensor_value(mgr, sensor, &value);
376 if (value == 0xdeadbeef) {
377 IFPGA_RAWDEV_PMD_ERR("dev_id %d sensor %s value %x\n",
378 raw_dev->dev_id, sensor->name, value);
382 /* monitor temperature sensors */
383 if (!strcmp(sensor->name, "Board Temperature") ||
384 !strcmp(sensor->name, "FPGA Die Temperature")) {
385 IFPGA_RAWDEV_PMD_INFO("read sensor %s %d %d %d\n",
386 sensor->name, value, sensor->high_warn,
389 if (HIGH_WARN(sensor, value) ||
390 LOW_WARN(sensor, value)) {
391 IFPGA_RAWDEV_PMD_INFO("%s reach theshold %d\n",
392 sensor->name, value);
398 /* monitor 12V AUX sensor */
399 if (!strcmp(sensor->name, "12V AUX Voltage")) {
400 if (value < AUX_VOLTAGE_WARN) {
401 IFPGA_RAWDEV_PMD_INFO(
402 "%s reach theshold %d mV\n",
403 sensor->name, value);
415 static int set_surprise_link_check_aer(
416 struct ifpga_rawdev *ifpga_rdev, int force_disable)
418 struct rte_rawdev *rdev;
425 uint32_t aer_new0, aer_new1;
428 printf("\n device does not exist\n");
432 rdev = ifpga_rdev->rawdev;
433 if (ifpga_rdev->aer_enable)
435 if (ifpga_monitor_sensor(rdev, &enable))
437 if (enable || force_disable) {
438 IFPGA_RAWDEV_PMD_ERR("Set AER, pls graceful shutdown\n");
439 ifpga_rdev->aer_enable = 1;
441 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
442 strlcat(path, ifpga_rdev->parent_bdf, sizeof(path));
443 strlcat(path, "/config", sizeof(path));
444 fd = open(path, O_RDWR);
447 pos = ifpga_pci_find_ext_capability(fd, RTE_PCI_EXT_CAP_ID_ERR);
450 /* save previout ECAP_AER+0x08 */
451 ret = pread(fd, &data, sizeof(data), pos+0x08);
454 ifpga_rdev->aer_old[0] = data;
455 /* save previout ECAP_AER+0x14 */
456 ret = pread(fd, &data, sizeof(data), pos+0x14);
459 ifpga_rdev->aer_old[1] = data;
461 /* set ECAP_AER+0x08 to 0xFFFFFFFF */
463 ret = pwrite(fd, &data, 4, pos+0x08);
466 /* set ECAP_AER+0x14 to 0xFFFFFFFF */
467 ret = pwrite(fd, &data, 4, pos+0x14);
471 /* read current ECAP_AER+0x08 */
472 ret = pread(fd, &data, sizeof(data), pos+0x08);
476 /* read current ECAP_AER+0x14 */
477 ret = pread(fd, &data, sizeof(data), pos+0x14);
485 printf(">>>>>>Set AER %x,%x %x,%x\n",
486 ifpga_rdev->aer_old[0], ifpga_rdev->aer_old[1],
499 ifpga_rawdev_gsd_handle(__rte_unused void *param)
501 struct ifpga_rawdev *ifpga_rdev;
508 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
509 ifpga_rdev = &ifpga_rawdevices[i];
510 if (ifpga_rdev->rawdev) {
511 ret = set_surprise_link_check_aer(ifpga_rdev,
513 if (ret == 1 && !gsd_enable) {
521 printf(">>>>>>Pls Shutdown APP\n");
523 rte_delay_us(100 * MS);
530 ifpga_monitor_start_func(void)
534 if (ifpga_monitor_start == 0) {
535 ret = pthread_create(&ifpga_monitor_start_thread,
537 ifpga_rawdev_gsd_handle, NULL);
539 IFPGA_RAWDEV_PMD_ERR(
540 "Fail to create ifpga nonitor thread");
543 ifpga_monitor_start = 1;
549 ifpga_monitor_stop_func(void)
553 if (ifpga_monitor_start == 1) {
554 ret = pthread_cancel(ifpga_monitor_start_thread);
556 IFPGA_RAWDEV_PMD_ERR("Can't cancel the thread");
558 ret = pthread_join(ifpga_monitor_start_thread, NULL);
560 IFPGA_RAWDEV_PMD_ERR("Can't join the thread");
562 ifpga_monitor_start = 0;
571 ifpga_fill_afu_dev(struct opae_accelerator *acc,
572 struct rte_afu_device *afu_dev)
574 struct rte_mem_resource *res = afu_dev->mem_resource;
575 struct opae_acc_region_info region_info;
576 struct opae_acc_info info;
580 ret = opae_acc_get_info(acc, &info);
584 if (info.num_regions > PCI_MAX_RESOURCE)
587 afu_dev->num_region = info.num_regions;
589 for (i = 0; i < info.num_regions; i++) {
590 region_info.index = i;
591 ret = opae_acc_get_region_info(acc, ®ion_info);
595 if ((region_info.flags & ACC_REGION_MMIO) &&
596 (region_info.flags & ACC_REGION_READ) &&
597 (region_info.flags & ACC_REGION_WRITE)) {
598 res[i].phys_addr = region_info.phys_addr;
599 res[i].len = region_info.len;
600 res[i].addr = region_info.addr;
609 ifpga_rawdev_info_get(struct rte_rawdev *dev,
610 rte_rawdev_obj_t dev_info)
612 struct opae_adapter *adapter;
613 struct opae_accelerator *acc;
614 struct rte_afu_device *afu_dev;
615 struct opae_manager *mgr = NULL;
616 struct opae_eth_group_region_info opae_lside_eth_info;
617 struct opae_eth_group_region_info opae_nside_eth_info;
618 int lside_bar_idx, nside_bar_idx;
620 IFPGA_RAWDEV_PMD_FUNC_TRACE();
623 IFPGA_RAWDEV_PMD_ERR("Invalid request");
627 adapter = ifpga_rawdev_get_priv(dev);
632 afu_dev->rawdev = dev;
634 /* find opae_accelerator and fill info into afu_device */
635 opae_adapter_for_each_acc(adapter, acc) {
636 if (acc->index != afu_dev->id.port)
639 if (ifpga_fill_afu_dev(acc, afu_dev)) {
640 IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
645 /* get opae_manager to rawdev */
646 mgr = opae_adapter_get_mgr(adapter);
648 /* get LineSide BAR Index */
649 if (opae_manager_get_eth_group_region_info(mgr, 0,
650 &opae_lside_eth_info)) {
653 lside_bar_idx = opae_lside_eth_info.mem_idx;
655 /* get NICSide BAR Index */
656 if (opae_manager_get_eth_group_region_info(mgr, 1,
657 &opae_nside_eth_info)) {
660 nside_bar_idx = opae_nside_eth_info.mem_idx;
662 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
663 nside_bar_idx >= PCI_MAX_RESOURCE ||
664 lside_bar_idx == nside_bar_idx)
667 /* fill LineSide BAR Index */
668 afu_dev->mem_resource[lside_bar_idx].phys_addr =
669 opae_lside_eth_info.phys_addr;
670 afu_dev->mem_resource[lside_bar_idx].len =
671 opae_lside_eth_info.len;
672 afu_dev->mem_resource[lside_bar_idx].addr =
673 opae_lside_eth_info.addr;
675 /* fill NICSide BAR Index */
676 afu_dev->mem_resource[nside_bar_idx].phys_addr =
677 opae_nside_eth_info.phys_addr;
678 afu_dev->mem_resource[nside_bar_idx].len =
679 opae_nside_eth_info.len;
680 afu_dev->mem_resource[nside_bar_idx].addr =
681 opae_nside_eth_info.addr;
686 ifpga_rawdev_configure(const struct rte_rawdev *dev,
687 rte_rawdev_obj_t config)
689 IFPGA_RAWDEV_PMD_FUNC_TRACE();
691 RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
693 return config ? 0 : 1;
697 ifpga_rawdev_start(struct rte_rawdev *dev)
700 struct opae_adapter *adapter;
702 IFPGA_RAWDEV_PMD_FUNC_TRACE();
704 RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
706 adapter = ifpga_rawdev_get_priv(dev);
714 ifpga_rawdev_stop(struct rte_rawdev *dev)
720 ifpga_rawdev_close(struct rte_rawdev *dev)
726 ifpga_rawdev_reset(struct rte_rawdev *dev)
732 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size,
736 struct opae_adapter *adapter;
737 struct opae_manager *mgr;
738 struct opae_accelerator *acc;
739 struct opae_bridge *br;
742 adapter = ifpga_rawdev_get_priv(raw_dev);
746 mgr = opae_adapter_get_mgr(adapter);
750 acc = opae_adapter_get_acc(adapter, port_id);
754 br = opae_acc_get_br(acc);
758 ret = opae_manager_flash(mgr, port_id, buffer, size, status);
760 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
764 ret = opae_bridge_reset(br);
766 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
767 __func__, port_id, ret);
775 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
776 const char *file_name)
778 struct stat file_stat;
788 file_fd = open(file_name, O_RDONLY);
790 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
791 __func__, file_name);
792 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
795 ret = stat(file_name, &file_stat);
797 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
802 buffer_size = file_stat.st_size;
803 if (buffer_size <= 0) {
808 IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
809 buffer = rte_malloc(NULL, buffer_size, 0);
815 /*read the raw data*/
816 if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
822 ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
823 IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
824 ret ? "failed" : "success");
840 ifpga_rawdev_pr(struct rte_rawdev *dev,
841 rte_rawdev_obj_t pr_conf)
843 struct opae_adapter *adapter;
844 struct opae_manager *mgr;
845 struct opae_board_info *info;
846 struct rte_afu_pr_conf *afu_pr_conf;
849 struct opae_accelerator *acc;
851 IFPGA_RAWDEV_PMD_FUNC_TRACE();
853 adapter = ifpga_rawdev_get_priv(dev);
860 afu_pr_conf = pr_conf;
862 if (afu_pr_conf->pr_enable) {
863 ret = rte_fpga_do_pr(dev,
864 afu_pr_conf->afu_id.port,
865 afu_pr_conf->bs_path);
867 IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
872 mgr = opae_adapter_get_mgr(adapter);
874 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
878 if (ifpga_mgr_ops.get_board_info(mgr, &info)) {
879 IFPGA_RAWDEV_PMD_ERR("ifpga manager get_board_info fail!");
883 if (info->lightweight) {
884 /* set uuid to all 0, when fpga is lightweight image */
885 memset(&afu_pr_conf->afu_id.uuid.uuid_low, 0, sizeof(u64));
886 memset(&afu_pr_conf->afu_id.uuid.uuid_high, 0, sizeof(u64));
888 acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
892 ret = opae_acc_get_uuid(acc, &uuid);
896 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b,
898 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high, uuid.b + 8,
901 IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n",
903 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
904 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
910 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
911 const char *attr_name, uint64_t *attr_value)
913 struct opae_adapter *adapter;
914 struct opae_manager *mgr;
915 struct opae_retimer_info opae_rtm_info;
916 struct opae_retimer_status opae_rtm_status;
917 struct opae_eth_group_info opae_eth_grp_info;
918 struct opae_eth_group_region_info opae_eth_grp_reg_info;
919 int eth_group_num = 0;
920 uint64_t port_link_bitmap = 0, port_link_bit;
923 #define MAX_PORT_PER_RETIMER 4
925 IFPGA_RAWDEV_PMD_FUNC_TRACE();
927 if (!dev || !attr_name || !attr_value) {
928 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
932 adapter = ifpga_rawdev_get_priv(dev);
934 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
938 mgr = opae_adapter_get_mgr(adapter);
940 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
944 /* currently, eth_group_num is always 2 */
945 eth_group_num = opae_manager_get_eth_group_nums(mgr);
946 if (eth_group_num < 0)
949 if (!strcmp(attr_name, "LineSideBaseMAC")) {
950 /* Currently FPGA not implement, so just set all zeros*/
951 *attr_value = (uint64_t)0;
954 if (!strcmp(attr_name, "LineSideMACType")) {
955 /* eth_group 0 on FPGA connect to LineSide */
956 if (opae_manager_get_eth_group_info(mgr, 0,
959 switch (opae_eth_grp_info.speed) {
962 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
966 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
970 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
975 if (!strcmp(attr_name, "LineSideLinkSpeed")) {
976 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
978 switch (opae_rtm_status.speed) {
981 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
985 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
989 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
993 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
997 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
1001 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
1005 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1007 case MXD_SPEED_UNKNOWN:
1009 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1013 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1018 if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
1019 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1021 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
1024 if (!strcmp(attr_name, "LineSideLinkPortNum")) {
1025 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1027 uint64_t tmp = (uint64_t)opae_rtm_info.ports_per_retimer *
1028 (uint64_t)opae_rtm_info.nums_retimer;
1032 if (!strcmp(attr_name, "LineSideLinkStatus")) {
1033 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1035 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1039 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
1040 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
1041 p = i * MAX_PORT_PER_RETIMER;
1042 for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
1044 IFPGA_BIT_SET(port_link_bit, (p+j));
1045 port_link_bit &= port_link_bitmap;
1047 IFPGA_BIT_SET((*attr_value), q);
1053 if (!strcmp(attr_name, "LineSideBARIndex")) {
1054 /* eth_group 0 on FPGA connect to LineSide */
1055 if (opae_manager_get_eth_group_region_info(mgr, 0,
1056 &opae_eth_grp_reg_info))
1058 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1061 if (!strcmp(attr_name, "NICSideMACType")) {
1062 /* eth_group 1 on FPGA connect to NicSide */
1063 if (opae_manager_get_eth_group_info(mgr, 1,
1064 &opae_eth_grp_info))
1066 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1069 if (!strcmp(attr_name, "NICSideLinkSpeed")) {
1070 /* eth_group 1 on FPGA connect to NicSide */
1071 if (opae_manager_get_eth_group_info(mgr, 1,
1072 &opae_eth_grp_info))
1074 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1077 if (!strcmp(attr_name, "NICSideLinkPortNum")) {
1078 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1080 uint64_t tmp = (uint64_t)opae_rtm_info.nums_fvl *
1081 (uint64_t)opae_rtm_info.ports_per_fvl;
1085 if (!strcmp(attr_name, "NICSideLinkStatus"))
1087 if (!strcmp(attr_name, "NICSideBARIndex")) {
1088 /* eth_group 1 on FPGA connect to NicSide */
1089 if (opae_manager_get_eth_group_region_info(mgr, 1,
1090 &opae_eth_grp_reg_info))
1092 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1096 IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
1100 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
1101 .dev_info_get = ifpga_rawdev_info_get,
1102 .dev_configure = ifpga_rawdev_configure,
1103 .dev_start = ifpga_rawdev_start,
1104 .dev_stop = ifpga_rawdev_stop,
1105 .dev_close = ifpga_rawdev_close,
1106 .dev_reset = ifpga_rawdev_reset,
1108 .queue_def_conf = NULL,
1109 .queue_setup = NULL,
1110 .queue_release = NULL,
1112 .attr_get = ifpga_rawdev_get_attr,
1115 .enqueue_bufs = NULL,
1116 .dequeue_bufs = NULL,
1121 .xstats_get_names = NULL,
1122 .xstats_get_by_name = NULL,
1123 .xstats_reset = NULL,
1125 .firmware_status_get = NULL,
1126 .firmware_version_get = NULL,
1127 .firmware_load = ifpga_rawdev_pr,
1128 .firmware_unload = NULL,
1130 .dev_selftest = NULL,
1134 ifpga_get_fme_error_prop(struct opae_manager *mgr,
1135 u64 prop_id, u64 *val)
1137 struct feature_prop prop;
1139 prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1140 prop.prop_id = prop_id;
1142 if (opae_manager_ifpga_get_prop(mgr, &prop))
1151 ifpga_set_fme_error_prop(struct opae_manager *mgr,
1152 u64 prop_id, u64 val)
1154 struct feature_prop prop;
1156 prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1157 prop.prop_id = prop_id;
1161 if (opae_manager_ifpga_set_prop(mgr, &prop))
1168 fme_err_read_seu_emr(struct opae_manager *mgr)
1173 ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
1177 IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%" PRIx64 "\n", val);
1179 ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
1183 IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%" PRIx64 "\n", val);
1188 static int fme_clear_warning_intr(struct opae_manager *mgr)
1192 if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
1195 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1197 if ((val & 0x40) != 0)
1198 IFPGA_RAWDEV_PMD_INFO("clean not done\n");
1203 static int fme_clean_fme_error(struct opae_manager *mgr)
1207 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1210 IFPGA_RAWDEV_PMD_DEBUG("before clean 0x%" PRIx64 "\n", val);
1212 ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_CLEAR, val);
1214 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1217 IFPGA_RAWDEV_PMD_DEBUG("after clean 0x%" PRIx64 "\n", val);
1223 fme_err_handle_error0(struct opae_manager *mgr)
1225 struct feature_fme_error0 fme_error0;
1228 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1231 if (fme_clean_fme_error(mgr))
1234 fme_error0.csr = val;
1236 if (fme_error0.fabric_err)
1237 IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
1238 else if (fme_error0.fabfifo_overflow)
1239 IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
1240 else if (fme_error0.afu_acc_mode_err)
1241 IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
1242 else if (fme_error0.pcie0cdc_parity_err)
1243 IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
1244 else if (fme_error0.cvlcdc_parity_err)
1245 IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
1246 else if (fme_error0.fpgaseuerr)
1247 fme_err_read_seu_emr(mgr);
1249 /* clean the errors */
1250 if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
1257 fme_err_handle_catfatal_error(struct opae_manager *mgr)
1259 struct feature_fme_ras_catfaterror fme_catfatal;
1262 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
1265 fme_catfatal.csr = val;
1267 if (fme_catfatal.cci_fatal_err)
1268 IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
1269 else if (fme_catfatal.fabric_fatal_err)
1270 IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
1271 else if (fme_catfatal.pcie_poison_err)
1272 IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
1273 else if (fme_catfatal.inject_fata_err)
1274 IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
1275 else if (fme_catfatal.crc_catast_err)
1276 IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
1277 else if (fme_catfatal.injected_catast_err)
1278 IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
1279 else if (fme_catfatal.bmc_seu_catast_err)
1280 fme_err_read_seu_emr(mgr);
1286 fme_err_handle_nonfaterror(struct opae_manager *mgr)
1288 struct feature_fme_ras_nonfaterror nonfaterr;
1291 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1294 nonfaterr.csr = val;
1296 if (nonfaterr.temp_thresh_ap1)
1297 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP1\n");
1298 else if (nonfaterr.temp_thresh_ap2)
1299 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP2\n");
1300 else if (nonfaterr.pcie_error)
1301 IFPGA_RAWDEV_PMD_INFO("an error has occurred in pcie\n");
1302 else if (nonfaterr.portfatal_error)
1303 IFPGA_RAWDEV_PMD_INFO("fatal error occurred in AFU port.\n");
1304 else if (nonfaterr.proc_hot)
1305 IFPGA_RAWDEV_PMD_INFO("a ProcHot event\n");
1306 else if (nonfaterr.afu_acc_mode_err)
1307 IFPGA_RAWDEV_PMD_INFO("an AFU PF/VF access mismatch\n");
1308 else if (nonfaterr.injected_nonfata_err) {
1309 IFPGA_RAWDEV_PMD_INFO("Injected Warning Error\n");
1310 fme_clear_warning_intr(mgr);
1311 } else if (nonfaterr.temp_thresh_AP6)
1312 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP6\n");
1313 else if (nonfaterr.power_thresh_AP1)
1314 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP1\n");
1315 else if (nonfaterr.power_thresh_AP2)
1316 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP2\n");
1317 else if (nonfaterr.mbp_err)
1318 IFPGA_RAWDEV_PMD_INFO("an MBP event\n");
1324 fme_interrupt_handler(void *param)
1326 struct opae_manager *mgr = (struct opae_manager *)param;
1328 IFPGA_RAWDEV_PMD_INFO("%s interrupt occurred\n", __func__);
1330 fme_err_handle_error0(mgr);
1331 fme_err_handle_nonfaterror(mgr);
1332 fme_err_handle_catfatal_error(mgr);
1336 ifpga_unregister_msix_irq(enum ifpga_irq_type type,
1337 int vec_start, rte_intr_callback_fn handler, void *arg)
1339 struct rte_intr_handle intr_handle;
1341 if (type == IFPGA_FME_IRQ)
1342 intr_handle = ifpga_irq_handle[0];
1343 else if (type == IFPGA_AFU_IRQ)
1344 intr_handle = ifpga_irq_handle[vec_start + 1];
1346 rte_intr_efd_disable(&intr_handle);
1348 return rte_intr_callback_unregister(&intr_handle,
1353 ifpga_register_msix_irq(struct rte_rawdev *dev, int port_id,
1354 enum ifpga_irq_type type, int vec_start, int count,
1355 rte_intr_callback_fn handler, const char *name,
1359 struct rte_intr_handle intr_handle;
1360 struct opae_adapter *adapter;
1361 struct opae_manager *mgr;
1362 struct opae_accelerator *acc;
1364 adapter = ifpga_rawdev_get_priv(dev);
1368 mgr = opae_adapter_get_mgr(adapter);
1372 if (type == IFPGA_FME_IRQ) {
1373 intr_handle = ifpga_irq_handle[0];
1375 } else if (type == IFPGA_AFU_IRQ)
1376 intr_handle = ifpga_irq_handle[vec_start + 1];
1378 intr_handle.type = RTE_INTR_HANDLE_VFIO_MSIX;
1380 ret = rte_intr_efd_enable(&intr_handle, count);
1384 intr_handle.fd = intr_handle.efds[0];
1386 IFPGA_RAWDEV_PMD_DEBUG("register %s irq, vfio_fd=%d, fd=%d\n",
1387 name, intr_handle.vfio_dev_fd,
1390 if (type == IFPGA_FME_IRQ) {
1391 struct fpga_fme_err_irq_set err_irq_set;
1392 err_irq_set.evtfd = intr_handle.efds[0];
1394 ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
1397 } else if (type == IFPGA_AFU_IRQ) {
1398 acc = opae_adapter_get_acc(adapter, port_id);
1402 ret = opae_acc_set_irq(acc, vec_start, count, intr_handle.efds);
1407 /* register interrupt handler using DPDK API */
1408 ret = rte_intr_callback_register(&intr_handle,
1409 handler, (void *)arg);
1413 IFPGA_RAWDEV_PMD_INFO("success register %s interrupt\n", name);
1419 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
1423 struct rte_rawdev *rawdev = NULL;
1424 struct ifpga_rawdev *dev = NULL;
1425 struct opae_adapter *adapter = NULL;
1426 struct opae_manager *mgr = NULL;
1427 struct opae_adapter_data_pci *data = NULL;
1428 char name[RTE_RAWDEV_NAME_MAX_LEN];
1432 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1437 memset(name, 0, sizeof(name));
1438 snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%02x:%02x.%x",
1439 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1441 IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
1443 /* Allocate device structure */
1444 rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
1446 if (rawdev == NULL) {
1447 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
1452 ipn3ke_bridge_func.get_ifpga_rawdev = ifpga_rawdev_get;
1453 ipn3ke_bridge_func.set_i40e_sw_dev = rte_pmd_i40e_set_switch_dev;
1455 dev = ifpga_rawdev_allocate(rawdev);
1457 IFPGA_RAWDEV_PMD_ERR("Unable to allocate ifpga_rawdevice");
1461 dev->aer_enable = 0;
1463 /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
1464 data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
1470 /* init opae_adapter_data_pci for device specific information */
1471 for (i = 0; i < PCI_MAX_RESOURCE; i++) {
1472 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
1473 data->region[i].len = pci_dev->mem_resource[i].len;
1474 data->region[i].addr = pci_dev->mem_resource[i].addr;
1476 data->device_id = pci_dev->id.device_id;
1477 data->vendor_id = pci_dev->id.vendor_id;
1478 data->bus = pci_dev->addr.bus;
1479 data->devid = pci_dev->addr.devid;
1480 data->function = pci_dev->addr.function;
1481 data->vfio_dev_fd = pci_dev->intr_handle.vfio_dev_fd;
1483 adapter = rawdev->dev_private;
1484 /* create a opae_adapter based on above device data */
1485 ret = opae_adapter_init(adapter, pci_dev->device.name, data);
1488 goto free_adapter_data;
1491 rawdev->dev_ops = &ifpga_rawdev_ops;
1492 rawdev->device = &pci_dev->device;
1493 rawdev->driver_name = pci_dev->driver->driver.name;
1495 /* must enumerate the adapter before use it */
1496 ret = opae_adapter_enumerate(adapter);
1498 goto free_adapter_data;
1500 /* get opae_manager to rawdev */
1501 mgr = opae_adapter_get_mgr(adapter);
1504 IFPGA_RAWDEV_PMD_INFO("this is a PF function");
1507 ret = ifpga_register_msix_irq(rawdev, 0, IFPGA_FME_IRQ, 0, 0,
1508 fme_interrupt_handler, "fme_irq", mgr);
1510 goto free_adapter_data;
1516 opae_adapter_data_free(data);
1519 rte_rawdev_pmd_release(rawdev);
1525 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
1528 struct rte_rawdev *rawdev;
1529 char name[RTE_RAWDEV_NAME_MAX_LEN];
1530 struct opae_adapter *adapter;
1531 struct opae_manager *mgr;
1534 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1539 memset(name, 0, sizeof(name));
1540 snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%x:%02x.%x",
1541 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1543 IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
1544 name, rte_socket_id());
1546 rawdev = rte_rawdev_pmd_get_named_dev(name);
1548 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
1552 adapter = ifpga_rawdev_get_priv(rawdev);
1556 mgr = opae_adapter_get_mgr(adapter);
1560 if (ifpga_unregister_msix_irq(IFPGA_FME_IRQ, 0,
1561 fme_interrupt_handler, mgr))
1564 opae_adapter_data_free(adapter->data);
1565 opae_adapter_free(adapter);
1567 /* rte_rawdev_close is called by pmd_release */
1568 ret = rte_rawdev_pmd_release(rawdev);
1570 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
1576 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1577 struct rte_pci_device *pci_dev)
1579 IFPGA_RAWDEV_PMD_FUNC_TRACE();
1580 return ifpga_rawdev_create(pci_dev, rte_socket_id());
1584 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
1586 ifpga_monitor_stop_func();
1587 return ifpga_rawdev_destroy(pci_dev);
1590 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
1591 .id_table = pci_ifpga_map,
1592 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1593 .probe = ifpga_rawdev_pci_probe,
1594 .remove = ifpga_rawdev_pci_remove,
1597 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1598 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1599 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
1601 RTE_INIT(ifpga_rawdev_init_log)
1603 ifpga_rawdev_logtype = rte_log_register("driver.raw.init");
1604 if (ifpga_rawdev_logtype >= 0)
1605 rte_log_set_level(ifpga_rawdev_logtype, RTE_LOG_NOTICE);
1608 static const char * const valid_args[] = {
1609 #define IFPGA_ARG_NAME "ifpga"
1611 #define IFPGA_ARG_PORT "port"
1613 #define IFPGA_AFU_BTS "afu_bts"
1618 static int ifpga_rawdev_get_string_arg(const char *key __rte_unused,
1619 const char *value, void *extra_args)
1622 if (!value || !extra_args)
1625 size = strlen(value) + 1;
1626 *(char **)extra_args = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
1627 if (!*(char **)extra_args)
1630 strlcpy(*(char **)extra_args, value, size);
1635 ifpga_cfg_probe(struct rte_vdev_device *dev)
1637 struct rte_devargs *devargs;
1638 struct rte_kvargs *kvlist = NULL;
1639 struct rte_rawdev *rawdev = NULL;
1640 struct ifpga_rawdev *ifpga_dev;
1644 char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1647 devargs = dev->device.devargs;
1649 kvlist = rte_kvargs_parse(devargs->args, valid_args);
1651 IFPGA_RAWDEV_PMD_LOG(ERR, "error when parsing param");
1655 if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
1656 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
1657 &ifpga_rawdev_get_string_arg,
1659 IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1664 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1669 if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
1670 if (rte_kvargs_process(kvlist,
1672 &rte_ifpga_get_integer32_arg,
1674 IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1679 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1684 memset(dev_name, 0, sizeof(dev_name));
1685 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", name);
1686 rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1689 ifpga_dev = ifpga_rawdev_get(rawdev);
1693 ifpga_rawdev_fill_info(ifpga_dev, bdf);
1695 ifpga_monitor_start_func();
1697 memset(dev_name, 0, sizeof(dev_name));
1698 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1701 ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
1702 dev_name, devargs->args);
1705 rte_kvargs_free(kvlist);
1713 ifpga_cfg_remove(struct rte_vdev_device *vdev)
1715 IFPGA_RAWDEV_PMD_INFO("Remove ifpga_cfg %p",
1721 static struct rte_vdev_driver ifpga_cfg_driver = {
1722 .probe = ifpga_cfg_probe,
1723 .remove = ifpga_cfg_remove,
1726 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
1727 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
1728 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,