drivers/raw/ifpga/ifpga_rawdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2018 Intel Corporation
   3  */
   4
   5 #include <string.h>
   6 #include <dirent.h>
   7 #include <sys/stat.h>
   8 #include <unistd.h>
   9 #include <sys/types.h>
  10 #include <fcntl.h>
  11 #include <sys/ioctl.h>
  12 #include <sys/epoll.h>
  13 #include <rte_log.h>
  14 #include <rte_bus.h>
  15 #include <rte_malloc.h>
  16 #include <rte_devargs.h>
  17 #include <rte_memcpy.h>
  18 #include <rte_pci.h>
  19 #include <rte_bus_pci.h>
  20 #include <rte_kvargs.h>
  21 #include <rte_alarm.h>
  22 #include <rte_interrupts.h>
  23 #include <rte_errno.h>
  24 #include <rte_per_lcore.h>
  25 #include <rte_memory.h>
  26 #include <rte_memzone.h>
  27 #include <rte_eal.h>
  28 #include <rte_common.h>
  29 #include <rte_bus_vdev.h>
  30 #include <rte_string_fns.h>
  31 #include <rte_pmd_i40e.h>
  32
  33 #include "base/opae_hw_api.h"
  34 #include "base/opae_ifpga_hw_api.h"
  35 #include "base/ifpga_api.h"
  36 #include "rte_rawdev.h"
  37 #include "rte_rawdev_pmd.h"
  38 #include "rte_bus_ifpga.h"
  39 #include "ifpga_common.h"
  40 #include "ifpga_logs.h"
  41 #include "ifpga_rawdev.h"
  42 #include "ipn3ke_rawdev_api.h"
  43
  44 #define PCI_VENDOR_ID_INTEL          0x8086
  45 /* PCI Device ID */
  46 #define PCIE_DEVICE_ID_PF_INT_5_X    0xBCBD
  47 #define PCIE_DEVICE_ID_PF_INT_6_X    0xBCC0
  48 #define PCIE_DEVICE_ID_PF_DSC_1_X    0x09C4
  49 #define PCIE_DEVICE_ID_PAC_N3000     0x0B30
  50 #define PCIE_DEVICE_ID_PAC_N6000     0xBCCE
  51 /* VF Device */
  52 #define PCIE_DEVICE_ID_VF_INT_5_X    0xBCBF
  53 #define PCIE_DEVICE_ID_VF_INT_6_X    0xBCC1
  54 #define PCIE_DEVICE_ID_VF_DSC_1_X    0x09C5
  55 #define PCIE_DEVICE_ID_VF_PAC_N3000  0x0B31
  56 #define PCIE_DEVICE_ID_VF_PAC_N6000  0xBCCF
  57 #define RTE_MAX_RAW_DEVICE           10
  58
  59 static const struct rte_pci_id pci_ifpga_map[] = {
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N6000),},
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N6000),},
  70         { .vendor_id = 0, /* sentinel */ },
  71 };
  72
  73 static struct ifpga_rawdev ifpga_rawdevices[IFPGA_RAWDEV_NUM];
  74
  75 static int ifpga_monitor_refcnt;
  76 static pthread_t ifpga_monitor_start_thread;
  77
  78 static struct ifpga_rawdev *
  79 ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
  80 static int set_surprise_link_check_aer(
  81                 struct ifpga_rawdev *ifpga_rdev, int force_disable);
  82 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
  83                                               int start, uint32_t cap);
  84 static int ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap);
  85 static void fme_interrupt_handler(void *param);
  86
  87 struct ifpga_rawdev *
  88 ifpga_rawdev_get(const struct rte_rawdev *rawdev)
  89 {
  90         struct ifpga_rawdev *dev;
  91         unsigned int i;
  92
  93         if (rawdev == NULL)
  94                 return NULL;
  95
  96         for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
  97                 dev = &ifpga_rawdevices[i];
  98                 if (dev->rawdev == rawdev)
  99                         return dev;
 100         }
 101
 102         return NULL;
 103 }
 104
 105 static inline uint8_t
 106 ifpga_rawdev_find_free_device_index(void)
 107 {
 108         uint16_t dev_id;
 109
 110         for (dev_id = 0; dev_id < IFPGA_RAWDEV_NUM; dev_id++) {
 111                 if (ifpga_rawdevices[dev_id].rawdev == NULL)
 112                         return dev_id;
 113         }
 114
 115         return IFPGA_RAWDEV_NUM;
 116 }
 117
 118 static struct ifpga_rawdev *
 119 ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
 120 {
 121         struct ifpga_rawdev *dev;
 122         uint16_t dev_id;
 123         int i = 0;
 124
 125         dev = ifpga_rawdev_get(rawdev);
 126         if (dev != NULL) {
 127                 IFPGA_RAWDEV_PMD_ERR("Event device already allocated!");
 128                 return NULL;
 129         }
 130
 131         dev_id = ifpga_rawdev_find_free_device_index();
 132         if (dev_id == IFPGA_RAWDEV_NUM) {
 133                 IFPGA_RAWDEV_PMD_ERR("Reached maximum number of raw devices");
 134                 return NULL;
 135         }
 136
 137         dev = &ifpga_rawdevices[dev_id];
 138         dev->rawdev = rawdev;
 139         dev->dev_id = dev_id;
 140         for (i = 0; i < IFPGA_MAX_IRQ; i++)
 141                 dev->intr_handle[i] = NULL;
 142         dev->poll_enabled = 0;
 143         for (i = 0; i < IFPGA_MAX_VDEV; i++)
 144                 dev->vdev_name[i] = NULL;
 145
 146         return dev;
 147 }
 148
 149 static int
 150 ifpga_pci_find_next_ext_capability(unsigned int fd, int start, uint32_t cap)
 151 {
 152         uint32_t header;
 153         int ttl;
 154         int pos = RTE_PCI_CFG_SPACE_SIZE;
 155         int ret;
 156
 157         /* minimum 8 bytes per capability */
 158         ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
 159
 160         if (start)
 161                 pos = start;
 162         ret = pread(fd, &header, sizeof(header), pos);
 163         if (ret == -1)
 164                 return -1;
 165
 166         /*
 167          * If we have no capabilities, this is indicated by cap ID,
 168          * cap version and next pointer all being 0.
 169          */
 170         if (header == 0)
 171                 return 0;
 172
 173         while (ttl-- > 0) {
 174                 if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
 175                         return pos;
 176
 177                 pos = RTE_PCI_EXT_CAP_NEXT(header);
 178                 if (pos < RTE_PCI_CFG_SPACE_SIZE)
 179                         break;
 180                 ret = pread(fd, &header, sizeof(header), pos);
 181                 if (ret == -1)
 182                         return -1;
 183         }
 184
 185         return 0;
 186 }
 187
 188 static int
 189 ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap)
 190 {
 191         return ifpga_pci_find_next_ext_capability(fd, 0, cap);
 192 }
 193
 194 static int ifpga_get_dev_vendor_id(const char *bdf,
 195         uint32_t *dev_id, uint32_t *vendor_id)
 196 {
 197         int fd;
 198         char path[1024];
 199         int ret;
 200         uint32_t header;
 201
 202         strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
 203         strlcat(path, bdf, sizeof(path));
 204         strlcat(path, "/config", sizeof(path));
 205         fd = open(path, O_RDWR);
 206         if (fd < 0)
 207                 return -1;
 208         ret = pread(fd, &header, sizeof(header), 0);
 209         if (ret == -1) {
 210                 close(fd);
 211                 return -1;
 212         }
 213         (*vendor_id) = header & 0xffff;
 214         (*dev_id) = (header >> 16) & 0xffff;
 215         close(fd);
 216
 217         return 0;
 218 }
 219
 220 static int ifpga_rawdev_fill_info(struct ifpga_rawdev *ifpga_dev)
 221 {
 222         struct opae_adapter *adapter = NULL;
 223         char path[1024] = "/sys/bus/pci/devices/";
 224         char link[1024], link1[1024];
 225         char dir[1024] = "/sys/devices/";
 226         char *c;
 227         int ret;
 228         char sub_brg_bdf[4][16] = {{0}};
 229         int point;
 230         DIR *dp = NULL;
 231         struct dirent *entry;
 232         int i, j;
 233
 234         unsigned int dom, bus, dev;
 235         int func;
 236         uint32_t dev_id = 0;
 237         uint32_t vendor_id = 0;
 238
 239         adapter = ifpga_dev ? ifpga_rawdev_get_priv(ifpga_dev->rawdev) : NULL;
 240         if (!adapter)
 241                 return -ENODEV;
 242
 243         strlcat(path, adapter->name, sizeof(path));
 244         memset(link, 0, sizeof(link));
 245         memset(link1, 0, sizeof(link1));
 246         ret = readlink(path, link, (sizeof(link)-1));
 247         if ((ret < 0) || ((unsigned int)ret > (sizeof(link)-1)))
 248                 return -1;
 249         link[ret] = 0;   /* terminate string with null character */
 250         strlcpy(link1, link, sizeof(link1));
 251         memset(ifpga_dev->parent_bdf, 0, 16);
 252         point = strlen(link);
 253         if (point < 39)
 254                 return -1;
 255         point -= 39;
 256         link[point] = 0;
 257         if (point < 12)
 258                 return -1;
 259         point -= 12;
 260         rte_memcpy(ifpga_dev->parent_bdf, &link[point], 12);
 261
 262         point = strlen(link1);
 263         if (point < 26)
 264                 return -1;
 265         point -= 26;
 266         link1[point] = 0;
 267         if (point < 12)
 268                 return -1;
 269         point -= 12;
 270         c = strchr(link1, 'p');
 271         if (!c)
 272                 return -1;
 273         strlcat(dir, c, sizeof(dir));
 274
 275         /* scan folder */
 276         dp = opendir(dir);
 277         if (dp == NULL)
 278                 return -1;
 279         i = 0;
 280         while ((entry = readdir(dp)) != NULL) {
 281                 if (i >= 4)
 282                         break;
 283                 if (entry->d_name[0] == '.')
 284                         continue;
 285                 if (strlen(entry->d_name) > 12)
 286                         continue;
 287                 if (sscanf(entry->d_name, "%x:%x:%x.%d",
 288                         &dom, &bus, &dev, &func) < 4)
 289                         continue;
 290                 else {
 291                         strlcpy(sub_brg_bdf[i],
 292                                 entry->d_name,
 293                                 sizeof(sub_brg_bdf[i]));
 294                         i++;
 295                 }
 296         }
 297         closedir(dp);
 298
 299         /* get fpga and fvl */
 300         j = 0;
 301         for (i = 0; i < 4; i++) {
 302                 strlcpy(link, dir, sizeof(link));
 303                 strlcat(link, "/", sizeof(link));
 304                 strlcat(link, sub_brg_bdf[i], sizeof(link));
 305                 dp = opendir(link);
 306                 if (dp == NULL)
 307                         return -1;
 308                 while ((entry = readdir(dp)) != NULL) {
 309                         if (j >= 8)
 310                                 break;
 311                         if (entry->d_name[0] == '.')
 312                                 continue;
 313
 314                         if (strlen(entry->d_name) > 12)
 315                                 continue;
 316                         if (sscanf(entry->d_name, "%x:%x:%x.%d",
 317                                 &dom, &bus, &dev, &func) < 4)
 318                                 continue;
 319                         else {
 320                                 if (ifpga_get_dev_vendor_id(entry->d_name,
 321                                         &dev_id, &vendor_id))
 322                                         continue;
 323                                 if (vendor_id == 0x8086 &&
 324                                         (dev_id == 0x0CF8 ||
 325                                         dev_id == 0x0D58 ||
 326                                         dev_id == 0x1580)) {
 327                                         strlcpy(ifpga_dev->fvl_bdf[j],
 328                                                 entry->d_name,
 329                                                 sizeof(ifpga_dev->fvl_bdf[j]));
 330                                         j++;
 331                                 }
 332                         }
 333                 }
 334                 closedir(dp);
 335         }
 336
 337         return 0;
 338 }
 339
 340 #define HIGH_FATAL(_sens, value)\
 341         (((_sens)->flags & OPAE_SENSOR_HIGH_FATAL_VALID) &&\
 342          (value > (_sens)->high_fatal))
 343
 344 #define HIGH_WARN(_sens, value)\
 345         (((_sens)->flags & OPAE_SENSOR_HIGH_WARN_VALID) &&\
 346          (value > (_sens)->high_warn))
 347
 348 #define LOW_FATAL(_sens, value)\
 349         (((_sens)->flags & OPAE_SENSOR_LOW_FATAL_VALID) &&\
 350          (value > (_sens)->low_fatal))
 351
 352 #define LOW_WARN(_sens, value)\
 353         (((_sens)->flags & OPAE_SENSOR_LOW_WARN_VALID) &&\
 354          (value > (_sens)->low_warn))
 355
 356 #define AUX_VOLTAGE_WARN 11400
 357
 358 static int
 359 ifpga_monitor_sensor(struct rte_rawdev *raw_dev,
 360                bool *gsd_start)
 361 {
 362         struct opae_adapter *adapter;
 363         struct opae_manager *mgr;
 364         struct opae_sensor_info *sensor;
 365         unsigned int value;
 366         int ret;
 367
 368         adapter = ifpga_rawdev_get_priv(raw_dev);
 369         if (!adapter)
 370                 return -ENODEV;
 371
 372         mgr = opae_adapter_get_mgr(adapter);
 373         if (!mgr || !mgr->sensor_list)
 374                 return -ENODEV;
 375
 376         opae_mgr_for_each_sensor(mgr, sensor) {
 377                 if (!(sensor->flags & OPAE_SENSOR_VALID))
 378                         goto fail;
 379
 380                 ret = opae_mgr_get_sensor_value(mgr, sensor, &value);
 381                 if (ret)
 382                         goto fail;
 383
 384                 if (value == 0xdeadbeef) {
 385                         IFPGA_RAWDEV_PMD_DEBUG("dev_id %d sensor %s value %x\n",
 386                                         raw_dev->dev_id, sensor->name, value);
 387                         continue;
 388                 }
 389
 390                 /* monitor temperature sensors */
 391                 if (!strcmp(sensor->name, "Board Temperature") ||
 392                                 !strcmp(sensor->name, "FPGA Die Temperature")) {
 393                         IFPGA_RAWDEV_PMD_DEBUG("read sensor %s %d %d %d\n",
 394                                         sensor->name, value, sensor->high_warn,
 395                                         sensor->high_fatal);
 396
 397                         if (HIGH_WARN(sensor, value) ||
 398                                 LOW_WARN(sensor, value)) {
 399                                 IFPGA_RAWDEV_PMD_INFO("%s reach threshold %d\n",
 400                                         sensor->name, value);
 401                                 *gsd_start = true;
 402                                 break;
 403                         }
 404                 }
 405
 406                 /* monitor 12V AUX sensor */
 407                 if (!strcmp(sensor->name, "12V AUX Voltage")) {
 408                         if (value < AUX_VOLTAGE_WARN) {
 409                                 IFPGA_RAWDEV_PMD_INFO(
 410                                         "%s reach threshold %d mV\n",
 411                                         sensor->name, value);
 412                                 *gsd_start = true;
 413                                 break;
 414                         }
 415                 }
 416         }
 417
 418         return 0;
 419 fail:
 420         return -EFAULT;
 421 }
 422
 423 static int set_surprise_link_check_aer(
 424         struct ifpga_rawdev *ifpga_rdev, int force_disable)
 425 {
 426         struct rte_rawdev *rdev;
 427         int fd = -1;
 428         char path[1024];
 429         int pos;
 430         int ret;
 431         uint32_t data;
 432         bool enable = 0;
 433         uint32_t aer_new0, aer_new1;
 434
 435         if (!ifpga_rdev || !ifpga_rdev->rawdev) {
 436                 printf("\n device does not exist\n");
 437                 return -EFAULT;
 438         }
 439
 440         rdev = ifpga_rdev->rawdev;
 441         if (ifpga_rdev->aer_enable)
 442                 return -EFAULT;
 443         if (ifpga_monitor_sensor(rdev, &enable))
 444                 return -EFAULT;
 445         if (enable || force_disable) {
 446                 IFPGA_RAWDEV_PMD_ERR("Set AER, pls graceful shutdown\n");
 447                 ifpga_rdev->aer_enable = 1;
 448                 /* get bridge fd */
 449                 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
 450                 strlcat(path, ifpga_rdev->parent_bdf, sizeof(path));
 451                 strlcat(path, "/config", sizeof(path));
 452                 fd = open(path, O_RDWR);
 453                 if (fd < 0)
 454                         goto end;
 455                 pos = ifpga_pci_find_ext_capability(fd, RTE_PCI_EXT_CAP_ID_ERR);
 456                 if (!pos)
 457                         goto end;
 458                 /* save previous ECAP_AER+0x08 */
 459                 ret = pread(fd, &data, sizeof(data), pos+0x08);
 460                 if (ret == -1)
 461                         goto end;
 462                 ifpga_rdev->aer_old[0] = data;
 463                 /* save previous ECAP_AER+0x14 */
 464                 ret = pread(fd, &data, sizeof(data), pos+0x14);
 465                 if (ret == -1)
 466                         goto end;
 467                 ifpga_rdev->aer_old[1] = data;
 468
 469                 /* set ECAP_AER+0x08 to 0xFFFFFFFF */
 470                 data = 0xffffffff;
 471                 ret = pwrite(fd, &data, 4, pos+0x08);
 472                 if (ret == -1)
 473                         goto end;
 474                 /* set ECAP_AER+0x14 to 0xFFFFFFFF */
 475                 ret = pwrite(fd, &data, 4, pos+0x14);
 476                 if (ret == -1)
 477                         goto end;
 478
 479                 /* read current ECAP_AER+0x08 */
 480                 ret = pread(fd, &data, sizeof(data), pos+0x08);
 481                 if (ret == -1)
 482                         goto end;
 483                 aer_new0 = data;
 484                 /* read current ECAP_AER+0x14 */
 485                 ret = pread(fd, &data, sizeof(data), pos+0x14);
 486                 if (ret == -1)
 487                         goto end;
 488                 aer_new1 = data;
 489
 490                 if (fd != -1)
 491                         close(fd);
 492
 493                 printf(">>>>>>Set AER %x,%x %x,%x\n",
 494                         ifpga_rdev->aer_old[0], ifpga_rdev->aer_old[1],
 495                         aer_new0, aer_new1);
 496
 497                 return 1;
 498                 }
 499
 500 end:
 501         if (fd != -1)
 502                 close(fd);
 503         return -EFAULT;
 504 }
 505
 506 static void *
 507 ifpga_rawdev_gsd_handle(__rte_unused void *param)
 508 {
 509         struct ifpga_rawdev *ifpga_rdev;
 510         int i;
 511         int gsd_enable, ret;
 512 #define MS 1000
 513
 514         while (__atomic_load_n(&ifpga_monitor_refcnt, __ATOMIC_RELAXED)) {
 515                 gsd_enable = 0;
 516                 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
 517                         ifpga_rdev = &ifpga_rawdevices[i];
 518                         if (ifpga_rdev->poll_enabled) {
 519                                 ret = set_surprise_link_check_aer(ifpga_rdev,
 520                                         gsd_enable);
 521                                 if (ret == 1 && !gsd_enable) {
 522                                         gsd_enable = 1;
 523                                         i = -1;
 524                                 }
 525                         }
 526                 }
 527
 528                 if (gsd_enable)
 529                         printf(">>>>>>Pls Shutdown APP\n");
 530
 531                 rte_delay_us(100 * MS);
 532         }
 533
 534         return NULL;
 535 }
 536
 537 static int
 538 ifpga_monitor_start_func(struct ifpga_rawdev *dev)
 539 {
 540         int ret;
 541
 542         if (!dev)
 543                 return -ENODEV;
 544
 545         ret = ifpga_rawdev_fill_info(dev);
 546         if (ret)
 547                 return ret;
 548
 549         dev->poll_enabled = 1;
 550
 551         if (!__atomic_fetch_add(&ifpga_monitor_refcnt, 1, __ATOMIC_RELAXED)) {
 552                 ret = rte_ctrl_thread_create(&ifpga_monitor_start_thread,
 553                                              "ifpga-monitor", NULL,
 554                                              ifpga_rawdev_gsd_handle, NULL);
 555                 if (ret != 0) {
 556                         ifpga_monitor_start_thread = 0;
 557                         IFPGA_RAWDEV_PMD_ERR(
 558                                 "Fail to create ifpga monitor thread");
 559                         return -1;
 560                 }
 561         }
 562
 563         return 0;
 564 }
 565
 566 static int
 567 ifpga_monitor_stop_func(struct ifpga_rawdev *dev)
 568 {
 569         int ret;
 570
 571         if (!dev || !dev->poll_enabled)
 572                 return 0;
 573
 574         dev->poll_enabled = 0;
 575
 576         if (!__atomic_sub_fetch(&ifpga_monitor_refcnt, 1, __ATOMIC_RELAXED) &&
 577                 ifpga_monitor_start_thread) {
 578                 ret = pthread_cancel(ifpga_monitor_start_thread);
 579                 if (ret)
 580                         IFPGA_RAWDEV_PMD_ERR("Can't cancel the thread");
 581
 582                 ret = pthread_join(ifpga_monitor_start_thread, NULL);
 583                 if (ret)
 584                         IFPGA_RAWDEV_PMD_ERR("Can't join the thread");
 585
 586                 return ret;
 587         }
 588
 589         return 0;
 590 }
 591
 592 static int
 593 ifpga_fill_afu_dev(struct opae_accelerator *acc,
 594                 struct rte_afu_device *afu_dev)
 595 {
 596         struct rte_mem_resource *res = afu_dev->mem_resource;
 597         struct opae_acc_region_info region_info;
 598         struct opae_acc_info info;
 599         unsigned long i;
 600         int ret;
 601
 602         ret = opae_acc_get_info(acc, &info);
 603         if (ret)
 604                 return ret;
 605
 606         if (info.num_regions > PCI_MAX_RESOURCE)
 607                 return -EFAULT;
 608
 609         afu_dev->num_region = info.num_regions;
 610
 611         for (i = 0; i < info.num_regions; i++) {
 612                 region_info.index = i;
 613                 ret = opae_acc_get_region_info(acc, &region_info);
 614                 if (ret)
 615                         return ret;
 616
 617                 if ((region_info.flags & ACC_REGION_MMIO) &&
 618                     (region_info.flags & ACC_REGION_READ) &&
 619                     (region_info.flags & ACC_REGION_WRITE)) {
 620                         res[i].phys_addr = region_info.phys_addr;
 621                         res[i].len = region_info.len;
 622                         res[i].addr = region_info.addr;
 623                 } else
 624                         return -EFAULT;
 625         }
 626
 627         return 0;
 628 }
 629
 630 static int
 631 ifpga_rawdev_info_get(struct rte_rawdev *dev,
 632                       rte_rawdev_obj_t dev_info,
 633                       size_t dev_info_size)
 634 {
 635         struct opae_adapter *adapter;
 636         struct opae_accelerator *acc;
 637         struct rte_afu_device *afu_dev;
 638         struct opae_manager *mgr = NULL;
 639         struct opae_eth_group_region_info opae_lside_eth_info;
 640         struct opae_eth_group_region_info opae_nside_eth_info;
 641         int lside_bar_idx, nside_bar_idx;
 642
 643         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 644
 645         if (!dev_info || dev_info_size != sizeof(*afu_dev)) {
 646                 IFPGA_RAWDEV_PMD_ERR("Invalid request");
 647                 return -EINVAL;
 648         }
 649
 650         adapter = ifpga_rawdev_get_priv(dev);
 651         if (!adapter)
 652                 return -ENOENT;
 653
 654         afu_dev = dev_info;
 655         afu_dev->rawdev = dev;
 656
 657         /* find opae_accelerator and fill info into afu_device */
 658         opae_adapter_for_each_acc(adapter, acc) {
 659                 if (acc->index != afu_dev->id.port)
 660                         continue;
 661
 662                 if (ifpga_fill_afu_dev(acc, afu_dev)) {
 663                         IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
 664                         return -ENOENT;
 665                 }
 666         }
 667
 668         /* get opae_manager to rawdev */
 669         mgr = opae_adapter_get_mgr(adapter);
 670         if (mgr) {
 671                 /* get LineSide BAR Index */
 672                 if (opae_manager_get_eth_group_region_info(mgr, 0,
 673                         &opae_lside_eth_info)) {
 674                         return -ENOENT;
 675                 }
 676                 lside_bar_idx = opae_lside_eth_info.mem_idx;
 677
 678                 /* get NICSide BAR Index */
 679                 if (opae_manager_get_eth_group_region_info(mgr, 1,
 680                         &opae_nside_eth_info)) {
 681                         return -ENOENT;
 682                 }
 683                 nside_bar_idx = opae_nside_eth_info.mem_idx;
 684
 685                 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
 686                         nside_bar_idx >= PCI_MAX_RESOURCE ||
 687                         lside_bar_idx == nside_bar_idx)
 688                         return -ENOENT;
 689
 690                 /* fill LineSide BAR Index */
 691                 afu_dev->mem_resource[lside_bar_idx].phys_addr =
 692                         opae_lside_eth_info.phys_addr;
 693                 afu_dev->mem_resource[lside_bar_idx].len =
 694                         opae_lside_eth_info.len;
 695                 afu_dev->mem_resource[lside_bar_idx].addr =
 696                         opae_lside_eth_info.addr;
 697
 698                 /* fill NICSide BAR Index */
 699                 afu_dev->mem_resource[nside_bar_idx].phys_addr =
 700                         opae_nside_eth_info.phys_addr;
 701                 afu_dev->mem_resource[nside_bar_idx].len =
 702                         opae_nside_eth_info.len;
 703                 afu_dev->mem_resource[nside_bar_idx].addr =
 704                         opae_nside_eth_info.addr;
 705         }
 706         return 0;
 707 }
 708
 709 static int
 710 ifpga_rawdev_configure(const struct rte_rawdev *dev,
 711                 rte_rawdev_obj_t config,
 712                 size_t config_size __rte_unused)
 713 {
 714         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 715
 716         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 717
 718         return config ? 0 : 1;
 719 }
 720
 721 static int
 722 ifpga_rawdev_start(struct rte_rawdev *dev)
 723 {
 724         int ret = 0;
 725         struct opae_adapter *adapter;
 726
 727         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 728
 729         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 730
 731         adapter = ifpga_rawdev_get_priv(dev);
 732         if (!adapter)
 733                 return -ENODEV;
 734
 735         return ret;
 736 }
 737
 738 static void
 739 ifpga_rawdev_stop(struct rte_rawdev *dev)
 740 {
 741         dev->started = 0;
 742 }
 743
 744 static int
 745 ifpga_rawdev_close(struct rte_rawdev *dev)
 746 {
 747         struct ifpga_rawdev *ifpga_rdev = NULL;
 748         struct opae_adapter *adapter;
 749         struct opae_manager *mgr;
 750         char *vdev_name = NULL;
 751         int i, ret = 0;
 752
 753         if (dev) {
 754                 ifpga_rdev = ifpga_rawdev_get(dev);
 755                 if (ifpga_rdev) {
 756                         for (i = 0; i < IFPGA_MAX_VDEV; i++) {
 757                                 vdev_name = ifpga_rdev->vdev_name[i];
 758                                 if (vdev_name)
 759                                         rte_vdev_uninit(vdev_name);
 760                         }
 761                         ifpga_monitor_stop_func(ifpga_rdev);
 762                         ifpga_rdev->rawdev = NULL;
 763                 }
 764                 adapter = ifpga_rawdev_get_priv(dev);
 765                 if (adapter) {
 766                         mgr = opae_adapter_get_mgr(adapter);
 767                         if (ifpga_rdev && mgr) {
 768                                 if (ifpga_unregister_msix_irq(ifpga_rdev,
 769                                         IFPGA_FME_IRQ, 0,
 770                                         fme_interrupt_handler, mgr) < 0)
 771                                         ret = -EINVAL;
 772                         }
 773                         opae_adapter_destroy(adapter);
 774                         opae_adapter_data_free(adapter->data);
 775                 }
 776         }
 777
 778         return ret;
 779 }
 780
 781 static int
 782 ifpga_rawdev_reset(struct rte_rawdev *dev)
 783 {
 784         return dev ? 0:1;
 785 }
 786
 787 static int
 788 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size,
 789                         u64 *status)
 790 {
 791
 792         struct opae_adapter *adapter;
 793         struct opae_manager *mgr;
 794         struct opae_accelerator *acc;
 795         struct opae_bridge *br;
 796         int ret;
 797
 798         adapter = ifpga_rawdev_get_priv(raw_dev);
 799         if (!adapter)
 800                 return -ENODEV;
 801
 802         mgr = opae_adapter_get_mgr(adapter);
 803         if (!mgr)
 804                 return -ENODEV;
 805
 806         acc = opae_adapter_get_acc(adapter, port_id);
 807         if (!acc)
 808                 return -ENODEV;
 809
 810         br = opae_acc_get_br(acc);
 811         if (!br)
 812                 return -ENODEV;
 813
 814         ret = opae_manager_flash(mgr, port_id, buffer, size, status);
 815         if (ret) {
 816                 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
 817                 return ret;
 818         }
 819
 820         ret = opae_bridge_reset(br);
 821         if (ret) {
 822                 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
 823                                 __func__, port_id, ret);
 824                 return ret;
 825         }
 826
 827         return ret;
 828 }
 829
 830 static int
 831 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
 832                 const char *file_name)
 833 {
 834         struct stat file_stat;
 835         int file_fd;
 836         int ret = 0;
 837         ssize_t buffer_size;
 838         void *buffer, *buf_to_free;
 839         u64 pr_error;
 840
 841         if (!file_name)
 842                 return -EINVAL;
 843
 844         file_fd = open(file_name, O_RDONLY);
 845         if (file_fd < 0) {
 846                 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
 847                                 __func__, file_name);
 848                 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
 849                 return -EINVAL;
 850         }
 851         ret = stat(file_name, &file_stat);
 852         if (ret) {
 853                 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
 854                                 file_name);
 855                 ret = -EINVAL;
 856                 goto close_fd;
 857         }
 858         buffer_size = file_stat.st_size;
 859         if (buffer_size <= 0) {
 860                 ret = -EINVAL;
 861                 goto close_fd;
 862         }
 863
 864         IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
 865         buffer = rte_malloc(NULL, buffer_size, 0);
 866         if (!buffer) {
 867                 ret = -ENOMEM;
 868                 goto close_fd;
 869         }
 870         buf_to_free = buffer;
 871
 872         /*read the raw data*/
 873         if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
 874                 ret = -EINVAL;
 875                 goto free_buffer;
 876         }
 877
 878         /*do PR now*/
 879         ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
 880         IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
 881                 ret ? "failed" : "success");
 882         if (ret) {
 883                 ret = -EINVAL;
 884                 goto free_buffer;
 885         }
 886
 887 free_buffer:
 888         rte_free(buf_to_free);
 889 close_fd:
 890         close(file_fd);
 891         file_fd = 0;
 892         return ret;
 893 }
 894
 895 static int
 896 ifpga_rawdev_pr(struct rte_rawdev *dev,
 897         rte_rawdev_obj_t pr_conf)
 898 {
 899         struct opae_adapter *adapter;
 900         struct opae_manager *mgr;
 901         struct opae_board_info *info = NULL;
 902         struct rte_afu_pr_conf *afu_pr_conf;
 903         int ret;
 904         struct uuid uuid;
 905         struct opae_accelerator *acc;
 906
 907         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 908
 909         adapter = ifpga_rawdev_get_priv(dev);
 910         if (!adapter)
 911                 return -ENODEV;
 912
 913         if (!pr_conf)
 914                 return -EINVAL;
 915
 916         afu_pr_conf = pr_conf;
 917
 918         if (afu_pr_conf->pr_enable) {
 919                 ret = rte_fpga_do_pr(dev,
 920                                 afu_pr_conf->afu_id.port,
 921                                 afu_pr_conf->bs_path);
 922                 if (ret) {
 923                         IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
 924                         return ret;
 925                 }
 926         }
 927
 928         mgr = opae_adapter_get_mgr(adapter);
 929         if (mgr) {
 930                 if (ifpga_mgr_ops.get_board_info(mgr, &info)) {
 931                         IFPGA_RAWDEV_PMD_ERR("ifpga manager get_board_info fail!");
 932                         return -1;
 933                 }
 934         }
 935
 936         if (info && info->lightweight) {
 937                 /* set uuid to all 0, when fpga is lightweight image */
 938                 memset(&afu_pr_conf->afu_id.uuid.uuid_low, 0, sizeof(u64));
 939                 memset(&afu_pr_conf->afu_id.uuid.uuid_high, 0, sizeof(u64));
 940         } else {
 941                 acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
 942                 if (!acc)
 943                         return -ENODEV;
 944
 945                 ret = opae_acc_get_uuid(acc, &uuid);
 946                 if (ret)
 947                         return ret;
 948
 949                 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b,
 950                         sizeof(u64));
 951                 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high, uuid.b + 8,
 952                         sizeof(u64));
 953
 954                 IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n",
 955                         __func__,
 956                         (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
 957                         (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
 958         }
 959         return 0;
 960 }
 961
 962 static int
 963 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
 964         const char *attr_name, uint64_t *attr_value)
 965 {
 966         struct opae_adapter *adapter;
 967         struct opae_manager *mgr;
 968         struct opae_retimer_info opae_rtm_info;
 969         struct opae_retimer_status opae_rtm_status;
 970         struct opae_eth_group_info opae_eth_grp_info;
 971         struct opae_eth_group_region_info opae_eth_grp_reg_info;
 972         int eth_group_num = 0;
 973         uint64_t port_link_bitmap = 0, port_link_bit;
 974         uint32_t i, j, p, q;
 975
 976 #define MAX_PORT_PER_RETIMER    4
 977
 978         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 979
 980         if (!dev || !attr_name || !attr_value) {
 981                 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
 982                 return -1;
 983         }
 984
 985         adapter = ifpga_rawdev_get_priv(dev);
 986         if (!adapter) {
 987                 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
 988                 return -1;
 989         }
 990
 991         mgr = opae_adapter_get_mgr(adapter);
 992         if (!mgr) {
 993                 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
 994                 return -1;
 995         }
 996
 997         /* currently, eth_group_num is always 2 */
 998         eth_group_num = opae_manager_get_eth_group_nums(mgr);
 999         if (eth_group_num < 0)
1000                 return -1;
1001
1002         if (!strcmp(attr_name, "LineSideBaseMAC")) {
1003                 /* Currently FPGA not implement, so just set all zeros*/
1004                 *attr_value = (uint64_t)0;
1005                 return 0;
1006         }
1007         if (!strcmp(attr_name, "LineSideMACType")) {
1008                 /* eth_group 0 on FPGA connect to LineSide */
1009                 if (opae_manager_get_eth_group_info(mgr, 0,
1010                         &opae_eth_grp_info))
1011                         return -1;
1012                 switch (opae_eth_grp_info.speed) {
1013                 case ETH_SPEED_10G:
1014                         *attr_value =
1015                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
1016                         break;
1017                 case ETH_SPEED_25G:
1018                         *attr_value =
1019                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
1020                         break;
1021                 default:
1022                         *attr_value =
1023                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
1024                         break;
1025                 }
1026                 return 0;
1027         }
1028         if (!strcmp(attr_name, "LineSideLinkSpeed")) {
1029                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1030                         return -1;
1031                 switch (opae_rtm_status.speed) {
1032                 case MXD_1GB:
1033                         *attr_value =
1034                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1035                         break;
1036                 case MXD_2_5GB:
1037                         *attr_value =
1038                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1039                         break;
1040                 case MXD_5GB:
1041                         *attr_value =
1042                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1043                         break;
1044                 case MXD_10GB:
1045                         *attr_value =
1046                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
1047                         break;
1048                 case MXD_25GB:
1049                         *attr_value =
1050                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
1051                         break;
1052                 case MXD_40GB:
1053                         *attr_value =
1054                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
1055                         break;
1056                 case MXD_100GB:
1057                         *attr_value =
1058                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1059                         break;
1060                 case MXD_SPEED_UNKNOWN:
1061                         *attr_value =
1062                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1063                         break;
1064                 default:
1065                         *attr_value =
1066                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1067                         break;
1068                 }
1069                 return 0;
1070         }
1071         if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
1072                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1073                         return -1;
1074                 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
1075                 return 0;
1076         }
1077         if (!strcmp(attr_name, "LineSideLinkPortNum")) {
1078                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1079                         return -1;
1080                 uint64_t tmp = (uint64_t)opae_rtm_info.ports_per_retimer *
1081                                         (uint64_t)opae_rtm_info.nums_retimer;
1082                 *attr_value = tmp;
1083                 return 0;
1084         }
1085         if (!strcmp(attr_name, "LineSideLinkStatus")) {
1086                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1087                         return -1;
1088                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1089                         return -1;
1090                 (*attr_value) = 0;
1091                 q = 0;
1092                 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
1093                 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
1094                         p = i * MAX_PORT_PER_RETIMER;
1095                         for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
1096                                 port_link_bit = 0;
1097                                 IFPGA_BIT_SET(port_link_bit, (p+j));
1098                                 port_link_bit &= port_link_bitmap;
1099                                 if (port_link_bit)
1100                                         IFPGA_BIT_SET((*attr_value), q);
1101                                 q++;
1102                         }
1103                 }
1104                 return 0;
1105         }
1106         if (!strcmp(attr_name, "LineSideBARIndex")) {
1107                 /* eth_group 0 on FPGA connect to LineSide */
1108                 if (opae_manager_get_eth_group_region_info(mgr, 0,
1109                         &opae_eth_grp_reg_info))
1110                         return -1;
1111                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1112                 return 0;
1113         }
1114         if (!strcmp(attr_name, "NICSideMACType")) {
1115                 /* eth_group 1 on FPGA connect to NicSide */
1116                 if (opae_manager_get_eth_group_info(mgr, 1,
1117                         &opae_eth_grp_info))
1118                         return -1;
1119                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1120                 return 0;
1121         }
1122         if (!strcmp(attr_name, "NICSideLinkSpeed")) {
1123                 /* eth_group 1 on FPGA connect to NicSide */
1124                 if (opae_manager_get_eth_group_info(mgr, 1,
1125                         &opae_eth_grp_info))
1126                         return -1;
1127                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1128                 return 0;
1129         }
1130         if (!strcmp(attr_name, "NICSideLinkPortNum")) {
1131                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1132                         return -1;
1133                 uint64_t tmp = (uint64_t)opae_rtm_info.nums_fvl *
1134                                         (uint64_t)opae_rtm_info.ports_per_fvl;
1135                 *attr_value = tmp;
1136                 return 0;
1137         }
1138         if (!strcmp(attr_name, "NICSideLinkStatus"))
1139                 return 0;
1140         if (!strcmp(attr_name, "NICSideBARIndex")) {
1141                 /* eth_group 1 on FPGA connect to NicSide */
1142                 if (opae_manager_get_eth_group_region_info(mgr, 1,
1143                         &opae_eth_grp_reg_info))
1144                         return -1;
1145                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1146                 return 0;
1147         }
1148
1149         IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
1150         return -1;
1151 }
1152
1153 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
1154         .dev_info_get = ifpga_rawdev_info_get,
1155         .dev_configure = ifpga_rawdev_configure,
1156         .dev_start = ifpga_rawdev_start,
1157         .dev_stop = ifpga_rawdev_stop,
1158         .dev_close = ifpga_rawdev_close,
1159         .dev_reset = ifpga_rawdev_reset,
1160
1161         .queue_def_conf = NULL,
1162         .queue_setup = NULL,
1163         .queue_release = NULL,
1164
1165         .attr_get = ifpga_rawdev_get_attr,
1166         .attr_set = NULL,
1167
1168         .enqueue_bufs = NULL,
1169         .dequeue_bufs = NULL,
1170
1171         .dump = NULL,
1172
1173         .xstats_get = NULL,
1174         .xstats_get_names = NULL,
1175         .xstats_get_by_name = NULL,
1176         .xstats_reset = NULL,
1177
1178         .firmware_status_get = NULL,
1179         .firmware_version_get = NULL,
1180         .firmware_load = ifpga_rawdev_pr,
1181         .firmware_unload = NULL,
1182
1183         .dev_selftest = NULL,
1184 };
1185
1186 static int
1187 ifpga_get_fme_error_prop(struct opae_manager *mgr,
1188                 u64 prop_id, u64 *val)
1189 {
1190         struct feature_prop prop;
1191
1192         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1193         prop.prop_id = prop_id;
1194
1195         if (opae_manager_ifpga_get_prop(mgr, &prop))
1196                 return -EINVAL;
1197
1198         *val = prop.data;
1199
1200         return 0;
1201 }
1202
1203 static int
1204 ifpga_set_fme_error_prop(struct opae_manager *mgr,
1205                 u64 prop_id, u64 val)
1206 {
1207         struct feature_prop prop;
1208
1209         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1210         prop.prop_id = prop_id;
1211
1212         prop.data = val;
1213
1214         if (opae_manager_ifpga_set_prop(mgr, &prop))
1215                 return -EINVAL;
1216
1217         return 0;
1218 }
1219
1220 static int
1221 fme_err_read_seu_emr(struct opae_manager *mgr)
1222 {
1223         u64 val;
1224         int ret;
1225
1226         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
1227         if (ret)
1228                 return -EINVAL;
1229
1230         IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%" PRIx64 "\n", val);
1231
1232         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
1233         if (ret)
1234                 return -EINVAL;
1235
1236         IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%" PRIx64 "\n", val);
1237
1238         return 0;
1239 }
1240
1241 static int fme_clear_warning_intr(struct opae_manager *mgr)
1242 {
1243         u64 val;
1244
1245         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
1246                 return -EINVAL;
1247
1248         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1249                 return -EINVAL;
1250         if ((val & 0x40) != 0)
1251                 IFPGA_RAWDEV_PMD_INFO("clean not done\n");
1252
1253         return 0;
1254 }
1255
1256 static int fme_clean_fme_error(struct opae_manager *mgr)
1257 {
1258         u64 val;
1259
1260         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1261                 return -EINVAL;
1262
1263         IFPGA_RAWDEV_PMD_DEBUG("before clean 0x%" PRIx64 "\n", val);
1264
1265         ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_CLEAR, val);
1266
1267         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1268                 return -EINVAL;
1269
1270         IFPGA_RAWDEV_PMD_DEBUG("after clean 0x%" PRIx64 "\n", val);
1271
1272         return 0;
1273 }
1274
1275 static int
1276 fme_err_handle_error0(struct opae_manager *mgr)
1277 {
1278         struct feature_fme_error0 fme_error0;
1279         u64 val;
1280
1281         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1282                 return -EINVAL;
1283
1284         if (fme_clean_fme_error(mgr))
1285                 return -EINVAL;
1286
1287         fme_error0.csr = val;
1288
1289         if (fme_error0.fabric_err)
1290                 IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
1291         else if (fme_error0.fabfifo_overflow)
1292                 IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
1293         else if (fme_error0.afu_acc_mode_err)
1294                 IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
1295         else if (fme_error0.pcie0cdc_parity_err)
1296                 IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
1297         else if (fme_error0.cvlcdc_parity_err)
1298                 IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
1299         else if (fme_error0.fpgaseuerr)
1300                 fme_err_read_seu_emr(mgr);
1301
1302         /* clean the errors */
1303         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
1304                 return -EINVAL;
1305
1306         return 0;
1307 }
1308
1309 static int
1310 fme_err_handle_catfatal_error(struct opae_manager *mgr)
1311 {
1312         struct feature_fme_ras_catfaterror fme_catfatal;
1313         u64 val;
1314
1315         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
1316                 return -EINVAL;
1317
1318         fme_catfatal.csr = val;
1319
1320         if (fme_catfatal.cci_fatal_err)
1321                 IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
1322         else if (fme_catfatal.fabric_fatal_err)
1323                 IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
1324         else if (fme_catfatal.pcie_poison_err)
1325                 IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
1326         else if (fme_catfatal.inject_fata_err)
1327                 IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
1328         else if (fme_catfatal.crc_catast_err)
1329                 IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
1330         else if (fme_catfatal.injected_catast_err)
1331                 IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
1332         else if (fme_catfatal.bmc_seu_catast_err)
1333                 fme_err_read_seu_emr(mgr);
1334
1335         return 0;
1336 }
1337
1338 static int
1339 fme_err_handle_nonfaterror(struct opae_manager *mgr)
1340 {
1341         struct feature_fme_ras_nonfaterror nonfaterr;
1342         u64 val;
1343
1344         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1345                 return -EINVAL;
1346
1347         nonfaterr.csr = val;
1348
1349         if (nonfaterr.temp_thresh_ap1)
1350                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP1\n");
1351         else if (nonfaterr.temp_thresh_ap2)
1352                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP2\n");
1353         else if (nonfaterr.pcie_error)
1354                 IFPGA_RAWDEV_PMD_INFO("an error has occurred in pcie\n");
1355         else if (nonfaterr.portfatal_error)
1356                 IFPGA_RAWDEV_PMD_INFO("fatal error occurred in AFU port.\n");
1357         else if (nonfaterr.proc_hot)
1358                 IFPGA_RAWDEV_PMD_INFO("a ProcHot event\n");
1359         else if (nonfaterr.afu_acc_mode_err)
1360                 IFPGA_RAWDEV_PMD_INFO("an AFU PF/VF access mismatch\n");
1361         else if (nonfaterr.injected_nonfata_err) {
1362                 IFPGA_RAWDEV_PMD_INFO("Injected Warning Error\n");
1363                 fme_clear_warning_intr(mgr);
1364         } else if (nonfaterr.temp_thresh_AP6)
1365                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP6\n");
1366         else if (nonfaterr.power_thresh_AP1)
1367                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP1\n");
1368         else if (nonfaterr.power_thresh_AP2)
1369                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP2\n");
1370         else if (nonfaterr.mbp_err)
1371                 IFPGA_RAWDEV_PMD_INFO("an MBP event\n");
1372
1373         return 0;
1374 }
1375
1376 static void
1377 fme_interrupt_handler(void *param)
1378 {
1379         struct opae_manager *mgr = (struct opae_manager *)param;
1380
1381         IFPGA_RAWDEV_PMD_INFO("%s interrupt occurred\n", __func__);
1382
1383         fme_err_handle_error0(mgr);
1384         fme_err_handle_nonfaterror(mgr);
1385         fme_err_handle_catfatal_error(mgr);
1386 }
1387
1388 int
1389 ifpga_unregister_msix_irq(struct ifpga_rawdev *dev, enum ifpga_irq_type type,
1390                 int vec_start, rte_intr_callback_fn handler, void *arg)
1391 {
1392         struct rte_intr_handle **intr_handle;
1393         int rc = 0;
1394         int i = vec_start + 1;
1395
1396         if (!dev)
1397                 return -ENODEV;
1398
1399         if (type == IFPGA_FME_IRQ)
1400                 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[0];
1401         else if (type == IFPGA_AFU_IRQ)
1402                 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[i];
1403         else
1404                 return -EINVAL;
1405
1406         if ((*intr_handle) == NULL) {
1407                 IFPGA_RAWDEV_PMD_ERR("%s interrupt %d not registered\n",
1408                         type == IFPGA_FME_IRQ ? "FME" : "AFU",
1409                         type == IFPGA_FME_IRQ ? 0 : vec_start);
1410                 return -ENOENT;
1411         }
1412
1413         rte_intr_efd_disable(*intr_handle);
1414
1415         rc = rte_intr_callback_unregister(*intr_handle, handler, arg);
1416         if (rc < 0) {
1417                 IFPGA_RAWDEV_PMD_ERR("Failed to unregister %s interrupt %d\n",
1418                         type == IFPGA_FME_IRQ ? "FME" : "AFU",
1419                         type == IFPGA_FME_IRQ ? 0 : vec_start);
1420         } else {
1421                 rte_intr_instance_free(*intr_handle);
1422                 *intr_handle = NULL;
1423         }
1424
1425         return rc;
1426 }
1427
1428 int
1429 ifpga_register_msix_irq(struct ifpga_rawdev *dev, int port_id,
1430                 enum ifpga_irq_type type, int vec_start, int count,
1431                 rte_intr_callback_fn handler, const char *name,
1432                 void *arg)
1433 {
1434         int ret;
1435         struct rte_intr_handle **intr_handle;
1436         struct opae_adapter *adapter;
1437         struct opae_manager *mgr;
1438         struct opae_accelerator *acc;
1439         int *intr_efds = NULL, nb_intr, i;
1440
1441         if (!dev || !dev->rawdev)
1442                 return -ENODEV;
1443
1444         adapter = ifpga_rawdev_get_priv(dev->rawdev);
1445         if (!adapter)
1446                 return -ENODEV;
1447
1448         mgr = opae_adapter_get_mgr(adapter);
1449         if (!mgr)
1450                 return -ENODEV;
1451
1452         if (type == IFPGA_FME_IRQ) {
1453                 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[0];
1454                 count = 1;
1455         } else if (type == IFPGA_AFU_IRQ) {
1456                 i = vec_start + 1;
1457                 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[i];
1458         } else {
1459                 return -EINVAL;
1460         }
1461
1462         if (*intr_handle)
1463                 return -EBUSY;
1464
1465         *intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
1466         if (!(*intr_handle))
1467                 return -ENOMEM;
1468
1469         if (rte_intr_type_set(*intr_handle, RTE_INTR_HANDLE_VFIO_MSIX))
1470                 return -rte_errno;
1471
1472         ret = rte_intr_efd_enable(*intr_handle, count);
1473         if (ret)
1474                 return -ENODEV;
1475
1476         if (rte_intr_fd_set(*intr_handle,
1477                         rte_intr_efds_index_get(*intr_handle, 0)))
1478                 return -rte_errno;
1479
1480         IFPGA_RAWDEV_PMD_DEBUG("register %s irq, vfio_fd=%d, fd=%d\n",
1481                         name, rte_intr_dev_fd_get(*intr_handle),
1482                         rte_intr_fd_get(*intr_handle));
1483
1484         if (type == IFPGA_FME_IRQ) {
1485                 struct fpga_fme_err_irq_set err_irq_set;
1486                 err_irq_set.evtfd = rte_intr_efds_index_get(*intr_handle,
1487                                                                    0);
1488
1489                 ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
1490                 if (ret)
1491                         return -EINVAL;
1492         } else if (type == IFPGA_AFU_IRQ) {
1493                 acc = opae_adapter_get_acc(adapter, port_id);
1494                 if (!acc)
1495                         return -EINVAL;
1496
1497                 nb_intr = rte_intr_nb_intr_get(*intr_handle);
1498
1499                 intr_efds = calloc(nb_intr, sizeof(int));
1500                 if (!intr_efds)
1501                         return -ENOMEM;
1502
1503                 for (i = 0; i < nb_intr; i++)
1504                         intr_efds[i] = rte_intr_efds_index_get(*intr_handle, i);
1505
1506                 ret = opae_acc_set_irq(acc, vec_start, count, intr_efds);
1507                 if (ret) {
1508                         free(intr_efds);
1509                         return -EINVAL;
1510                 }
1511         }
1512
1513         /* register interrupt handler using DPDK API */
1514         ret = rte_intr_callback_register(*intr_handle,
1515                         handler, (void *)arg);
1516         if (ret) {
1517                 free(intr_efds);
1518                 return -EINVAL;
1519         }
1520
1521         IFPGA_RAWDEV_PMD_INFO("success register %s interrupt\n", name);
1522
1523         free(intr_efds);
1524         return 0;
1525 }
1526
1527 static int
1528 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
1529                         int socket_id)
1530 {
1531         int ret = 0;
1532         struct rte_rawdev *rawdev = NULL;
1533         struct ifpga_rawdev *dev = NULL;
1534         struct opae_adapter *adapter = NULL;
1535         struct opae_manager *mgr = NULL;
1536         struct opae_adapter_data_pci *data = NULL;
1537         char name[RTE_RAWDEV_NAME_MAX_LEN];
1538         int i;
1539
1540         if (!pci_dev) {
1541                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1542                 ret = -EINVAL;
1543                 goto cleanup;
1544         }
1545
1546         memset(name, 0, sizeof(name));
1547         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, IFPGA_RAWDEV_NAME_FMT,
1548                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1549
1550         IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
1551
1552         /* Allocate device structure */
1553         rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
1554                                          socket_id);
1555         if (rawdev == NULL) {
1556                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
1557                 ret = -EINVAL;
1558                 goto cleanup;
1559         }
1560
1561         ipn3ke_bridge_func.get_ifpga_rawdev = ifpga_rawdev_get;
1562         ipn3ke_bridge_func.set_i40e_sw_dev = rte_pmd_i40e_set_switch_dev;
1563
1564         dev = ifpga_rawdev_allocate(rawdev);
1565         if (dev == NULL) {
1566                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate ifpga_rawdevice");
1567                 ret = -EINVAL;
1568                 goto cleanup;
1569         }
1570         dev->aer_enable = 0;
1571
1572         /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
1573         data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
1574         if (!data) {
1575                 ret = -ENOMEM;
1576                 goto cleanup;
1577         }
1578
1579         /* init opae_adapter_data_pci for device specific information */
1580         for (i = 0; i < PCI_MAX_RESOURCE; i++) {
1581                 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
1582                 data->region[i].len = pci_dev->mem_resource[i].len;
1583                 data->region[i].addr = pci_dev->mem_resource[i].addr;
1584         }
1585         data->device_id = pci_dev->id.device_id;
1586         data->vendor_id = pci_dev->id.vendor_id;
1587         data->bus = pci_dev->addr.bus;
1588         data->devid = pci_dev->addr.devid;
1589         data->function = pci_dev->addr.function;
1590         data->vfio_dev_fd = rte_intr_dev_fd_get(pci_dev->intr_handle);
1591
1592         adapter = rawdev->dev_private;
1593         /* create a opae_adapter based on above device data */
1594         ret = opae_adapter_init(adapter, pci_dev->device.name, data);
1595         if (ret) {
1596                 ret = -ENOMEM;
1597                 goto cleanup;
1598         }
1599
1600         rawdev->dev_ops = &ifpga_rawdev_ops;
1601         rawdev->device = &pci_dev->device;
1602         rawdev->driver_name = pci_dev->driver->driver.name;
1603
1604         /* must enumerate the adapter before use it */
1605         ret = opae_adapter_enumerate(adapter);
1606         if (ret)
1607                 goto cleanup;
1608
1609         /* get opae_manager to rawdev */
1610         mgr = opae_adapter_get_mgr(adapter);
1611         if (mgr) {
1612                 ret = ifpga_register_msix_irq(dev, 0, IFPGA_FME_IRQ, 0, 0,
1613                                 fme_interrupt_handler, "fme_irq", mgr);
1614                 if (ret)
1615                         goto cleanup;
1616         }
1617
1618         ret = ifpga_monitor_start_func(dev);
1619         if (ret)
1620                 goto cleanup;
1621
1622         return ret;
1623
1624 cleanup:
1625         if (rawdev)
1626                 rte_rawdev_pmd_release(rawdev);
1627
1628         return ret;
1629 }
1630
1631 static int
1632 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
1633 {
1634         int ret;
1635         struct rte_rawdev *rawdev;
1636         char name[RTE_RAWDEV_NAME_MAX_LEN];
1637
1638         if (!pci_dev) {
1639                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1640                 ret = -EINVAL;
1641                 return ret;
1642         }
1643
1644         memset(name, 0, sizeof(name));
1645         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, IFPGA_RAWDEV_NAME_FMT,
1646                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1647
1648         IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
1649                 name, rte_socket_id());
1650
1651         rawdev = rte_rawdev_pmd_get_named_dev(name);
1652         if (!rawdev) {
1653                 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
1654                 return -EINVAL;
1655         }
1656
1657         /* rte_rawdev_close is called by pmd_release */
1658         ret = rte_rawdev_pmd_release(rawdev);
1659         if (ret)
1660                 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
1661
1662         return ret;
1663 }
1664
1665 static int
1666 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1667         struct rte_pci_device *pci_dev)
1668 {
1669         IFPGA_RAWDEV_PMD_FUNC_TRACE();
1670         return ifpga_rawdev_create(pci_dev, rte_socket_id());
1671 }
1672
1673 static int
1674 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
1675 {
1676         IFPGA_RAWDEV_PMD_INFO("remove pci_dev %s", pci_dev->device.name);
1677         return ifpga_rawdev_destroy(pci_dev);
1678 }
1679
1680 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
1681         .id_table  = pci_ifpga_map,
1682         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1683         .probe     = ifpga_rawdev_pci_probe,
1684         .remove    = ifpga_rawdev_pci_remove,
1685 };
1686
1687 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1688 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1689 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
1690 RTE_LOG_REGISTER_DEFAULT(ifpga_rawdev_logtype, NOTICE);
1691
1692 static const char * const valid_args[] = {
1693 #define IFPGA_ARG_NAME         "ifpga"
1694         IFPGA_ARG_NAME,
1695 #define IFPGA_ARG_PORT         "port"
1696         IFPGA_ARG_PORT,
1697 #define IFPGA_AFU_BTS          "afu_bts"
1698         IFPGA_AFU_BTS,
1699         NULL
1700 };
1701
1702 static int ifpga_rawdev_get_string_arg(const char *key __rte_unused,
1703         const char *value, void *extra_args)
1704 {
1705         int size;
1706         if (!value || !extra_args)
1707                 return -EINVAL;
1708
1709         size = strlen(value) + 1;
1710         *(char **)extra_args = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
1711         if (!*(char **)extra_args)
1712                 return -ENOMEM;
1713
1714         strlcpy(*(char **)extra_args, value, size);
1715
1716         return 0;
1717 }
1718
1719 static int
1720 ifpga_vdev_parse_devargs(struct rte_devargs *devargs,
1721         struct ifpga_vdev_args *args)
1722 {
1723         struct rte_kvargs *kvlist;
1724         char *name = NULL;
1725         int port = 0;
1726         int ret = -EINVAL;
1727
1728         if (!devargs || !args)
1729                 return ret;
1730
1731         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1732         if (!kvlist) {
1733                 IFPGA_RAWDEV_PMD_ERR("error when parsing devargs");
1734                 return ret;
1735         }
1736
1737         if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
1738                 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
1739                         &ifpga_rawdev_get_string_arg, &name) < 0) {
1740                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1741                                 IFPGA_ARG_NAME);
1742                         goto end;
1743                 } else {
1744                         strlcpy(args->bdf, name, sizeof(args->bdf));
1745                         rte_free(name);
1746                 }
1747         } else {
1748                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1749                         IFPGA_ARG_NAME);
1750                 goto end;
1751         }
1752
1753         if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
1754                 if (rte_kvargs_process(kvlist, IFPGA_ARG_PORT,
1755                         &rte_ifpga_get_integer32_arg, &port) < 0) {
1756                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1757                                 IFPGA_ARG_PORT);
1758                         goto end;
1759                 } else {
1760                         args->port = port;
1761                 }
1762         } else {
1763                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1764                         IFPGA_ARG_PORT);
1765                 goto end;
1766         }
1767
1768         ret = 0;
1769
1770 end:
1771         if (kvlist)
1772                 rte_kvargs_free(kvlist);
1773
1774         return ret;
1775 }
1776
1777 static int
1778 ifpga_cfg_probe(struct rte_vdev_device *vdev)
1779 {
1780         struct rte_rawdev *rawdev = NULL;
1781         struct ifpga_rawdev *ifpga_dev;
1782         struct ifpga_vdev_args args;
1783         char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1784         const char *vdev_name = NULL;
1785         int i, n, ret = 0;
1786
1787         vdev_name = rte_vdev_device_name(vdev);
1788         if (!vdev_name)
1789                 return -EINVAL;
1790
1791         IFPGA_RAWDEV_PMD_INFO("probe ifpga virtual device %s", vdev_name);
1792
1793         ret = ifpga_vdev_parse_devargs(vdev->device.devargs, &args);
1794         if (ret)
1795                 return ret;
1796
1797         memset(dev_name, 0, sizeof(dev_name));
1798         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", args.bdf);
1799         rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1800         if (!rawdev)
1801                 return -ENODEV;
1802         ifpga_dev = ifpga_rawdev_get(rawdev);
1803         if (!ifpga_dev)
1804                 return -ENODEV;
1805
1806         for (i = 0; i < IFPGA_MAX_VDEV; i++) {
1807                 if (ifpga_dev->vdev_name[i] == NULL) {
1808                         n = strlen(vdev_name) + 1;
1809                         ifpga_dev->vdev_name[i] = rte_malloc(NULL, n, 0);
1810                         if (ifpga_dev->vdev_name[i] == NULL)
1811                                 return -ENOMEM;
1812                         strlcpy(ifpga_dev->vdev_name[i], vdev_name, n);
1813                         break;
1814                 }
1815         }
1816
1817         if (i >= IFPGA_MAX_VDEV) {
1818                 IFPGA_RAWDEV_PMD_ERR("Can't create more virtual device!");
1819                 return -ENOENT;
1820         }
1821
1822         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1823                 args.port, args.bdf);
1824         ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
1825                         dev_name, vdev->device.devargs->args);
1826         if (ret) {
1827                 rte_free(ifpga_dev->vdev_name[i]);
1828                 ifpga_dev->vdev_name[i] = NULL;
1829         }
1830
1831         return ret;
1832 }
1833
1834 static int
1835 ifpga_cfg_remove(struct rte_vdev_device *vdev)
1836 {
1837         struct rte_rawdev *rawdev = NULL;
1838         struct ifpga_rawdev *ifpga_dev;
1839         struct ifpga_vdev_args args;
1840         char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1841         const char *vdev_name = NULL;
1842         char *tmp_vdev = NULL;
1843         int i, ret = 0;
1844
1845         vdev_name = rte_vdev_device_name(vdev);
1846         if (!vdev_name)
1847                 return -EINVAL;
1848
1849         IFPGA_RAWDEV_PMD_INFO("remove ifpga virtual device %s", vdev_name);
1850
1851         ret = ifpga_vdev_parse_devargs(vdev->device.devargs, &args);
1852         if (ret)
1853                 return ret;
1854
1855         memset(dev_name, 0, sizeof(dev_name));
1856         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", args.bdf);
1857         rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1858         if (!rawdev)
1859                 return -ENODEV;
1860         ifpga_dev = ifpga_rawdev_get(rawdev);
1861         if (!ifpga_dev)
1862                 return -ENODEV;
1863
1864         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1865                 args.port, args.bdf);
1866         ret = rte_eal_hotplug_remove(RTE_STR(IFPGA_BUS_NAME), dev_name);
1867
1868         for (i = 0; i < IFPGA_MAX_VDEV; i++) {
1869                 tmp_vdev = ifpga_dev->vdev_name[i];
1870                 if (tmp_vdev && !strcmp(tmp_vdev, vdev_name)) {
1871                         free(tmp_vdev);
1872                         ifpga_dev->vdev_name[i] = NULL;
1873                         break;
1874                 }
1875         }
1876
1877         return ret;
1878 }
1879
1880 static struct rte_vdev_driver ifpga_cfg_driver = {
1881         .probe = ifpga_cfg_probe,
1882         .remove = ifpga_cfg_remove,
1883 };
1884
1885 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
1886 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
1887 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,
1888         "ifpga=<string> "
1889         "port=<int> "
1890         "afu_bts=<path>");
1891
1892 struct rte_pci_bus *ifpga_get_pci_bus(void)
1893 {
1894         return rte_ifpga_rawdev_pmd.bus;
1895 }
1896
1897 int ifpga_rawdev_partial_reconfigure(struct rte_rawdev *dev, int port,
1898         const char *file)
1899 {
1900         if (!dev) {
1901                 IFPGA_RAWDEV_PMD_ERR("Input parameter is invalid");
1902                 return -EINVAL;
1903         }
1904
1905         return rte_fpga_do_pr(dev, port, file);
1906 }
1907
1908 void ifpga_rawdev_cleanup(void)
1909 {
1910         struct ifpga_rawdev *dev;
1911         unsigned int i;
1912
1913         for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
1914                 dev = &ifpga_rawdevices[i];
1915                 if (dev->rawdev) {
1916                         rte_rawdev_pmd_release(dev->rawdev);
1917                         dev->rawdev = NULL;
1918                 }
1919         }
1920 }