drivers/raw/ifpga/ifpga_rawdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2018 Intel Corporation
   3  */
   4
   5 #include <string.h>
   6 #include <dirent.h>
   7 #include <sys/stat.h>
   8 #include <unistd.h>
   9 #include <sys/types.h>
  10 #include <fcntl.h>
  11 #include <sys/ioctl.h>
  12 #include <sys/epoll.h>
  13 #include <rte_log.h>
  14 #include <rte_bus.h>
  15 #include <rte_malloc.h>
  16 #include <rte_devargs.h>
  17 #include <rte_memcpy.h>
  18 #include <rte_pci.h>
  19 #include <rte_bus_pci.h>
  20 #include <rte_kvargs.h>
  21 #include <rte_alarm.h>
  22 #include <rte_interrupts.h>
  23 #include <rte_errno.h>
  24 #include <rte_per_lcore.h>
  25 #include <rte_memory.h>
  26 #include <rte_memzone.h>
  27 #include <rte_eal.h>
  28 #include <rte_common.h>
  29 #include <rte_bus_vdev.h>
  30 #include <rte_string_fns.h>
  31 #include <rte_pmd_i40e.h>
  32
  33 #include "base/opae_hw_api.h"
  34 #include "base/opae_ifpga_hw_api.h"
  35 #include "base/ifpga_api.h"
  36 #include "rte_rawdev.h"
  37 #include "rte_rawdev_pmd.h"
  38 #include "rte_bus_ifpga.h"
  39 #include "ifpga_common.h"
  40 #include "ifpga_logs.h"
  41 #include "ifpga_rawdev.h"
  42 #include "ipn3ke_rawdev_api.h"
  43
  44 #define PCI_VENDOR_ID_INTEL          0x8086
  45 /* PCI Device ID */
  46 #define PCIE_DEVICE_ID_PF_INT_5_X    0xBCBD
  47 #define PCIE_DEVICE_ID_PF_INT_6_X    0xBCC0
  48 #define PCIE_DEVICE_ID_PF_DSC_1_X    0x09C4
  49 #define PCIE_DEVICE_ID_PAC_N3000     0x0B30
  50 /* VF Device */
  51 #define PCIE_DEVICE_ID_VF_INT_5_X    0xBCBF
  52 #define PCIE_DEVICE_ID_VF_INT_6_X    0xBCC1
  53 #define PCIE_DEVICE_ID_VF_DSC_1_X    0x09C5
  54 #define PCIE_DEVICE_ID_VF_PAC_N3000  0x0B31
  55 #define RTE_MAX_RAW_DEVICE           10
  56
  57 static const struct rte_pci_id pci_ifpga_map[] = {
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
  66         { .vendor_id = 0, /* sentinel */ },
  67 };
  68
  69 static struct ifpga_rawdev ifpga_rawdevices[IFPGA_RAWDEV_NUM];
  70
  71 static int ifpga_monitor_refcnt;
  72 static pthread_t ifpga_monitor_start_thread;
  73
  74 static struct ifpga_rawdev *
  75 ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
  76 static int set_surprise_link_check_aer(
  77                 struct ifpga_rawdev *ifpga_rdev, int force_disable);
  78 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
  79                                               int start, uint32_t cap);
  80 static int ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap);
  81
  82 struct ifpga_rawdev *
  83 ifpga_rawdev_get(const struct rte_rawdev *rawdev)
  84 {
  85         struct ifpga_rawdev *dev;
  86         unsigned int i;
  87
  88         if (rawdev == NULL)
  89                 return NULL;
  90
  91         for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
  92                 dev = &ifpga_rawdevices[i];
  93                 if (dev->rawdev == rawdev)
  94                         return dev;
  95         }
  96
  97         return NULL;
  98 }
  99
 100 static inline uint8_t
 101 ifpga_rawdev_find_free_device_index(void)
 102 {
 103         uint16_t dev_id;
 104
 105         for (dev_id = 0; dev_id < IFPGA_RAWDEV_NUM; dev_id++) {
 106                 if (ifpga_rawdevices[dev_id].rawdev == NULL)
 107                         return dev_id;
 108         }
 109
 110         return IFPGA_RAWDEV_NUM;
 111 }
 112 static struct ifpga_rawdev *
 113 ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
 114 {
 115         struct ifpga_rawdev *dev;
 116         uint16_t dev_id;
 117         int i = 0;
 118
 119         dev = ifpga_rawdev_get(rawdev);
 120         if (dev != NULL) {
 121                 IFPGA_RAWDEV_PMD_ERR("Event device already allocated!");
 122                 return NULL;
 123         }
 124
 125         dev_id = ifpga_rawdev_find_free_device_index();
 126         if (dev_id == IFPGA_RAWDEV_NUM) {
 127                 IFPGA_RAWDEV_PMD_ERR("Reached maximum number of raw devices");
 128                 return NULL;
 129         }
 130
 131         dev = &ifpga_rawdevices[dev_id];
 132         dev->rawdev = rawdev;
 133         dev->dev_id = dev_id;
 134         for (i = 0; i < IFPGA_MAX_IRQ; i++)
 135                 dev->intr_handle[i] = NULL;
 136         dev->poll_enabled = 0;
 137         for (i = 0; i < IFPGA_MAX_VDEV; i++)
 138                 dev->vdev_name[i] = NULL;
 139
 140         return dev;
 141 }
 142
 143 static int
 144 ifpga_pci_find_next_ext_capability(unsigned int fd, int start, uint32_t cap)
 145 {
 146         uint32_t header;
 147         int ttl;
 148         int pos = RTE_PCI_CFG_SPACE_SIZE;
 149         int ret;
 150
 151         /* minimum 8 bytes per capability */
 152         ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
 153
 154         if (start)
 155                 pos = start;
 156         ret = pread(fd, &header, sizeof(header), pos);
 157         if (ret == -1)
 158                 return -1;
 159
 160         /*
 161          * If we have no capabilities, this is indicated by cap ID,
 162          * cap version and next pointer all being 0.
 163          */
 164         if (header == 0)
 165                 return 0;
 166
 167         while (ttl-- > 0) {
 168                 if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
 169                         return pos;
 170
 171                 pos = RTE_PCI_EXT_CAP_NEXT(header);
 172                 if (pos < RTE_PCI_CFG_SPACE_SIZE)
 173                         break;
 174                 ret = pread(fd, &header, sizeof(header), pos);
 175                 if (ret == -1)
 176                         return -1;
 177         }
 178
 179         return 0;
 180 }
 181
 182 static int
 183 ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap)
 184 {
 185         return ifpga_pci_find_next_ext_capability(fd, 0, cap);
 186 }
 187
 188 static int ifpga_get_dev_vendor_id(const char *bdf,
 189         uint32_t *dev_id, uint32_t *vendor_id)
 190 {
 191         int fd;
 192         char path[1024];
 193         int ret;
 194         uint32_t header;
 195
 196         strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
 197         strlcat(path, bdf, sizeof(path));
 198         strlcat(path, "/config", sizeof(path));
 199         fd = open(path, O_RDWR);
 200         if (fd < 0)
 201                 return -1;
 202         ret = pread(fd, &header, sizeof(header), 0);
 203         if (ret == -1) {
 204                 close(fd);
 205                 return -1;
 206         }
 207         (*vendor_id) = header & 0xffff;
 208         (*dev_id) = (header >> 16) & 0xffff;
 209         close(fd);
 210
 211         return 0;
 212 }
 213
 214 static int ifpga_rawdev_fill_info(struct ifpga_rawdev *ifpga_dev)
 215 {
 216         struct opae_adapter *adapter = NULL;
 217         char path[1024] = "/sys/bus/pci/devices/";
 218         char link[1024], link1[1024];
 219         char dir[1024] = "/sys/devices/";
 220         char *c;
 221         int ret;
 222         char sub_brg_bdf[4][16] = {{0}};
 223         int point;
 224         DIR *dp = NULL;
 225         struct dirent *entry;
 226         int i, j;
 227
 228         unsigned int dom, bus, dev;
 229         int func;
 230         uint32_t dev_id = 0;
 231         uint32_t vendor_id = 0;
 232
 233         adapter = ifpga_dev ? ifpga_rawdev_get_priv(ifpga_dev->rawdev) : NULL;
 234         if (!adapter)
 235                 return -ENODEV;
 236
 237         strlcat(path, adapter->name, sizeof(path));
 238         memset(link, 0, sizeof(link));
 239         memset(link1, 0, sizeof(link1));
 240         ret = readlink(path, link, (sizeof(link)-1));
 241         if ((ret < 0) || ((unsigned int)ret > (sizeof(link)-1)))
 242                 return -1;
 243         link[ret] = 0;   /* terminate string with null character */
 244         strlcpy(link1, link, sizeof(link1));
 245         memset(ifpga_dev->parent_bdf, 0, 16);
 246         point = strlen(link);
 247         if (point < 39)
 248                 return -1;
 249         point -= 39;
 250         link[point] = 0;
 251         if (point < 12)
 252                 return -1;
 253         point -= 12;
 254         rte_memcpy(ifpga_dev->parent_bdf, &link[point], 12);
 255
 256         point = strlen(link1);
 257         if (point < 26)
 258                 return -1;
 259         point -= 26;
 260         link1[point] = 0;
 261         if (point < 12)
 262                 return -1;
 263         point -= 12;
 264         c = strchr(link1, 'p');
 265         if (!c)
 266                 return -1;
 267         strlcat(dir, c, sizeof(dir));
 268
 269         /* scan folder */
 270         dp = opendir(dir);
 271         if (dp == NULL)
 272                 return -1;
 273         i = 0;
 274         while ((entry = readdir(dp)) != NULL) {
 275                 if (i >= 4)
 276                         break;
 277                 if (entry->d_name[0] == '.')
 278                         continue;
 279                 if (strlen(entry->d_name) > 12)
 280                         continue;
 281                 if (sscanf(entry->d_name, "%x:%x:%x.%d",
 282                         &dom, &bus, &dev, &func) < 4)
 283                         continue;
 284                 else {
 285                         strlcpy(sub_brg_bdf[i],
 286                                 entry->d_name,
 287                                 sizeof(sub_brg_bdf[i]));
 288                         i++;
 289                 }
 290         }
 291         closedir(dp);
 292
 293         /* get fpga and fvl */
 294         j = 0;
 295         for (i = 0; i < 4; i++) {
 296                 strlcpy(link, dir, sizeof(link));
 297                 strlcat(link, "/", sizeof(link));
 298                 strlcat(link, sub_brg_bdf[i], sizeof(link));
 299                 dp = opendir(link);
 300                 if (dp == NULL)
 301                         return -1;
 302                 while ((entry = readdir(dp)) != NULL) {
 303                         if (j >= 8)
 304                                 break;
 305                         if (entry->d_name[0] == '.')
 306                                 continue;
 307
 308                         if (strlen(entry->d_name) > 12)
 309                                 continue;
 310                         if (sscanf(entry->d_name, "%x:%x:%x.%d",
 311                                 &dom, &bus, &dev, &func) < 4)
 312                                 continue;
 313                         else {
 314                                 if (ifpga_get_dev_vendor_id(entry->d_name,
 315                                         &dev_id, &vendor_id))
 316                                         continue;
 317                                 if (vendor_id == 0x8086 &&
 318                                         (dev_id == 0x0CF8 ||
 319                                         dev_id == 0x0D58 ||
 320                                         dev_id == 0x1580)) {
 321                                         strlcpy(ifpga_dev->fvl_bdf[j],
 322                                                 entry->d_name,
 323                                                 sizeof(ifpga_dev->fvl_bdf[j]));
 324                                         j++;
 325                                 }
 326                         }
 327                 }
 328                 closedir(dp);
 329         }
 330
 331         return 0;
 332 }
 333
 334 #define HIGH_FATAL(_sens, value)\
 335         (((_sens)->flags & OPAE_SENSOR_HIGH_FATAL_VALID) &&\
 336          (value > (_sens)->high_fatal))
 337
 338 #define HIGH_WARN(_sens, value)\
 339         (((_sens)->flags & OPAE_SENSOR_HIGH_WARN_VALID) &&\
 340          (value > (_sens)->high_warn))
 341
 342 #define LOW_FATAL(_sens, value)\
 343         (((_sens)->flags & OPAE_SENSOR_LOW_FATAL_VALID) &&\
 344          (value > (_sens)->low_fatal))
 345
 346 #define LOW_WARN(_sens, value)\
 347         (((_sens)->flags & OPAE_SENSOR_LOW_WARN_VALID) &&\
 348          (value > (_sens)->low_warn))
 349
 350 #define AUX_VOLTAGE_WARN 11400
 351
 352 static int
 353 ifpga_monitor_sensor(struct rte_rawdev *raw_dev,
 354                bool *gsd_start)
 355 {
 356         struct opae_adapter *adapter;
 357         struct opae_manager *mgr;
 358         struct opae_sensor_info *sensor;
 359         unsigned int value;
 360         int ret;
 361
 362         adapter = ifpga_rawdev_get_priv(raw_dev);
 363         if (!adapter)
 364                 return -ENODEV;
 365
 366         mgr = opae_adapter_get_mgr(adapter);
 367         if (!mgr)
 368                 return -ENODEV;
 369
 370         opae_mgr_for_each_sensor(mgr, sensor) {
 371                 if (!(sensor->flags & OPAE_SENSOR_VALID))
 372                         goto fail;
 373
 374                 ret = opae_mgr_get_sensor_value(mgr, sensor, &value);
 375                 if (ret)
 376                         goto fail;
 377
 378                 if (value == 0xdeadbeef) {
 379                         IFPGA_RAWDEV_PMD_ERR("dev_id %d sensor %s value %x\n",
 380                                         raw_dev->dev_id, sensor->name, value);
 381                         continue;
 382                 }
 383
 384                 /* monitor temperature sensors */
 385                 if (!strcmp(sensor->name, "Board Temperature") ||
 386                                 !strcmp(sensor->name, "FPGA Die Temperature")) {
 387                         IFPGA_RAWDEV_PMD_DEBUG("read sensor %s %d %d %d\n",
 388                                         sensor->name, value, sensor->high_warn,
 389                                         sensor->high_fatal);
 390
 391                         if (HIGH_WARN(sensor, value) ||
 392                                 LOW_WARN(sensor, value)) {
 393                                 IFPGA_RAWDEV_PMD_INFO("%s reach threshold %d\n",
 394                                         sensor->name, value);
 395                                 *gsd_start = true;
 396                                 break;
 397                         }
 398                 }
 399
 400                 /* monitor 12V AUX sensor */
 401                 if (!strcmp(sensor->name, "12V AUX Voltage")) {
 402                         if (value < AUX_VOLTAGE_WARN) {
 403                                 IFPGA_RAWDEV_PMD_INFO(
 404                                         "%s reach threshold %d mV\n",
 405                                         sensor->name, value);
 406                                 *gsd_start = true;
 407                                 break;
 408                         }
 409                 }
 410         }
 411
 412         return 0;
 413 fail:
 414         return -EFAULT;
 415 }
 416
 417 static int set_surprise_link_check_aer(
 418         struct ifpga_rawdev *ifpga_rdev, int force_disable)
 419 {
 420         struct rte_rawdev *rdev;
 421         int fd = -1;
 422         char path[1024];
 423         int pos;
 424         int ret;
 425         uint32_t data;
 426         bool enable = 0;
 427         uint32_t aer_new0, aer_new1;
 428
 429         if (!ifpga_rdev || !ifpga_rdev->rawdev) {
 430                 printf("\n device does not exist\n");
 431                 return -EFAULT;
 432         }
 433
 434         rdev = ifpga_rdev->rawdev;
 435         if (ifpga_rdev->aer_enable)
 436                 return -EFAULT;
 437         if (ifpga_monitor_sensor(rdev, &enable))
 438                 return -EFAULT;
 439         if (enable || force_disable) {
 440                 IFPGA_RAWDEV_PMD_ERR("Set AER, pls graceful shutdown\n");
 441                 ifpga_rdev->aer_enable = 1;
 442                 /* get bridge fd */
 443                 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
 444                 strlcat(path, ifpga_rdev->parent_bdf, sizeof(path));
 445                 strlcat(path, "/config", sizeof(path));
 446                 fd = open(path, O_RDWR);
 447                 if (fd < 0)
 448                         goto end;
 449                 pos = ifpga_pci_find_ext_capability(fd, RTE_PCI_EXT_CAP_ID_ERR);
 450                 if (!pos)
 451                         goto end;
 452                 /* save previous ECAP_AER+0x08 */
 453                 ret = pread(fd, &data, sizeof(data), pos+0x08);
 454                 if (ret == -1)
 455                         goto end;
 456                 ifpga_rdev->aer_old[0] = data;
 457                 /* save previous ECAP_AER+0x14 */
 458                 ret = pread(fd, &data, sizeof(data), pos+0x14);
 459                 if (ret == -1)
 460                         goto end;
 461                 ifpga_rdev->aer_old[1] = data;
 462
 463                 /* set ECAP_AER+0x08 to 0xFFFFFFFF */
 464                 data = 0xffffffff;
 465                 ret = pwrite(fd, &data, 4, pos+0x08);
 466                 if (ret == -1)
 467                         goto end;
 468                 /* set ECAP_AER+0x14 to 0xFFFFFFFF */
 469                 ret = pwrite(fd, &data, 4, pos+0x14);
 470                 if (ret == -1)
 471                         goto end;
 472
 473                 /* read current ECAP_AER+0x08 */
 474                 ret = pread(fd, &data, sizeof(data), pos+0x08);
 475                 if (ret == -1)
 476                         goto end;
 477                 aer_new0 = data;
 478                 /* read current ECAP_AER+0x14 */
 479                 ret = pread(fd, &data, sizeof(data), pos+0x14);
 480                 if (ret == -1)
 481                         goto end;
 482                 aer_new1 = data;
 483
 484                 if (fd != -1)
 485                         close(fd);
 486
 487                 printf(">>>>>>Set AER %x,%x %x,%x\n",
 488                         ifpga_rdev->aer_old[0], ifpga_rdev->aer_old[1],
 489                         aer_new0, aer_new1);
 490
 491                 return 1;
 492                 }
 493
 494 end:
 495         if (fd != -1)
 496                 close(fd);
 497         return -EFAULT;
 498 }
 499
 500 static void *
 501 ifpga_rawdev_gsd_handle(__rte_unused void *param)
 502 {
 503         struct ifpga_rawdev *ifpga_rdev;
 504         int i;
 505         int gsd_enable, ret;
 506 #define MS 1000
 507
 508         while (__atomic_load_n(&ifpga_monitor_refcnt, __ATOMIC_RELAXED)) {
 509                 gsd_enable = 0;
 510                 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
 511                         ifpga_rdev = &ifpga_rawdevices[i];
 512                         if (ifpga_rdev->poll_enabled) {
 513                                 ret = set_surprise_link_check_aer(ifpga_rdev,
 514                                         gsd_enable);
 515                                 if (ret == 1 && !gsd_enable) {
 516                                         gsd_enable = 1;
 517                                         i = -1;
 518                                 }
 519                         }
 520                 }
 521
 522                 if (gsd_enable)
 523                         printf(">>>>>>Pls Shutdown APP\n");
 524
 525                 rte_delay_us(100 * MS);
 526         }
 527
 528         return NULL;
 529 }
 530
 531 static int
 532 ifpga_monitor_start_func(struct ifpga_rawdev *dev)
 533 {
 534         int ret;
 535
 536         if (!dev)
 537                 return -ENODEV;
 538
 539         ret = ifpga_rawdev_fill_info(dev);
 540         if (ret)
 541                 return ret;
 542
 543         dev->poll_enabled = 1;
 544
 545         if (!__atomic_fetch_add(&ifpga_monitor_refcnt, 1, __ATOMIC_RELAXED)) {
 546                 ret = rte_ctrl_thread_create(&ifpga_monitor_start_thread,
 547                                              "ifpga-monitor", NULL,
 548                                              ifpga_rawdev_gsd_handle, NULL);
 549                 if (ret != 0) {
 550                         ifpga_monitor_start_thread = 0;
 551                         IFPGA_RAWDEV_PMD_ERR(
 552                                 "Fail to create ifpga monitor thread");
 553                         return -1;
 554                 }
 555         }
 556
 557         return 0;
 558 }
 559
 560 static int
 561 ifpga_monitor_stop_func(struct ifpga_rawdev *dev)
 562 {
 563         int ret;
 564
 565         if (!dev || !dev->poll_enabled)
 566                 return 0;
 567
 568         dev->poll_enabled = 0;
 569
 570         if (!__atomic_sub_fetch(&ifpga_monitor_refcnt, 1, __ATOMIC_RELAXED) &&
 571                 ifpga_monitor_start_thread) {
 572                 ret = pthread_cancel(ifpga_monitor_start_thread);
 573                 if (ret)
 574                         IFPGA_RAWDEV_PMD_ERR("Can't cancel the thread");
 575
 576                 ret = pthread_join(ifpga_monitor_start_thread, NULL);
 577                 if (ret)
 578                         IFPGA_RAWDEV_PMD_ERR("Can't join the thread");
 579
 580                 return ret;
 581         }
 582
 583         return 0;
 584 }
 585
 586 static int
 587 ifpga_fill_afu_dev(struct opae_accelerator *acc,
 588                 struct rte_afu_device *afu_dev)
 589 {
 590         struct rte_mem_resource *res = afu_dev->mem_resource;
 591         struct opae_acc_region_info region_info;
 592         struct opae_acc_info info;
 593         unsigned long i;
 594         int ret;
 595
 596         ret = opae_acc_get_info(acc, &info);
 597         if (ret)
 598                 return ret;
 599
 600         if (info.num_regions > PCI_MAX_RESOURCE)
 601                 return -EFAULT;
 602
 603         afu_dev->num_region = info.num_regions;
 604
 605         for (i = 0; i < info.num_regions; i++) {
 606                 region_info.index = i;
 607                 ret = opae_acc_get_region_info(acc, &region_info);
 608                 if (ret)
 609                         return ret;
 610
 611                 if ((region_info.flags & ACC_REGION_MMIO) &&
 612                     (region_info.flags & ACC_REGION_READ) &&
 613                     (region_info.flags & ACC_REGION_WRITE)) {
 614                         res[i].phys_addr = region_info.phys_addr;
 615                         res[i].len = region_info.len;
 616                         res[i].addr = region_info.addr;
 617                 } else
 618                         return -EFAULT;
 619         }
 620
 621         return 0;
 622 }
 623
 624 static int
 625 ifpga_rawdev_info_get(struct rte_rawdev *dev,
 626                       rte_rawdev_obj_t dev_info,
 627                       size_t dev_info_size)
 628 {
 629         struct opae_adapter *adapter;
 630         struct opae_accelerator *acc;
 631         struct rte_afu_device *afu_dev;
 632         struct opae_manager *mgr = NULL;
 633         struct opae_eth_group_region_info opae_lside_eth_info;
 634         struct opae_eth_group_region_info opae_nside_eth_info;
 635         int lside_bar_idx, nside_bar_idx;
 636
 637         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 638
 639         if (!dev_info || dev_info_size != sizeof(*afu_dev)) {
 640                 IFPGA_RAWDEV_PMD_ERR("Invalid request");
 641                 return -EINVAL;
 642         }
 643
 644         adapter = ifpga_rawdev_get_priv(dev);
 645         if (!adapter)
 646                 return -ENOENT;
 647
 648         afu_dev = dev_info;
 649         afu_dev->rawdev = dev;
 650
 651         /* find opae_accelerator and fill info into afu_device */
 652         opae_adapter_for_each_acc(adapter, acc) {
 653                 if (acc->index != afu_dev->id.port)
 654                         continue;
 655
 656                 if (ifpga_fill_afu_dev(acc, afu_dev)) {
 657                         IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
 658                         return -ENOENT;
 659                 }
 660         }
 661
 662         /* get opae_manager to rawdev */
 663         mgr = opae_adapter_get_mgr(adapter);
 664         if (mgr) {
 665                 /* get LineSide BAR Index */
 666                 if (opae_manager_get_eth_group_region_info(mgr, 0,
 667                         &opae_lside_eth_info)) {
 668                         return -ENOENT;
 669                 }
 670                 lside_bar_idx = opae_lside_eth_info.mem_idx;
 671
 672                 /* get NICSide BAR Index */
 673                 if (opae_manager_get_eth_group_region_info(mgr, 1,
 674                         &opae_nside_eth_info)) {
 675                         return -ENOENT;
 676                 }
 677                 nside_bar_idx = opae_nside_eth_info.mem_idx;
 678
 679                 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
 680                         nside_bar_idx >= PCI_MAX_RESOURCE ||
 681                         lside_bar_idx == nside_bar_idx)
 682                         return -ENOENT;
 683
 684                 /* fill LineSide BAR Index */
 685                 afu_dev->mem_resource[lside_bar_idx].phys_addr =
 686                         opae_lside_eth_info.phys_addr;
 687                 afu_dev->mem_resource[lside_bar_idx].len =
 688                         opae_lside_eth_info.len;
 689                 afu_dev->mem_resource[lside_bar_idx].addr =
 690                         opae_lside_eth_info.addr;
 691
 692                 /* fill NICSide BAR Index */
 693                 afu_dev->mem_resource[nside_bar_idx].phys_addr =
 694                         opae_nside_eth_info.phys_addr;
 695                 afu_dev->mem_resource[nside_bar_idx].len =
 696                         opae_nside_eth_info.len;
 697                 afu_dev->mem_resource[nside_bar_idx].addr =
 698                         opae_nside_eth_info.addr;
 699         }
 700         return 0;
 701 }
 702
 703 static int
 704 ifpga_rawdev_configure(const struct rte_rawdev *dev,
 705                 rte_rawdev_obj_t config,
 706                 size_t config_size __rte_unused)
 707 {
 708         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 709
 710         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 711
 712         return config ? 0 : 1;
 713 }
 714
 715 static int
 716 ifpga_rawdev_start(struct rte_rawdev *dev)
 717 {
 718         int ret = 0;
 719         struct opae_adapter *adapter;
 720
 721         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 722
 723         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 724
 725         adapter = ifpga_rawdev_get_priv(dev);
 726         if (!adapter)
 727                 return -ENODEV;
 728
 729         return ret;
 730 }
 731
 732 static void
 733 ifpga_rawdev_stop(struct rte_rawdev *dev)
 734 {
 735         dev->started = 0;
 736 }
 737
 738 static int
 739 ifpga_rawdev_close(struct rte_rawdev *dev)
 740 {
 741         struct ifpga_rawdev *ifpga_rdev = NULL;
 742         struct opae_adapter *adapter;
 743         char *vdev_name = NULL;
 744         int i = 0;
 745
 746         if (dev) {
 747                 ifpga_rdev = ifpga_rawdev_get(dev);
 748                 if (ifpga_rdev) {
 749                         for (i = 0; i < IFPGA_MAX_VDEV; i++) {
 750                                 vdev_name = ifpga_rdev->vdev_name[i];
 751                                 if (vdev_name)
 752                                         rte_vdev_uninit(vdev_name);
 753                         }
 754                         ifpga_monitor_stop_func(ifpga_rdev);
 755                         ifpga_rdev->rawdev = NULL;
 756                 }
 757                 adapter = ifpga_rawdev_get_priv(dev);
 758                 if (adapter) {
 759                         opae_adapter_destroy(adapter);
 760                         opae_adapter_data_free(adapter->data);
 761                 }
 762         }
 763
 764         return dev ? 0:1;
 765 }
 766
 767 static int
 768 ifpga_rawdev_reset(struct rte_rawdev *dev)
 769 {
 770         return dev ? 0:1;
 771 }
 772
 773 static int
 774 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size,
 775                         u64 *status)
 776 {
 777
 778         struct opae_adapter *adapter;
 779         struct opae_manager *mgr;
 780         struct opae_accelerator *acc;
 781         struct opae_bridge *br;
 782         int ret;
 783
 784         adapter = ifpga_rawdev_get_priv(raw_dev);
 785         if (!adapter)
 786                 return -ENODEV;
 787
 788         mgr = opae_adapter_get_mgr(adapter);
 789         if (!mgr)
 790                 return -ENODEV;
 791
 792         acc = opae_adapter_get_acc(adapter, port_id);
 793         if (!acc)
 794                 return -ENODEV;
 795
 796         br = opae_acc_get_br(acc);
 797         if (!br)
 798                 return -ENODEV;
 799
 800         ret = opae_manager_flash(mgr, port_id, buffer, size, status);
 801         if (ret) {
 802                 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
 803                 return ret;
 804         }
 805
 806         ret = opae_bridge_reset(br);
 807         if (ret) {
 808                 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
 809                                 __func__, port_id, ret);
 810                 return ret;
 811         }
 812
 813         return ret;
 814 }
 815
 816 static int
 817 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
 818                 const char *file_name)
 819 {
 820         struct stat file_stat;
 821         int file_fd;
 822         int ret = 0;
 823         ssize_t buffer_size;
 824         void *buffer, *buf_to_free;
 825         u64 pr_error;
 826
 827         if (!file_name)
 828                 return -EINVAL;
 829
 830         file_fd = open(file_name, O_RDONLY);
 831         if (file_fd < 0) {
 832                 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
 833                                 __func__, file_name);
 834                 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
 835                 return -EINVAL;
 836         }
 837         ret = stat(file_name, &file_stat);
 838         if (ret) {
 839                 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
 840                                 file_name);
 841                 ret = -EINVAL;
 842                 goto close_fd;
 843         }
 844         buffer_size = file_stat.st_size;
 845         if (buffer_size <= 0) {
 846                 ret = -EINVAL;
 847                 goto close_fd;
 848         }
 849
 850         IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
 851         buffer = rte_malloc(NULL, buffer_size, 0);
 852         if (!buffer) {
 853                 ret = -ENOMEM;
 854                 goto close_fd;
 855         }
 856         buf_to_free = buffer;
 857
 858         /*read the raw data*/
 859         if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
 860                 ret = -EINVAL;
 861                 goto free_buffer;
 862         }
 863
 864         /*do PR now*/
 865         ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
 866         IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
 867                 ret ? "failed" : "success");
 868         if (ret) {
 869                 ret = -EINVAL;
 870                 goto free_buffer;
 871         }
 872
 873 free_buffer:
 874         rte_free(buf_to_free);
 875 close_fd:
 876         close(file_fd);
 877         file_fd = 0;
 878         return ret;
 879 }
 880
 881 static int
 882 ifpga_rawdev_pr(struct rte_rawdev *dev,
 883         rte_rawdev_obj_t pr_conf)
 884 {
 885         struct opae_adapter *adapter;
 886         struct opae_manager *mgr;
 887         struct opae_board_info *info;
 888         struct rte_afu_pr_conf *afu_pr_conf;
 889         int ret;
 890         struct uuid uuid;
 891         struct opae_accelerator *acc;
 892
 893         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 894
 895         adapter = ifpga_rawdev_get_priv(dev);
 896         if (!adapter)
 897                 return -ENODEV;
 898
 899         if (!pr_conf)
 900                 return -EINVAL;
 901
 902         afu_pr_conf = pr_conf;
 903
 904         if (afu_pr_conf->pr_enable) {
 905                 ret = rte_fpga_do_pr(dev,
 906                                 afu_pr_conf->afu_id.port,
 907                                 afu_pr_conf->bs_path);
 908                 if (ret) {
 909                         IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
 910                         return ret;
 911                 }
 912         }
 913
 914         mgr = opae_adapter_get_mgr(adapter);
 915         if (!mgr) {
 916                 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
 917                 return -1;
 918         }
 919
 920         if (ifpga_mgr_ops.get_board_info(mgr, &info)) {
 921                 IFPGA_RAWDEV_PMD_ERR("ifpga manager get_board_info fail!");
 922                 return -1;
 923         }
 924
 925         if (info->lightweight) {
 926                 /* set uuid to all 0, when fpga is lightweight image */
 927                 memset(&afu_pr_conf->afu_id.uuid.uuid_low, 0, sizeof(u64));
 928                 memset(&afu_pr_conf->afu_id.uuid.uuid_high, 0, sizeof(u64));
 929         } else {
 930                 acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
 931                 if (!acc)
 932                         return -ENODEV;
 933
 934                 ret = opae_acc_get_uuid(acc, &uuid);
 935                 if (ret)
 936                         return ret;
 937
 938                 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b,
 939                         sizeof(u64));
 940                 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high, uuid.b + 8,
 941                         sizeof(u64));
 942
 943                 IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n",
 944                         __func__,
 945                         (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
 946                         (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
 947                 }
 948         return 0;
 949 }
 950
 951 static int
 952 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
 953         const char *attr_name, uint64_t *attr_value)
 954 {
 955         struct opae_adapter *adapter;
 956         struct opae_manager *mgr;
 957         struct opae_retimer_info opae_rtm_info;
 958         struct opae_retimer_status opae_rtm_status;
 959         struct opae_eth_group_info opae_eth_grp_info;
 960         struct opae_eth_group_region_info opae_eth_grp_reg_info;
 961         int eth_group_num = 0;
 962         uint64_t port_link_bitmap = 0, port_link_bit;
 963         uint32_t i, j, p, q;
 964
 965 #define MAX_PORT_PER_RETIMER    4
 966
 967         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 968
 969         if (!dev || !attr_name || !attr_value) {
 970                 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
 971                 return -1;
 972         }
 973
 974         adapter = ifpga_rawdev_get_priv(dev);
 975         if (!adapter) {
 976                 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
 977                 return -1;
 978         }
 979
 980         mgr = opae_adapter_get_mgr(adapter);
 981         if (!mgr) {
 982                 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
 983                 return -1;
 984         }
 985
 986         /* currently, eth_group_num is always 2 */
 987         eth_group_num = opae_manager_get_eth_group_nums(mgr);
 988         if (eth_group_num < 0)
 989                 return -1;
 990
 991         if (!strcmp(attr_name, "LineSideBaseMAC")) {
 992                 /* Currently FPGA not implement, so just set all zeros*/
 993                 *attr_value = (uint64_t)0;
 994                 return 0;
 995         }
 996         if (!strcmp(attr_name, "LineSideMACType")) {
 997                 /* eth_group 0 on FPGA connect to LineSide */
 998                 if (opae_manager_get_eth_group_info(mgr, 0,
 999                         &opae_eth_grp_info))
1000                         return -1;
1001                 switch (opae_eth_grp_info.speed) {
1002                 case ETH_SPEED_10G:
1003                         *attr_value =
1004                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
1005                         break;
1006                 case ETH_SPEED_25G:
1007                         *attr_value =
1008                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
1009                         break;
1010                 default:
1011                         *attr_value =
1012                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
1013                         break;
1014                 }
1015                 return 0;
1016         }
1017         if (!strcmp(attr_name, "LineSideLinkSpeed")) {
1018                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1019                         return -1;
1020                 switch (opae_rtm_status.speed) {
1021                 case MXD_1GB:
1022                         *attr_value =
1023                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1024                         break;
1025                 case MXD_2_5GB:
1026                         *attr_value =
1027                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1028                         break;
1029                 case MXD_5GB:
1030                         *attr_value =
1031                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1032                         break;
1033                 case MXD_10GB:
1034                         *attr_value =
1035                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
1036                         break;
1037                 case MXD_25GB:
1038                         *attr_value =
1039                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
1040                         break;
1041                 case MXD_40GB:
1042                         *attr_value =
1043                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
1044                         break;
1045                 case MXD_100GB:
1046                         *attr_value =
1047                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1048                         break;
1049                 case MXD_SPEED_UNKNOWN:
1050                         *attr_value =
1051                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1052                         break;
1053                 default:
1054                         *attr_value =
1055                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1056                         break;
1057                 }
1058                 return 0;
1059         }
1060         if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
1061                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1062                         return -1;
1063                 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
1064                 return 0;
1065         }
1066         if (!strcmp(attr_name, "LineSideLinkPortNum")) {
1067                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1068                         return -1;
1069                 uint64_t tmp = (uint64_t)opae_rtm_info.ports_per_retimer *
1070                                         (uint64_t)opae_rtm_info.nums_retimer;
1071                 *attr_value = tmp;
1072                 return 0;
1073         }
1074         if (!strcmp(attr_name, "LineSideLinkStatus")) {
1075                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1076                         return -1;
1077                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1078                         return -1;
1079                 (*attr_value) = 0;
1080                 q = 0;
1081                 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
1082                 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
1083                         p = i * MAX_PORT_PER_RETIMER;
1084                         for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
1085                                 port_link_bit = 0;
1086                                 IFPGA_BIT_SET(port_link_bit, (p+j));
1087                                 port_link_bit &= port_link_bitmap;
1088                                 if (port_link_bit)
1089                                         IFPGA_BIT_SET((*attr_value), q);
1090                                 q++;
1091                         }
1092                 }
1093                 return 0;
1094         }
1095         if (!strcmp(attr_name, "LineSideBARIndex")) {
1096                 /* eth_group 0 on FPGA connect to LineSide */
1097                 if (opae_manager_get_eth_group_region_info(mgr, 0,
1098                         &opae_eth_grp_reg_info))
1099                         return -1;
1100                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1101                 return 0;
1102         }
1103         if (!strcmp(attr_name, "NICSideMACType")) {
1104                 /* eth_group 1 on FPGA connect to NicSide */
1105                 if (opae_manager_get_eth_group_info(mgr, 1,
1106                         &opae_eth_grp_info))
1107                         return -1;
1108                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1109                 return 0;
1110         }
1111         if (!strcmp(attr_name, "NICSideLinkSpeed")) {
1112                 /* eth_group 1 on FPGA connect to NicSide */
1113                 if (opae_manager_get_eth_group_info(mgr, 1,
1114                         &opae_eth_grp_info))
1115                         return -1;
1116                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1117                 return 0;
1118         }
1119         if (!strcmp(attr_name, "NICSideLinkPortNum")) {
1120                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1121                         return -1;
1122                 uint64_t tmp = (uint64_t)opae_rtm_info.nums_fvl *
1123                                         (uint64_t)opae_rtm_info.ports_per_fvl;
1124                 *attr_value = tmp;
1125                 return 0;
1126         }
1127         if (!strcmp(attr_name, "NICSideLinkStatus"))
1128                 return 0;
1129         if (!strcmp(attr_name, "NICSideBARIndex")) {
1130                 /* eth_group 1 on FPGA connect to NicSide */
1131                 if (opae_manager_get_eth_group_region_info(mgr, 1,
1132                         &opae_eth_grp_reg_info))
1133                         return -1;
1134                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1135                 return 0;
1136         }
1137
1138         IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
1139         return -1;
1140 }
1141
1142 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
1143         .dev_info_get = ifpga_rawdev_info_get,
1144         .dev_configure = ifpga_rawdev_configure,
1145         .dev_start = ifpga_rawdev_start,
1146         .dev_stop = ifpga_rawdev_stop,
1147         .dev_close = ifpga_rawdev_close,
1148         .dev_reset = ifpga_rawdev_reset,
1149
1150         .queue_def_conf = NULL,
1151         .queue_setup = NULL,
1152         .queue_release = NULL,
1153
1154         .attr_get = ifpga_rawdev_get_attr,
1155         .attr_set = NULL,
1156
1157         .enqueue_bufs = NULL,
1158         .dequeue_bufs = NULL,
1159
1160         .dump = NULL,
1161
1162         .xstats_get = NULL,
1163         .xstats_get_names = NULL,
1164         .xstats_get_by_name = NULL,
1165         .xstats_reset = NULL,
1166
1167         .firmware_status_get = NULL,
1168         .firmware_version_get = NULL,
1169         .firmware_load = ifpga_rawdev_pr,
1170         .firmware_unload = NULL,
1171
1172         .dev_selftest = NULL,
1173 };
1174
1175 static int
1176 ifpga_get_fme_error_prop(struct opae_manager *mgr,
1177                 u64 prop_id, u64 *val)
1178 {
1179         struct feature_prop prop;
1180
1181         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1182         prop.prop_id = prop_id;
1183
1184         if (opae_manager_ifpga_get_prop(mgr, &prop))
1185                 return -EINVAL;
1186
1187         *val = prop.data;
1188
1189         return 0;
1190 }
1191
1192 static int
1193 ifpga_set_fme_error_prop(struct opae_manager *mgr,
1194                 u64 prop_id, u64 val)
1195 {
1196         struct feature_prop prop;
1197
1198         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1199         prop.prop_id = prop_id;
1200
1201         prop.data = val;
1202
1203         if (opae_manager_ifpga_set_prop(mgr, &prop))
1204                 return -EINVAL;
1205
1206         return 0;
1207 }
1208
1209 static int
1210 fme_err_read_seu_emr(struct opae_manager *mgr)
1211 {
1212         u64 val;
1213         int ret;
1214
1215         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
1216         if (ret)
1217                 return -EINVAL;
1218
1219         IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%" PRIx64 "\n", val);
1220
1221         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
1222         if (ret)
1223                 return -EINVAL;
1224
1225         IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%" PRIx64 "\n", val);
1226
1227         return 0;
1228 }
1229
1230 static int fme_clear_warning_intr(struct opae_manager *mgr)
1231 {
1232         u64 val;
1233
1234         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
1235                 return -EINVAL;
1236
1237         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1238                 return -EINVAL;
1239         if ((val & 0x40) != 0)
1240                 IFPGA_RAWDEV_PMD_INFO("clean not done\n");
1241
1242         return 0;
1243 }
1244
1245 static int fme_clean_fme_error(struct opae_manager *mgr)
1246 {
1247         u64 val;
1248
1249         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1250                 return -EINVAL;
1251
1252         IFPGA_RAWDEV_PMD_DEBUG("before clean 0x%" PRIx64 "\n", val);
1253
1254         ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_CLEAR, val);
1255
1256         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1257                 return -EINVAL;
1258
1259         IFPGA_RAWDEV_PMD_DEBUG("after clean 0x%" PRIx64 "\n", val);
1260
1261         return 0;
1262 }
1263
1264 static int
1265 fme_err_handle_error0(struct opae_manager *mgr)
1266 {
1267         struct feature_fme_error0 fme_error0;
1268         u64 val;
1269
1270         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1271                 return -EINVAL;
1272
1273         if (fme_clean_fme_error(mgr))
1274                 return -EINVAL;
1275
1276         fme_error0.csr = val;
1277
1278         if (fme_error0.fabric_err)
1279                 IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
1280         else if (fme_error0.fabfifo_overflow)
1281                 IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
1282         else if (fme_error0.afu_acc_mode_err)
1283                 IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
1284         else if (fme_error0.pcie0cdc_parity_err)
1285                 IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
1286         else if (fme_error0.cvlcdc_parity_err)
1287                 IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
1288         else if (fme_error0.fpgaseuerr)
1289                 fme_err_read_seu_emr(mgr);
1290
1291         /* clean the errors */
1292         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
1293                 return -EINVAL;
1294
1295         return 0;
1296 }
1297
1298 static int
1299 fme_err_handle_catfatal_error(struct opae_manager *mgr)
1300 {
1301         struct feature_fme_ras_catfaterror fme_catfatal;
1302         u64 val;
1303
1304         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
1305                 return -EINVAL;
1306
1307         fme_catfatal.csr = val;
1308
1309         if (fme_catfatal.cci_fatal_err)
1310                 IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
1311         else if (fme_catfatal.fabric_fatal_err)
1312                 IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
1313         else if (fme_catfatal.pcie_poison_err)
1314                 IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
1315         else if (fme_catfatal.inject_fata_err)
1316                 IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
1317         else if (fme_catfatal.crc_catast_err)
1318                 IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
1319         else if (fme_catfatal.injected_catast_err)
1320                 IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
1321         else if (fme_catfatal.bmc_seu_catast_err)
1322                 fme_err_read_seu_emr(mgr);
1323
1324         return 0;
1325 }
1326
1327 static int
1328 fme_err_handle_nonfaterror(struct opae_manager *mgr)
1329 {
1330         struct feature_fme_ras_nonfaterror nonfaterr;
1331         u64 val;
1332
1333         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1334                 return -EINVAL;
1335
1336         nonfaterr.csr = val;
1337
1338         if (nonfaterr.temp_thresh_ap1)
1339                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP1\n");
1340         else if (nonfaterr.temp_thresh_ap2)
1341                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP2\n");
1342         else if (nonfaterr.pcie_error)
1343                 IFPGA_RAWDEV_PMD_INFO("an error has occurred in pcie\n");
1344         else if (nonfaterr.portfatal_error)
1345                 IFPGA_RAWDEV_PMD_INFO("fatal error occurred in AFU port.\n");
1346         else if (nonfaterr.proc_hot)
1347                 IFPGA_RAWDEV_PMD_INFO("a ProcHot event\n");
1348         else if (nonfaterr.afu_acc_mode_err)
1349                 IFPGA_RAWDEV_PMD_INFO("an AFU PF/VF access mismatch\n");
1350         else if (nonfaterr.injected_nonfata_err) {
1351                 IFPGA_RAWDEV_PMD_INFO("Injected Warning Error\n");
1352                 fme_clear_warning_intr(mgr);
1353         } else if (nonfaterr.temp_thresh_AP6)
1354                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP6\n");
1355         else if (nonfaterr.power_thresh_AP1)
1356                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP1\n");
1357         else if (nonfaterr.power_thresh_AP2)
1358                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP2\n");
1359         else if (nonfaterr.mbp_err)
1360                 IFPGA_RAWDEV_PMD_INFO("an MBP event\n");
1361
1362         return 0;
1363 }
1364
1365 static void
1366 fme_interrupt_handler(void *param)
1367 {
1368         struct opae_manager *mgr = (struct opae_manager *)param;
1369
1370         IFPGA_RAWDEV_PMD_INFO("%s interrupt occurred\n", __func__);
1371
1372         fme_err_handle_error0(mgr);
1373         fme_err_handle_nonfaterror(mgr);
1374         fme_err_handle_catfatal_error(mgr);
1375 }
1376
1377 int
1378 ifpga_unregister_msix_irq(struct ifpga_rawdev *dev, enum ifpga_irq_type type,
1379                 int vec_start, rte_intr_callback_fn handler, void *arg)
1380 {
1381         struct rte_intr_handle **intr_handle;
1382         int rc = 0;
1383         int i = vec_start + 1;
1384
1385         if (!dev)
1386                 return -ENODEV;
1387
1388         if (type == IFPGA_FME_IRQ)
1389                 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[0];
1390         else if (type == IFPGA_AFU_IRQ)
1391                 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[i];
1392         else
1393                 return -EINVAL;
1394
1395         if ((*intr_handle) == NULL) {
1396                 IFPGA_RAWDEV_PMD_ERR("%s interrupt %d not registered\n",
1397                         type == IFPGA_FME_IRQ ? "FME" : "AFU",
1398                         type == IFPGA_FME_IRQ ? 0 : vec_start);
1399                 return -ENOENT;
1400         }
1401
1402         rte_intr_efd_disable(*intr_handle);
1403
1404         rc = rte_intr_callback_unregister(*intr_handle, handler, arg);
1405         if (rc < 0) {
1406                 IFPGA_RAWDEV_PMD_ERR("Failed to unregister %s interrupt %d\n",
1407                         type == IFPGA_FME_IRQ ? "FME" : "AFU",
1408                         type == IFPGA_FME_IRQ ? 0 : vec_start);
1409         } else {
1410                 rte_intr_instance_free(*intr_handle);
1411                 *intr_handle = NULL;
1412         }
1413
1414         return rc;
1415 }
1416
1417 int
1418 ifpga_register_msix_irq(struct ifpga_rawdev *dev, int port_id,
1419                 enum ifpga_irq_type type, int vec_start, int count,
1420                 rte_intr_callback_fn handler, const char *name,
1421                 void *arg)
1422 {
1423         int ret;
1424         struct rte_intr_handle **intr_handle;
1425         struct opae_adapter *adapter;
1426         struct opae_manager *mgr;
1427         struct opae_accelerator *acc;
1428         int *intr_efds = NULL, nb_intr, i;
1429
1430         if (!dev || !dev->rawdev)
1431                 return -ENODEV;
1432
1433         adapter = ifpga_rawdev_get_priv(dev->rawdev);
1434         if (!adapter)
1435                 return -ENODEV;
1436
1437         mgr = opae_adapter_get_mgr(adapter);
1438         if (!mgr)
1439                 return -ENODEV;
1440
1441         if (type == IFPGA_FME_IRQ) {
1442                 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[0];
1443                 count = 1;
1444         } else if (type == IFPGA_AFU_IRQ) {
1445                 i = vec_start + 1;
1446                 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[i];
1447         } else {
1448                 return -EINVAL;
1449         }
1450
1451         if (*intr_handle)
1452                 return -EBUSY;
1453
1454         *intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
1455         if (!(*intr_handle))
1456                 return -ENOMEM;
1457
1458         if (rte_intr_type_set(*intr_handle, RTE_INTR_HANDLE_VFIO_MSIX))
1459                 return -rte_errno;
1460
1461         ret = rte_intr_efd_enable(*intr_handle, count);
1462         if (ret)
1463                 return -ENODEV;
1464
1465         if (rte_intr_fd_set(*intr_handle,
1466                         rte_intr_efds_index_get(*intr_handle, 0)))
1467                 return -rte_errno;
1468
1469         IFPGA_RAWDEV_PMD_DEBUG("register %s irq, vfio_fd=%d, fd=%d\n",
1470                         name, rte_intr_dev_fd_get(*intr_handle),
1471                         rte_intr_fd_get(*intr_handle));
1472
1473         if (type == IFPGA_FME_IRQ) {
1474                 struct fpga_fme_err_irq_set err_irq_set;
1475                 err_irq_set.evtfd = rte_intr_efds_index_get(*intr_handle,
1476                                                                    0);
1477
1478                 ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
1479                 if (ret)
1480                         return -EINVAL;
1481         } else if (type == IFPGA_AFU_IRQ) {
1482                 acc = opae_adapter_get_acc(adapter, port_id);
1483                 if (!acc)
1484                         return -EINVAL;
1485
1486                 nb_intr = rte_intr_nb_intr_get(*intr_handle);
1487
1488                 intr_efds = calloc(nb_intr, sizeof(int));
1489                 if (!intr_efds)
1490                         return -ENOMEM;
1491
1492                 for (i = 0; i < nb_intr; i++)
1493                         intr_efds[i] = rte_intr_efds_index_get(*intr_handle, i);
1494
1495                 ret = opae_acc_set_irq(acc, vec_start, count, intr_efds);
1496                 if (ret) {
1497                         free(intr_efds);
1498                         return -EINVAL;
1499                 }
1500         }
1501
1502         /* register interrupt handler using DPDK API */
1503         ret = rte_intr_callback_register(*intr_handle,
1504                         handler, (void *)arg);
1505         if (ret) {
1506                 free(intr_efds);
1507                 return -EINVAL;
1508         }
1509
1510         IFPGA_RAWDEV_PMD_INFO("success register %s interrupt\n", name);
1511
1512         free(intr_efds);
1513         return 0;
1514 }
1515
1516 static int
1517 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
1518                         int socket_id)
1519 {
1520         int ret = 0;
1521         struct rte_rawdev *rawdev = NULL;
1522         struct ifpga_rawdev *dev = NULL;
1523         struct opae_adapter *adapter = NULL;
1524         struct opae_manager *mgr = NULL;
1525         struct opae_adapter_data_pci *data = NULL;
1526         char name[RTE_RAWDEV_NAME_MAX_LEN];
1527         int i;
1528
1529         if (!pci_dev) {
1530                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1531                 ret = -EINVAL;
1532                 goto cleanup;
1533         }
1534
1535         memset(name, 0, sizeof(name));
1536         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, IFPGA_RAWDEV_NAME_FMT,
1537                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1538
1539         IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
1540
1541         /* Allocate device structure */
1542         rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
1543                                          socket_id);
1544         if (rawdev == NULL) {
1545                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
1546                 ret = -EINVAL;
1547                 goto cleanup;
1548         }
1549
1550         ipn3ke_bridge_func.get_ifpga_rawdev = ifpga_rawdev_get;
1551         ipn3ke_bridge_func.set_i40e_sw_dev = rte_pmd_i40e_set_switch_dev;
1552
1553         dev = ifpga_rawdev_allocate(rawdev);
1554         if (dev == NULL) {
1555                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate ifpga_rawdevice");
1556                 ret = -EINVAL;
1557                 goto cleanup;
1558         }
1559         dev->aer_enable = 0;
1560
1561         /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
1562         data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
1563         if (!data) {
1564                 ret = -ENOMEM;
1565                 goto cleanup;
1566         }
1567
1568         /* init opae_adapter_data_pci for device specific information */
1569         for (i = 0; i < PCI_MAX_RESOURCE; i++) {
1570                 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
1571                 data->region[i].len = pci_dev->mem_resource[i].len;
1572                 data->region[i].addr = pci_dev->mem_resource[i].addr;
1573         }
1574         data->device_id = pci_dev->id.device_id;
1575         data->vendor_id = pci_dev->id.vendor_id;
1576         data->bus = pci_dev->addr.bus;
1577         data->devid = pci_dev->addr.devid;
1578         data->function = pci_dev->addr.function;
1579         data->vfio_dev_fd = rte_intr_dev_fd_get(pci_dev->intr_handle);
1580
1581         adapter = rawdev->dev_private;
1582         /* create a opae_adapter based on above device data */
1583         ret = opae_adapter_init(adapter, pci_dev->device.name, data);
1584         if (ret) {
1585                 ret = -ENOMEM;
1586                 goto free_adapter_data;
1587         }
1588
1589         rawdev->dev_ops = &ifpga_rawdev_ops;
1590         rawdev->device = &pci_dev->device;
1591         rawdev->driver_name = pci_dev->driver->driver.name;
1592
1593         /* must enumerate the adapter before use it */
1594         ret = opae_adapter_enumerate(adapter);
1595         if (ret)
1596                 goto free_adapter_data;
1597
1598         /* get opae_manager to rawdev */
1599         mgr = opae_adapter_get_mgr(adapter);
1600         if (mgr) {
1601                 /* PF function */
1602                 IFPGA_RAWDEV_PMD_INFO("this is a PF function");
1603         }
1604
1605         ret = ifpga_register_msix_irq(dev, 0, IFPGA_FME_IRQ, 0, 0,
1606                         fme_interrupt_handler, "fme_irq", mgr);
1607         if (ret)
1608                 goto free_adapter_data;
1609
1610         ret = ifpga_monitor_start_func(dev);
1611         if (ret)
1612                 goto free_adapter_data;
1613
1614         return ret;
1615
1616 free_adapter_data:
1617         if (data)
1618                 opae_adapter_data_free(data);
1619 cleanup:
1620         if (rawdev)
1621                 rte_rawdev_pmd_release(rawdev);
1622
1623         return ret;
1624 }
1625
1626 static int
1627 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
1628 {
1629         int ret;
1630         struct rte_rawdev *rawdev;
1631         char name[RTE_RAWDEV_NAME_MAX_LEN];
1632         struct opae_adapter *adapter;
1633         struct opae_manager *mgr;
1634         struct ifpga_rawdev *dev;
1635
1636         if (!pci_dev) {
1637                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1638                 ret = -EINVAL;
1639                 return ret;
1640         }
1641
1642         memset(name, 0, sizeof(name));
1643         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, IFPGA_RAWDEV_NAME_FMT,
1644                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1645
1646         IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
1647                 name, rte_socket_id());
1648
1649         rawdev = rte_rawdev_pmd_get_named_dev(name);
1650         if (!rawdev) {
1651                 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
1652                 return -EINVAL;
1653         }
1654         dev = ifpga_rawdev_get(rawdev);
1655
1656         adapter = ifpga_rawdev_get_priv(rawdev);
1657         if (!adapter)
1658                 return -ENODEV;
1659
1660         mgr = opae_adapter_get_mgr(adapter);
1661         if (!mgr)
1662                 return -ENODEV;
1663
1664         if (ifpga_unregister_msix_irq(dev, IFPGA_FME_IRQ, 0,
1665                                 fme_interrupt_handler, mgr) < 0)
1666                 return -EINVAL;
1667
1668         /* rte_rawdev_close is called by pmd_release */
1669         ret = rte_rawdev_pmd_release(rawdev);
1670         if (ret)
1671                 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
1672
1673         return ret;
1674 }
1675
1676 static int
1677 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1678         struct rte_pci_device *pci_dev)
1679 {
1680         IFPGA_RAWDEV_PMD_FUNC_TRACE();
1681         return ifpga_rawdev_create(pci_dev, rte_socket_id());
1682 }
1683
1684 static int
1685 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
1686 {
1687         IFPGA_RAWDEV_PMD_INFO("remove pci_dev %s", pci_dev->device.name);
1688         return ifpga_rawdev_destroy(pci_dev);
1689 }
1690
1691 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
1692         .id_table  = pci_ifpga_map,
1693         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1694         .probe     = ifpga_rawdev_pci_probe,
1695         .remove    = ifpga_rawdev_pci_remove,
1696 };
1697
1698 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1699 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1700 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
1701 RTE_LOG_REGISTER_DEFAULT(ifpga_rawdev_logtype, NOTICE);
1702
1703 static const char * const valid_args[] = {
1704 #define IFPGA_ARG_NAME         "ifpga"
1705         IFPGA_ARG_NAME,
1706 #define IFPGA_ARG_PORT         "port"
1707         IFPGA_ARG_PORT,
1708 #define IFPGA_AFU_BTS          "afu_bts"
1709         IFPGA_AFU_BTS,
1710         NULL
1711 };
1712
1713 static int ifpga_rawdev_get_string_arg(const char *key __rte_unused,
1714         const char *value, void *extra_args)
1715 {
1716         int size;
1717         if (!value || !extra_args)
1718                 return -EINVAL;
1719
1720         size = strlen(value) + 1;
1721         *(char **)extra_args = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
1722         if (!*(char **)extra_args)
1723                 return -ENOMEM;
1724
1725         strlcpy(*(char **)extra_args, value, size);
1726
1727         return 0;
1728 }
1729
1730 static int
1731 ifpga_vdev_parse_devargs(struct rte_devargs *devargs,
1732         struct ifpga_vdev_args *args)
1733 {
1734         struct rte_kvargs *kvlist;
1735         char *name = NULL;
1736         int port = 0;
1737         int ret = -EINVAL;
1738
1739         if (!devargs || !args)
1740                 return ret;
1741
1742         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1743         if (!kvlist) {
1744                 IFPGA_RAWDEV_PMD_ERR("error when parsing devargs");
1745                 return ret;
1746         }
1747
1748         if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
1749                 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
1750                         &ifpga_rawdev_get_string_arg, &name) < 0) {
1751                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1752                                 IFPGA_ARG_NAME);
1753                         goto end;
1754                 } else {
1755                         strlcpy(args->bdf, name, sizeof(args->bdf));
1756                         rte_free(name);
1757                 }
1758         } else {
1759                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1760                         IFPGA_ARG_NAME);
1761                 goto end;
1762         }
1763
1764         if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
1765                 if (rte_kvargs_process(kvlist, IFPGA_ARG_PORT,
1766                         &rte_ifpga_get_integer32_arg, &port) < 0) {
1767                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1768                                 IFPGA_ARG_PORT);
1769                         goto end;
1770                 } else {
1771                         args->port = port;
1772                 }
1773         } else {
1774                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1775                         IFPGA_ARG_PORT);
1776                 goto end;
1777         }
1778
1779         ret = 0;
1780
1781 end:
1782         if (kvlist)
1783                 rte_kvargs_free(kvlist);
1784
1785         return ret;
1786 }
1787
1788 static int
1789 ifpga_cfg_probe(struct rte_vdev_device *vdev)
1790 {
1791         struct rte_rawdev *rawdev = NULL;
1792         struct ifpga_rawdev *ifpga_dev;
1793         struct ifpga_vdev_args args;
1794         char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1795         const char *vdev_name = NULL;
1796         int i, n, ret = 0;
1797
1798         vdev_name = rte_vdev_device_name(vdev);
1799         if (!vdev_name)
1800                 return -EINVAL;
1801
1802         IFPGA_RAWDEV_PMD_INFO("probe ifpga virtual device %s", vdev_name);
1803
1804         ret = ifpga_vdev_parse_devargs(vdev->device.devargs, &args);
1805         if (ret)
1806                 return ret;
1807
1808         memset(dev_name, 0, sizeof(dev_name));
1809         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", args.bdf);
1810         rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1811         if (!rawdev)
1812                 return -ENODEV;
1813         ifpga_dev = ifpga_rawdev_get(rawdev);
1814         if (!ifpga_dev)
1815                 return -ENODEV;
1816
1817         for (i = 0; i < IFPGA_MAX_VDEV; i++) {
1818                 if (ifpga_dev->vdev_name[i] == NULL) {
1819                         n = strlen(vdev_name) + 1;
1820                         ifpga_dev->vdev_name[i] = rte_malloc(NULL, n, 0);
1821                         if (ifpga_dev->vdev_name[i] == NULL)
1822                                 return -ENOMEM;
1823                         strlcpy(ifpga_dev->vdev_name[i], vdev_name, n);
1824                         break;
1825                 }
1826         }
1827
1828         if (i >= IFPGA_MAX_VDEV) {
1829                 IFPGA_RAWDEV_PMD_ERR("Can't create more virtual device!");
1830                 return -ENOENT;
1831         }
1832
1833         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1834                 args.port, args.bdf);
1835         ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
1836                         dev_name, vdev->device.devargs->args);
1837         if (ret) {
1838                 rte_free(ifpga_dev->vdev_name[i]);
1839                 ifpga_dev->vdev_name[i] = NULL;
1840         }
1841
1842         return ret;
1843 }
1844
1845 static int
1846 ifpga_cfg_remove(struct rte_vdev_device *vdev)
1847 {
1848         struct rte_rawdev *rawdev = NULL;
1849         struct ifpga_rawdev *ifpga_dev;
1850         struct ifpga_vdev_args args;
1851         char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1852         const char *vdev_name = NULL;
1853         char *tmp_vdev = NULL;
1854         int i, ret = 0;
1855
1856         vdev_name = rte_vdev_device_name(vdev);
1857         if (!vdev_name)
1858                 return -EINVAL;
1859
1860         IFPGA_RAWDEV_PMD_INFO("remove ifpga virtual device %s", vdev_name);
1861
1862         ret = ifpga_vdev_parse_devargs(vdev->device.devargs, &args);
1863         if (ret)
1864                 return ret;
1865
1866         memset(dev_name, 0, sizeof(dev_name));
1867         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", args.bdf);
1868         rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1869         if (!rawdev)
1870                 return -ENODEV;
1871         ifpga_dev = ifpga_rawdev_get(rawdev);
1872         if (!ifpga_dev)
1873                 return -ENODEV;
1874
1875         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1876                 args.port, args.bdf);
1877         ret = rte_eal_hotplug_remove(RTE_STR(IFPGA_BUS_NAME), dev_name);
1878
1879         for (i = 0; i < IFPGA_MAX_VDEV; i++) {
1880                 tmp_vdev = ifpga_dev->vdev_name[i];
1881                 if (tmp_vdev && !strcmp(tmp_vdev, vdev_name)) {
1882                         free(tmp_vdev);
1883                         ifpga_dev->vdev_name[i] = NULL;
1884                         break;
1885                 }
1886         }
1887
1888         return ret;
1889 }
1890
1891 static struct rte_vdev_driver ifpga_cfg_driver = {
1892         .probe = ifpga_cfg_probe,
1893         .remove = ifpga_cfg_remove,
1894 };
1895
1896 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
1897 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
1898 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,
1899         "ifpga=<string> "
1900         "port=<int> "
1901         "afu_bts=<path>");
1902
1903 struct rte_pci_bus *ifpga_get_pci_bus(void)
1904 {
1905         return rte_ifpga_rawdev_pmd.bus;
1906 }
1907
1908 int ifpga_rawdev_partial_reconfigure(struct rte_rawdev *dev, int port,
1909         const char *file)
1910 {
1911         if (!dev) {
1912                 IFPGA_RAWDEV_PMD_ERR("Input parameter is invalid");
1913                 return -EINVAL;
1914         }
1915
1916         return rte_fpga_do_pr(dev, port, file);
1917 }
1918
1919 void ifpga_rawdev_cleanup(void)
1920 {
1921         struct ifpga_rawdev *dev;
1922         unsigned int i;
1923
1924         for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
1925                 dev = &ifpga_rawdevices[i];
1926                 if (dev->rawdev) {
1927                         rte_rawdev_pmd_release(dev->rawdev);
1928                         dev->rawdev = NULL;
1929                 }
1930         }
1931 }