drivers/raw/ifpga/ifpga_rawdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2018 Intel Corporation
   3  */
   4
   5 #include <string.h>
   6 #include <dirent.h>
   7 #include <sys/stat.h>
   8 #include <unistd.h>
   9 #include <sys/types.h>
  10 #include <fcntl.h>
  11 #include <sys/ioctl.h>
  12 #include <sys/epoll.h>
  13 #include <rte_log.h>
  14 #include <rte_bus.h>
  15 #include <rte_malloc.h>
  16 #include <rte_devargs.h>
  17 #include <rte_memcpy.h>
  18 #include <rte_pci.h>
  19 #include <rte_bus_pci.h>
  20 #include <rte_kvargs.h>
  21 #include <rte_alarm.h>
  22 #include <rte_interrupts.h>
  23 #include <rte_errno.h>
  24 #include <rte_per_lcore.h>
  25 #include <rte_memory.h>
  26 #include <rte_memzone.h>
  27 #include <rte_eal.h>
  28 #include <rte_common.h>
  29 #include <rte_bus_vdev.h>
  30 #include <rte_string_fns.h>
  31 #include <rte_pmd_i40e.h>
  32
  33 #include "base/opae_hw_api.h"
  34 #include "base/opae_ifpga_hw_api.h"
  35 #include "base/ifpga_api.h"
  36 #include "rte_rawdev.h"
  37 #include "rte_rawdev_pmd.h"
  38 #include "rte_bus_ifpga.h"
  39 #include "ifpga_common.h"
  40 #include "ifpga_logs.h"
  41 #include "ifpga_rawdev.h"
  42 #include "ipn3ke_rawdev_api.h"
  43
  44 #define PCI_VENDOR_ID_INTEL          0x8086
  45 /* PCI Device ID */
  46 #define PCIE_DEVICE_ID_PF_INT_5_X    0xBCBD
  47 #define PCIE_DEVICE_ID_PF_INT_6_X    0xBCC0
  48 #define PCIE_DEVICE_ID_PF_DSC_1_X    0x09C4
  49 #define PCIE_DEVICE_ID_PAC_N3000     0x0B30
  50 /* VF Device */
  51 #define PCIE_DEVICE_ID_VF_INT_5_X    0xBCBF
  52 #define PCIE_DEVICE_ID_VF_INT_6_X    0xBCC1
  53 #define PCIE_DEVICE_ID_VF_DSC_1_X    0x09C5
  54 #define PCIE_DEVICE_ID_VF_PAC_N3000  0x0B31
  55 #define RTE_MAX_RAW_DEVICE           10
  56
  57 static const struct rte_pci_id pci_ifpga_map[] = {
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
  66         { .vendor_id = 0, /* sentinel */ },
  67 };
  68
  69 static struct ifpga_rawdev ifpga_rawdevices[IFPGA_RAWDEV_NUM];
  70
  71 static int ifpga_monitor_start;
  72 static pthread_t ifpga_monitor_start_thread;
  73
  74 static struct ifpga_rawdev *
  75 ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
  76 static int set_surprise_link_check_aer(
  77                 struct ifpga_rawdev *ifpga_rdev, int force_disable);
  78 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
  79                                               int start, uint32_t cap);
  80 static int ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap);
  81
  82 struct ifpga_rawdev *
  83 ifpga_rawdev_get(const struct rte_rawdev *rawdev)
  84 {
  85         struct ifpga_rawdev *dev;
  86         unsigned int i;
  87
  88         if (rawdev == NULL)
  89                 return NULL;
  90
  91         for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
  92                 dev = &ifpga_rawdevices[i];
  93                 if (dev->rawdev == rawdev)
  94                         return dev;
  95         }
  96
  97         return NULL;
  98 }
  99
 100 static inline uint8_t
 101 ifpga_rawdev_find_free_device_index(void)
 102 {
 103         uint16_t dev_id;
 104
 105         for (dev_id = 0; dev_id < IFPGA_RAWDEV_NUM; dev_id++) {
 106                 if (ifpga_rawdevices[dev_id].rawdev == NULL)
 107                         return dev_id;
 108         }
 109
 110         return IFPGA_RAWDEV_NUM;
 111 }
 112 static struct ifpga_rawdev *
 113 ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
 114 {
 115         struct ifpga_rawdev *dev;
 116         uint16_t dev_id;
 117         int i = 0;
 118
 119         dev = ifpga_rawdev_get(rawdev);
 120         if (dev != NULL) {
 121                 IFPGA_RAWDEV_PMD_ERR("Event device already allocated!");
 122                 return NULL;
 123         }
 124
 125         dev_id = ifpga_rawdev_find_free_device_index();
 126         if (dev_id == IFPGA_RAWDEV_NUM) {
 127                 IFPGA_RAWDEV_PMD_ERR("Reached maximum number of raw devices");
 128                 return NULL;
 129         }
 130
 131         dev = &ifpga_rawdevices[dev_id];
 132         dev->rawdev = rawdev;
 133         dev->dev_id = dev_id;
 134         for (i = 0; i < IFPGA_MAX_IRQ; i++)
 135                 dev->intr_handle[i] = NULL;
 136
 137         return dev;
 138 }
 139
 140 static int
 141 ifpga_pci_find_next_ext_capability(unsigned int fd, int start, uint32_t cap)
 142 {
 143         uint32_t header;
 144         int ttl;
 145         int pos = RTE_PCI_CFG_SPACE_SIZE;
 146         int ret;
 147
 148         /* minimum 8 bytes per capability */
 149         ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
 150
 151         if (start)
 152                 pos = start;
 153         ret = pread(fd, &header, sizeof(header), pos);
 154         if (ret == -1)
 155                 return -1;
 156
 157         /*
 158          * If we have no capabilities, this is indicated by cap ID,
 159          * cap version and next pointer all being 0.
 160          */
 161         if (header == 0)
 162                 return 0;
 163
 164         while (ttl-- > 0) {
 165                 if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
 166                         return pos;
 167
 168                 pos = RTE_PCI_EXT_CAP_NEXT(header);
 169                 if (pos < RTE_PCI_CFG_SPACE_SIZE)
 170                         break;
 171                 ret = pread(fd, &header, sizeof(header), pos);
 172                 if (ret == -1)
 173                         return -1;
 174         }
 175
 176         return 0;
 177 }
 178
 179 static int
 180 ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap)
 181 {
 182         return ifpga_pci_find_next_ext_capability(fd, 0, cap);
 183 }
 184
 185 static int ifpga_get_dev_vendor_id(const char *bdf,
 186         uint32_t *dev_id, uint32_t *vendor_id)
 187 {
 188         int fd;
 189         char path[1024];
 190         int ret;
 191         uint32_t header;
 192
 193         strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
 194         strlcat(path, bdf, sizeof(path));
 195         strlcat(path, "/config", sizeof(path));
 196         fd = open(path, O_RDWR);
 197         if (fd < 0)
 198                 return -1;
 199         ret = pread(fd, &header, sizeof(header), 0);
 200         if (ret == -1) {
 201                 close(fd);
 202                 return -1;
 203         }
 204         (*vendor_id) = header & 0xffff;
 205         (*dev_id) = (header >> 16) & 0xffff;
 206         close(fd);
 207
 208         return 0;
 209 }
 210 static int ifpga_rawdev_fill_info(struct ifpga_rawdev *ifpga_dev,
 211         const char *bdf)
 212 {
 213         char path[1024] = "/sys/bus/pci/devices/0000:";
 214         char link[1024], link1[1024];
 215         char dir[1024] = "/sys/devices/";
 216         char *c;
 217         int ret;
 218         char sub_brg_bdf[4][16] = {{0}};
 219         int point;
 220         DIR *dp = NULL;
 221         struct dirent *entry;
 222         int i, j;
 223
 224         unsigned int dom, bus, dev;
 225         int func;
 226         uint32_t dev_id, vendor_id;
 227
 228         strlcat(path, bdf, sizeof(path));
 229         memset(link, 0, sizeof(link));
 230         memset(link1, 0, sizeof(link1));
 231         ret = readlink(path, link, (sizeof(link)-1));
 232         if ((ret < 0) || ((unsigned int)ret > (sizeof(link)-1)))
 233                 return -1;
 234         link[ret] = 0;   /* terminate string with null character */
 235         strlcpy(link1, link, sizeof(link1));
 236         memset(ifpga_dev->parent_bdf, 0, 16);
 237         point = strlen(link);
 238         if (point < 39)
 239                 return -1;
 240         point -= 39;
 241         link[point] = 0;
 242         if (point < 12)
 243                 return -1;
 244         point -= 12;
 245         rte_memcpy(ifpga_dev->parent_bdf, &link[point], 12);
 246
 247         point = strlen(link1);
 248         if (point < 26)
 249                 return -1;
 250         point -= 26;
 251         link1[point] = 0;
 252         if (point < 12)
 253                 return -1;
 254         point -= 12;
 255         c = strchr(link1, 'p');
 256         if (!c)
 257                 return -1;
 258         strlcat(dir, c, sizeof(dir));
 259
 260         /* scan folder */
 261         dp = opendir(dir);
 262         if (dp == NULL)
 263                 return -1;
 264         i = 0;
 265         while ((entry = readdir(dp)) != NULL) {
 266                 if (i >= 4)
 267                         break;
 268                 if (entry->d_name[0] == '.')
 269                         continue;
 270                 if (strlen(entry->d_name) > 12)
 271                         continue;
 272                 if (sscanf(entry->d_name, "%x:%x:%x.%d",
 273                         &dom, &bus, &dev, &func) < 4)
 274                         continue;
 275                 else {
 276                         strlcpy(sub_brg_bdf[i],
 277                                 entry->d_name,
 278                                 sizeof(sub_brg_bdf[i]));
 279                         i++;
 280                 }
 281         }
 282         closedir(dp);
 283
 284         /* get fpga and fvl */
 285         j = 0;
 286         for (i = 0; i < 4; i++) {
 287                 strlcpy(link, dir, sizeof(link));
 288                 strlcat(link, "/", sizeof(link));
 289                 strlcat(link, sub_brg_bdf[i], sizeof(link));
 290                 dp = opendir(link);
 291                 if (dp == NULL)
 292                         return -1;
 293                 while ((entry = readdir(dp)) != NULL) {
 294                         if (j >= 8)
 295                                 break;
 296                         if (entry->d_name[0] == '.')
 297                                 continue;
 298
 299                         if (strlen(entry->d_name) > 12)
 300                                 continue;
 301                         if (sscanf(entry->d_name, "%x:%x:%x.%d",
 302                                 &dom, &bus, &dev, &func) < 4)
 303                                 continue;
 304                         else {
 305                                 if (ifpga_get_dev_vendor_id(entry->d_name,
 306                                         &dev_id, &vendor_id))
 307                                         continue;
 308                                 if (vendor_id == 0x8086 &&
 309                                         (dev_id == 0x0CF8 ||
 310                                         dev_id == 0x0D58 ||
 311                                         dev_id == 0x1580)) {
 312                                         strlcpy(ifpga_dev->fvl_bdf[j],
 313                                                 entry->d_name,
 314                                                 sizeof(ifpga_dev->fvl_bdf[j]));
 315                                         j++;
 316                                 }
 317                         }
 318                 }
 319                 closedir(dp);
 320         }
 321
 322         return 0;
 323 }
 324
 325 #define HIGH_FATAL(_sens, value)\
 326         (((_sens)->flags & OPAE_SENSOR_HIGH_FATAL_VALID) &&\
 327          (value > (_sens)->high_fatal))
 328
 329 #define HIGH_WARN(_sens, value)\
 330         (((_sens)->flags & OPAE_SENSOR_HIGH_WARN_VALID) &&\
 331          (value > (_sens)->high_warn))
 332
 333 #define LOW_FATAL(_sens, value)\
 334         (((_sens)->flags & OPAE_SENSOR_LOW_FATAL_VALID) &&\
 335          (value > (_sens)->low_fatal))
 336
 337 #define LOW_WARN(_sens, value)\
 338         (((_sens)->flags & OPAE_SENSOR_LOW_WARN_VALID) &&\
 339          (value > (_sens)->low_warn))
 340
 341 #define AUX_VOLTAGE_WARN 11400
 342
 343 static int
 344 ifpga_monitor_sensor(struct rte_rawdev *raw_dev,
 345                bool *gsd_start)
 346 {
 347         struct opae_adapter *adapter;
 348         struct opae_manager *mgr;
 349         struct opae_sensor_info *sensor;
 350         unsigned int value;
 351         int ret;
 352
 353         adapter = ifpga_rawdev_get_priv(raw_dev);
 354         if (!adapter)
 355                 return -ENODEV;
 356
 357         mgr = opae_adapter_get_mgr(adapter);
 358         if (!mgr)
 359                 return -ENODEV;
 360
 361         opae_mgr_for_each_sensor(mgr, sensor) {
 362                 if (!(sensor->flags & OPAE_SENSOR_VALID))
 363                         goto fail;
 364
 365                 ret = opae_mgr_get_sensor_value(mgr, sensor, &value);
 366                 if (ret)
 367                         goto fail;
 368
 369                 if (value == 0xdeadbeef) {
 370                         IFPGA_RAWDEV_PMD_ERR("dev_id %d sensor %s value %x\n",
 371                                         raw_dev->dev_id, sensor->name, value);
 372                         continue;
 373                 }
 374
 375                 /* monitor temperature sensors */
 376                 if (!strcmp(sensor->name, "Board Temperature") ||
 377                                 !strcmp(sensor->name, "FPGA Die Temperature")) {
 378                         IFPGA_RAWDEV_PMD_INFO("read sensor %s %d %d %d\n",
 379                                         sensor->name, value, sensor->high_warn,
 380                                         sensor->high_fatal);
 381
 382                         if (HIGH_WARN(sensor, value) ||
 383                                 LOW_WARN(sensor, value)) {
 384                                 IFPGA_RAWDEV_PMD_INFO("%s reach threshold %d\n",
 385                                         sensor->name, value);
 386                                 *gsd_start = true;
 387                                 break;
 388                         }
 389                 }
 390
 391                 /* monitor 12V AUX sensor */
 392                 if (!strcmp(sensor->name, "12V AUX Voltage")) {
 393                         if (value < AUX_VOLTAGE_WARN) {
 394                                 IFPGA_RAWDEV_PMD_INFO(
 395                                         "%s reach threshold %d mV\n",
 396                                         sensor->name, value);
 397                                 *gsd_start = true;
 398                                 break;
 399                         }
 400                 }
 401         }
 402
 403         return 0;
 404 fail:
 405         return -EFAULT;
 406 }
 407
 408 static int set_surprise_link_check_aer(
 409         struct ifpga_rawdev *ifpga_rdev, int force_disable)
 410 {
 411         struct rte_rawdev *rdev;
 412         int fd = -1;
 413         char path[1024];
 414         int pos;
 415         int ret;
 416         uint32_t data;
 417         bool enable = 0;
 418         uint32_t aer_new0, aer_new1;
 419
 420         if (!ifpga_rdev) {
 421                 printf("\n device does not exist\n");
 422                 return -EFAULT;
 423         }
 424
 425         rdev = ifpga_rdev->rawdev;
 426         if (ifpga_rdev->aer_enable)
 427                 return -EFAULT;
 428         if (ifpga_monitor_sensor(rdev, &enable))
 429                 return -EFAULT;
 430         if (enable || force_disable) {
 431                 IFPGA_RAWDEV_PMD_ERR("Set AER, pls graceful shutdown\n");
 432                 ifpga_rdev->aer_enable = 1;
 433                 /* get bridge fd */
 434                 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
 435                 strlcat(path, ifpga_rdev->parent_bdf, sizeof(path));
 436                 strlcat(path, "/config", sizeof(path));
 437                 fd = open(path, O_RDWR);
 438                 if (fd < 0)
 439                         goto end;
 440                 pos = ifpga_pci_find_ext_capability(fd, RTE_PCI_EXT_CAP_ID_ERR);
 441                 if (!pos)
 442                         goto end;
 443                 /* save previous ECAP_AER+0x08 */
 444                 ret = pread(fd, &data, sizeof(data), pos+0x08);
 445                 if (ret == -1)
 446                         goto end;
 447                 ifpga_rdev->aer_old[0] = data;
 448                 /* save previous ECAP_AER+0x14 */
 449                 ret = pread(fd, &data, sizeof(data), pos+0x14);
 450                 if (ret == -1)
 451                         goto end;
 452                 ifpga_rdev->aer_old[1] = data;
 453
 454                 /* set ECAP_AER+0x08 to 0xFFFFFFFF */
 455                 data = 0xffffffff;
 456                 ret = pwrite(fd, &data, 4, pos+0x08);
 457                 if (ret == -1)
 458                         goto end;
 459                 /* set ECAP_AER+0x14 to 0xFFFFFFFF */
 460                 ret = pwrite(fd, &data, 4, pos+0x14);
 461                 if (ret == -1)
 462                         goto end;
 463
 464                 /* read current ECAP_AER+0x08 */
 465                 ret = pread(fd, &data, sizeof(data), pos+0x08);
 466                 if (ret == -1)
 467                         goto end;
 468                 aer_new0 = data;
 469                 /* read current ECAP_AER+0x14 */
 470                 ret = pread(fd, &data, sizeof(data), pos+0x14);
 471                 if (ret == -1)
 472                         goto end;
 473                 aer_new1 = data;
 474
 475                 if (fd != -1)
 476                         close(fd);
 477
 478                 printf(">>>>>>Set AER %x,%x %x,%x\n",
 479                         ifpga_rdev->aer_old[0], ifpga_rdev->aer_old[1],
 480                         aer_new0, aer_new1);
 481
 482                 return 1;
 483                 }
 484
 485 end:
 486         if (fd != -1)
 487                 close(fd);
 488         return -EFAULT;
 489 }
 490
 491 static void *
 492 ifpga_rawdev_gsd_handle(__rte_unused void *param)
 493 {
 494         struct ifpga_rawdev *ifpga_rdev;
 495         int i;
 496         int gsd_enable, ret;
 497 #define MS 1000
 498
 499         while (__atomic_load_n(&ifpga_monitor_start, __ATOMIC_RELAXED)) {
 500                 gsd_enable = 0;
 501                 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
 502                         ifpga_rdev = &ifpga_rawdevices[i];
 503                         if (ifpga_rdev->rawdev) {
 504                                 ret = set_surprise_link_check_aer(ifpga_rdev,
 505                                         gsd_enable);
 506                                 if (ret == 1 && !gsd_enable) {
 507                                         gsd_enable = 1;
 508                                         i = -1;
 509                                 }
 510                         }
 511                 }
 512
 513                 if (gsd_enable)
 514                         printf(">>>>>>Pls Shutdown APP\n");
 515
 516                 rte_delay_us(100 * MS);
 517         }
 518
 519         return NULL;
 520 }
 521
 522 static int
 523 ifpga_monitor_start_func(void)
 524 {
 525         int ret;
 526
 527         if (!__atomic_load_n(&ifpga_monitor_start, __ATOMIC_RELAXED)) {
 528                 ret = rte_ctrl_thread_create(&ifpga_monitor_start_thread,
 529                                              "ifpga-monitor", NULL,
 530                                              ifpga_rawdev_gsd_handle, NULL);
 531                 if (ret != 0) {
 532                         IFPGA_RAWDEV_PMD_ERR(
 533                                 "Fail to create ifpga monitor thread");
 534                         return -1;
 535                 }
 536                 __atomic_store_n(&ifpga_monitor_start, 1, __ATOMIC_RELAXED);
 537         }
 538
 539         return 0;
 540 }
 541 static int
 542 ifpga_monitor_stop_func(void)
 543 {
 544         int ret;
 545
 546         if (__atomic_load_n(&ifpga_monitor_start, __ATOMIC_RELAXED)) {
 547                 __atomic_store_n(&ifpga_monitor_start, 0, __ATOMIC_RELAXED);
 548
 549                 ret = pthread_cancel(ifpga_monitor_start_thread);
 550                 if (ret)
 551                         IFPGA_RAWDEV_PMD_ERR("Can't cancel the thread");
 552
 553                 ret = pthread_join(ifpga_monitor_start_thread, NULL);
 554                 if (ret)
 555                         IFPGA_RAWDEV_PMD_ERR("Can't join the thread");
 556
 557                 return ret;
 558         }
 559
 560         return 0;
 561 }
 562
 563 static int
 564 ifpga_fill_afu_dev(struct opae_accelerator *acc,
 565                 struct rte_afu_device *afu_dev)
 566 {
 567         struct rte_mem_resource *res = afu_dev->mem_resource;
 568         struct opae_acc_region_info region_info;
 569         struct opae_acc_info info;
 570         unsigned long i;
 571         int ret;
 572
 573         ret = opae_acc_get_info(acc, &info);
 574         if (ret)
 575                 return ret;
 576
 577         if (info.num_regions > PCI_MAX_RESOURCE)
 578                 return -EFAULT;
 579
 580         afu_dev->num_region = info.num_regions;
 581
 582         for (i = 0; i < info.num_regions; i++) {
 583                 region_info.index = i;
 584                 ret = opae_acc_get_region_info(acc, &region_info);
 585                 if (ret)
 586                         return ret;
 587
 588                 if ((region_info.flags & ACC_REGION_MMIO) &&
 589                     (region_info.flags & ACC_REGION_READ) &&
 590                     (region_info.flags & ACC_REGION_WRITE)) {
 591                         res[i].phys_addr = region_info.phys_addr;
 592                         res[i].len = region_info.len;
 593                         res[i].addr = region_info.addr;
 594                 } else
 595                         return -EFAULT;
 596         }
 597
 598         return 0;
 599 }
 600
 601 static int
 602 ifpga_rawdev_info_get(struct rte_rawdev *dev,
 603                       rte_rawdev_obj_t dev_info,
 604                       size_t dev_info_size)
 605 {
 606         struct opae_adapter *adapter;
 607         struct opae_accelerator *acc;
 608         struct rte_afu_device *afu_dev;
 609         struct opae_manager *mgr = NULL;
 610         struct opae_eth_group_region_info opae_lside_eth_info;
 611         struct opae_eth_group_region_info opae_nside_eth_info;
 612         int lside_bar_idx, nside_bar_idx;
 613
 614         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 615
 616         if (!dev_info || dev_info_size != sizeof(*afu_dev)) {
 617                 IFPGA_RAWDEV_PMD_ERR("Invalid request");
 618                 return -EINVAL;
 619         }
 620
 621         adapter = ifpga_rawdev_get_priv(dev);
 622         if (!adapter)
 623                 return -ENOENT;
 624
 625         afu_dev = dev_info;
 626         afu_dev->rawdev = dev;
 627
 628         /* find opae_accelerator and fill info into afu_device */
 629         opae_adapter_for_each_acc(adapter, acc) {
 630                 if (acc->index != afu_dev->id.port)
 631                         continue;
 632
 633                 if (ifpga_fill_afu_dev(acc, afu_dev)) {
 634                         IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
 635                         return -ENOENT;
 636                 }
 637         }
 638
 639         /* get opae_manager to rawdev */
 640         mgr = opae_adapter_get_mgr(adapter);
 641         if (mgr) {
 642                 /* get LineSide BAR Index */
 643                 if (opae_manager_get_eth_group_region_info(mgr, 0,
 644                         &opae_lside_eth_info)) {
 645                         return -ENOENT;
 646                 }
 647                 lside_bar_idx = opae_lside_eth_info.mem_idx;
 648
 649                 /* get NICSide BAR Index */
 650                 if (opae_manager_get_eth_group_region_info(mgr, 1,
 651                         &opae_nside_eth_info)) {
 652                         return -ENOENT;
 653                 }
 654                 nside_bar_idx = opae_nside_eth_info.mem_idx;
 655
 656                 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
 657                         nside_bar_idx >= PCI_MAX_RESOURCE ||
 658                         lside_bar_idx == nside_bar_idx)
 659                         return -ENOENT;
 660
 661                 /* fill LineSide BAR Index */
 662                 afu_dev->mem_resource[lside_bar_idx].phys_addr =
 663                         opae_lside_eth_info.phys_addr;
 664                 afu_dev->mem_resource[lside_bar_idx].len =
 665                         opae_lside_eth_info.len;
 666                 afu_dev->mem_resource[lside_bar_idx].addr =
 667                         opae_lside_eth_info.addr;
 668
 669                 /* fill NICSide BAR Index */
 670                 afu_dev->mem_resource[nside_bar_idx].phys_addr =
 671                         opae_nside_eth_info.phys_addr;
 672                 afu_dev->mem_resource[nside_bar_idx].len =
 673                         opae_nside_eth_info.len;
 674                 afu_dev->mem_resource[nside_bar_idx].addr =
 675                         opae_nside_eth_info.addr;
 676         }
 677         return 0;
 678 }
 679
 680 static int
 681 ifpga_rawdev_configure(const struct rte_rawdev *dev,
 682                 rte_rawdev_obj_t config,
 683                 size_t config_size __rte_unused)
 684 {
 685         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 686
 687         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 688
 689         return config ? 0 : 1;
 690 }
 691
 692 static int
 693 ifpga_rawdev_start(struct rte_rawdev *dev)
 694 {
 695         int ret = 0;
 696         struct opae_adapter *adapter;
 697
 698         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 699
 700         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 701
 702         adapter = ifpga_rawdev_get_priv(dev);
 703         if (!adapter)
 704                 return -ENODEV;
 705
 706         return ret;
 707 }
 708
 709 static void
 710 ifpga_rawdev_stop(struct rte_rawdev *dev)
 711 {
 712         dev->started = 0;
 713 }
 714
 715 static int
 716 ifpga_rawdev_close(struct rte_rawdev *dev)
 717 {
 718         struct opae_adapter *adapter;
 719
 720         if (dev) {
 721                 adapter = ifpga_rawdev_get_priv(dev);
 722                 if (adapter) {
 723                         opae_adapter_destroy(adapter);
 724                         opae_adapter_data_free(adapter->data);
 725                 }
 726         }
 727
 728         return dev ? 0:1;
 729 }
 730
 731 static int
 732 ifpga_rawdev_reset(struct rte_rawdev *dev)
 733 {
 734         return dev ? 0:1;
 735 }
 736
 737 static int
 738 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size,
 739                         u64 *status)
 740 {
 741
 742         struct opae_adapter *adapter;
 743         struct opae_manager *mgr;
 744         struct opae_accelerator *acc;
 745         struct opae_bridge *br;
 746         int ret;
 747
 748         adapter = ifpga_rawdev_get_priv(raw_dev);
 749         if (!adapter)
 750                 return -ENODEV;
 751
 752         mgr = opae_adapter_get_mgr(adapter);
 753         if (!mgr)
 754                 return -ENODEV;
 755
 756         acc = opae_adapter_get_acc(adapter, port_id);
 757         if (!acc)
 758                 return -ENODEV;
 759
 760         br = opae_acc_get_br(acc);
 761         if (!br)
 762                 return -ENODEV;
 763
 764         ret = opae_manager_flash(mgr, port_id, buffer, size, status);
 765         if (ret) {
 766                 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
 767                 return ret;
 768         }
 769
 770         ret = opae_bridge_reset(br);
 771         if (ret) {
 772                 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
 773                                 __func__, port_id, ret);
 774                 return ret;
 775         }
 776
 777         return ret;
 778 }
 779
 780 static int
 781 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
 782                 const char *file_name)
 783 {
 784         struct stat file_stat;
 785         int file_fd;
 786         int ret = 0;
 787         ssize_t buffer_size;
 788         void *buffer, *buf_to_free;
 789         u64 pr_error;
 790
 791         if (!file_name)
 792                 return -EINVAL;
 793
 794         file_fd = open(file_name, O_RDONLY);
 795         if (file_fd < 0) {
 796                 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
 797                                 __func__, file_name);
 798                 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
 799                 return -EINVAL;
 800         }
 801         ret = stat(file_name, &file_stat);
 802         if (ret) {
 803                 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
 804                                 file_name);
 805                 ret = -EINVAL;
 806                 goto close_fd;
 807         }
 808         buffer_size = file_stat.st_size;
 809         if (buffer_size <= 0) {
 810                 ret = -EINVAL;
 811                 goto close_fd;
 812         }
 813
 814         IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
 815         buffer = rte_malloc(NULL, buffer_size, 0);
 816         if (!buffer) {
 817                 ret = -ENOMEM;
 818                 goto close_fd;
 819         }
 820         buf_to_free = buffer;
 821
 822         /*read the raw data*/
 823         if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
 824                 ret = -EINVAL;
 825                 goto free_buffer;
 826         }
 827
 828         /*do PR now*/
 829         ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
 830         IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
 831                 ret ? "failed" : "success");
 832         if (ret) {
 833                 ret = -EINVAL;
 834                 goto free_buffer;
 835         }
 836
 837 free_buffer:
 838         rte_free(buf_to_free);
 839 close_fd:
 840         close(file_fd);
 841         file_fd = 0;
 842         return ret;
 843 }
 844
 845 static int
 846 ifpga_rawdev_pr(struct rte_rawdev *dev,
 847         rte_rawdev_obj_t pr_conf)
 848 {
 849         struct opae_adapter *adapter;
 850         struct opae_manager *mgr;
 851         struct opae_board_info *info;
 852         struct rte_afu_pr_conf *afu_pr_conf;
 853         int ret;
 854         struct uuid uuid;
 855         struct opae_accelerator *acc;
 856
 857         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 858
 859         adapter = ifpga_rawdev_get_priv(dev);
 860         if (!adapter)
 861                 return -ENODEV;
 862
 863         if (!pr_conf)
 864                 return -EINVAL;
 865
 866         afu_pr_conf = pr_conf;
 867
 868         if (afu_pr_conf->pr_enable) {
 869                 ret = rte_fpga_do_pr(dev,
 870                                 afu_pr_conf->afu_id.port,
 871                                 afu_pr_conf->bs_path);
 872                 if (ret) {
 873                         IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
 874                         return ret;
 875                 }
 876         }
 877
 878         mgr = opae_adapter_get_mgr(adapter);
 879         if (!mgr) {
 880                 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
 881                 return -1;
 882         }
 883
 884         if (ifpga_mgr_ops.get_board_info(mgr, &info)) {
 885                 IFPGA_RAWDEV_PMD_ERR("ifpga manager get_board_info fail!");
 886                 return -1;
 887         }
 888
 889         if (info->lightweight) {
 890                 /* set uuid to all 0, when fpga is lightweight image */
 891                 memset(&afu_pr_conf->afu_id.uuid.uuid_low, 0, sizeof(u64));
 892                 memset(&afu_pr_conf->afu_id.uuid.uuid_high, 0, sizeof(u64));
 893         } else {
 894                 acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
 895                 if (!acc)
 896                         return -ENODEV;
 897
 898                 ret = opae_acc_get_uuid(acc, &uuid);
 899                 if (ret)
 900                         return ret;
 901
 902                 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b,
 903                         sizeof(u64));
 904                 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high, uuid.b + 8,
 905                         sizeof(u64));
 906
 907                 IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n",
 908                         __func__,
 909                         (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
 910                         (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
 911                 }
 912         return 0;
 913 }
 914
 915 static int
 916 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
 917         const char *attr_name, uint64_t *attr_value)
 918 {
 919         struct opae_adapter *adapter;
 920         struct opae_manager *mgr;
 921         struct opae_retimer_info opae_rtm_info;
 922         struct opae_retimer_status opae_rtm_status;
 923         struct opae_eth_group_info opae_eth_grp_info;
 924         struct opae_eth_group_region_info opae_eth_grp_reg_info;
 925         int eth_group_num = 0;
 926         uint64_t port_link_bitmap = 0, port_link_bit;
 927         uint32_t i, j, p, q;
 928
 929 #define MAX_PORT_PER_RETIMER    4
 930
 931         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 932
 933         if (!dev || !attr_name || !attr_value) {
 934                 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
 935                 return -1;
 936         }
 937
 938         adapter = ifpga_rawdev_get_priv(dev);
 939         if (!adapter) {
 940                 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
 941                 return -1;
 942         }
 943
 944         mgr = opae_adapter_get_mgr(adapter);
 945         if (!mgr) {
 946                 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
 947                 return -1;
 948         }
 949
 950         /* currently, eth_group_num is always 2 */
 951         eth_group_num = opae_manager_get_eth_group_nums(mgr);
 952         if (eth_group_num < 0)
 953                 return -1;
 954
 955         if (!strcmp(attr_name, "LineSideBaseMAC")) {
 956                 /* Currently FPGA not implement, so just set all zeros*/
 957                 *attr_value = (uint64_t)0;
 958                 return 0;
 959         }
 960         if (!strcmp(attr_name, "LineSideMACType")) {
 961                 /* eth_group 0 on FPGA connect to LineSide */
 962                 if (opae_manager_get_eth_group_info(mgr, 0,
 963                         &opae_eth_grp_info))
 964                         return -1;
 965                 switch (opae_eth_grp_info.speed) {
 966                 case ETH_SPEED_10G:
 967                         *attr_value =
 968                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
 969                         break;
 970                 case ETH_SPEED_25G:
 971                         *attr_value =
 972                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
 973                         break;
 974                 default:
 975                         *attr_value =
 976                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
 977                         break;
 978                 }
 979                 return 0;
 980         }
 981         if (!strcmp(attr_name, "LineSideLinkSpeed")) {
 982                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
 983                         return -1;
 984                 switch (opae_rtm_status.speed) {
 985                 case MXD_1GB:
 986                         *attr_value =
 987                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 988                         break;
 989                 case MXD_2_5GB:
 990                         *attr_value =
 991                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 992                         break;
 993                 case MXD_5GB:
 994                         *attr_value =
 995                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 996                         break;
 997                 case MXD_10GB:
 998                         *attr_value =
 999                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
1000                         break;
1001                 case MXD_25GB:
1002                         *attr_value =
1003                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
1004                         break;
1005                 case MXD_40GB:
1006                         *attr_value =
1007                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
1008                         break;
1009                 case MXD_100GB:
1010                         *attr_value =
1011                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1012                         break;
1013                 case MXD_SPEED_UNKNOWN:
1014                         *attr_value =
1015                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1016                         break;
1017                 default:
1018                         *attr_value =
1019                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1020                         break;
1021                 }
1022                 return 0;
1023         }
1024         if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
1025                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1026                         return -1;
1027                 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
1028                 return 0;
1029         }
1030         if (!strcmp(attr_name, "LineSideLinkPortNum")) {
1031                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1032                         return -1;
1033                 uint64_t tmp = (uint64_t)opae_rtm_info.ports_per_retimer *
1034                                         (uint64_t)opae_rtm_info.nums_retimer;
1035                 *attr_value = tmp;
1036                 return 0;
1037         }
1038         if (!strcmp(attr_name, "LineSideLinkStatus")) {
1039                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1040                         return -1;
1041                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1042                         return -1;
1043                 (*attr_value) = 0;
1044                 q = 0;
1045                 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
1046                 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
1047                         p = i * MAX_PORT_PER_RETIMER;
1048                         for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
1049                                 port_link_bit = 0;
1050                                 IFPGA_BIT_SET(port_link_bit, (p+j));
1051                                 port_link_bit &= port_link_bitmap;
1052                                 if (port_link_bit)
1053                                         IFPGA_BIT_SET((*attr_value), q);
1054                                 q++;
1055                         }
1056                 }
1057                 return 0;
1058         }
1059         if (!strcmp(attr_name, "LineSideBARIndex")) {
1060                 /* eth_group 0 on FPGA connect to LineSide */
1061                 if (opae_manager_get_eth_group_region_info(mgr, 0,
1062                         &opae_eth_grp_reg_info))
1063                         return -1;
1064                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1065                 return 0;
1066         }
1067         if (!strcmp(attr_name, "NICSideMACType")) {
1068                 /* eth_group 1 on FPGA connect to NicSide */
1069                 if (opae_manager_get_eth_group_info(mgr, 1,
1070                         &opae_eth_grp_info))
1071                         return -1;
1072                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1073                 return 0;
1074         }
1075         if (!strcmp(attr_name, "NICSideLinkSpeed")) {
1076                 /* eth_group 1 on FPGA connect to NicSide */
1077                 if (opae_manager_get_eth_group_info(mgr, 1,
1078                         &opae_eth_grp_info))
1079                         return -1;
1080                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1081                 return 0;
1082         }
1083         if (!strcmp(attr_name, "NICSideLinkPortNum")) {
1084                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1085                         return -1;
1086                 uint64_t tmp = (uint64_t)opae_rtm_info.nums_fvl *
1087                                         (uint64_t)opae_rtm_info.ports_per_fvl;
1088                 *attr_value = tmp;
1089                 return 0;
1090         }
1091         if (!strcmp(attr_name, "NICSideLinkStatus"))
1092                 return 0;
1093         if (!strcmp(attr_name, "NICSideBARIndex")) {
1094                 /* eth_group 1 on FPGA connect to NicSide */
1095                 if (opae_manager_get_eth_group_region_info(mgr, 1,
1096                         &opae_eth_grp_reg_info))
1097                         return -1;
1098                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1099                 return 0;
1100         }
1101
1102         IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
1103         return -1;
1104 }
1105
1106 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
1107         .dev_info_get = ifpga_rawdev_info_get,
1108         .dev_configure = ifpga_rawdev_configure,
1109         .dev_start = ifpga_rawdev_start,
1110         .dev_stop = ifpga_rawdev_stop,
1111         .dev_close = ifpga_rawdev_close,
1112         .dev_reset = ifpga_rawdev_reset,
1113
1114         .queue_def_conf = NULL,
1115         .queue_setup = NULL,
1116         .queue_release = NULL,
1117
1118         .attr_get = ifpga_rawdev_get_attr,
1119         .attr_set = NULL,
1120
1121         .enqueue_bufs = NULL,
1122         .dequeue_bufs = NULL,
1123
1124         .dump = NULL,
1125
1126         .xstats_get = NULL,
1127         .xstats_get_names = NULL,
1128         .xstats_get_by_name = NULL,
1129         .xstats_reset = NULL,
1130
1131         .firmware_status_get = NULL,
1132         .firmware_version_get = NULL,
1133         .firmware_load = ifpga_rawdev_pr,
1134         .firmware_unload = NULL,
1135
1136         .dev_selftest = NULL,
1137 };
1138
1139 static int
1140 ifpga_get_fme_error_prop(struct opae_manager *mgr,
1141                 u64 prop_id, u64 *val)
1142 {
1143         struct feature_prop prop;
1144
1145         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1146         prop.prop_id = prop_id;
1147
1148         if (opae_manager_ifpga_get_prop(mgr, &prop))
1149                 return -EINVAL;
1150
1151         *val = prop.data;
1152
1153         return 0;
1154 }
1155
1156 static int
1157 ifpga_set_fme_error_prop(struct opae_manager *mgr,
1158                 u64 prop_id, u64 val)
1159 {
1160         struct feature_prop prop;
1161
1162         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1163         prop.prop_id = prop_id;
1164
1165         prop.data = val;
1166
1167         if (opae_manager_ifpga_set_prop(mgr, &prop))
1168                 return -EINVAL;
1169
1170         return 0;
1171 }
1172
1173 static int
1174 fme_err_read_seu_emr(struct opae_manager *mgr)
1175 {
1176         u64 val;
1177         int ret;
1178
1179         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
1180         if (ret)
1181                 return -EINVAL;
1182
1183         IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%" PRIx64 "\n", val);
1184
1185         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
1186         if (ret)
1187                 return -EINVAL;
1188
1189         IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%" PRIx64 "\n", val);
1190
1191         return 0;
1192 }
1193
1194 static int fme_clear_warning_intr(struct opae_manager *mgr)
1195 {
1196         u64 val;
1197
1198         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
1199                 return -EINVAL;
1200
1201         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1202                 return -EINVAL;
1203         if ((val & 0x40) != 0)
1204                 IFPGA_RAWDEV_PMD_INFO("clean not done\n");
1205
1206         return 0;
1207 }
1208
1209 static int fme_clean_fme_error(struct opae_manager *mgr)
1210 {
1211         u64 val;
1212
1213         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1214                 return -EINVAL;
1215
1216         IFPGA_RAWDEV_PMD_DEBUG("before clean 0x%" PRIx64 "\n", val);
1217
1218         ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_CLEAR, val);
1219
1220         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1221                 return -EINVAL;
1222
1223         IFPGA_RAWDEV_PMD_DEBUG("after clean 0x%" PRIx64 "\n", val);
1224
1225         return 0;
1226 }
1227
1228 static int
1229 fme_err_handle_error0(struct opae_manager *mgr)
1230 {
1231         struct feature_fme_error0 fme_error0;
1232         u64 val;
1233
1234         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1235                 return -EINVAL;
1236
1237         if (fme_clean_fme_error(mgr))
1238                 return -EINVAL;
1239
1240         fme_error0.csr = val;
1241
1242         if (fme_error0.fabric_err)
1243                 IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
1244         else if (fme_error0.fabfifo_overflow)
1245                 IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
1246         else if (fme_error0.afu_acc_mode_err)
1247                 IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
1248         else if (fme_error0.pcie0cdc_parity_err)
1249                 IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
1250         else if (fme_error0.cvlcdc_parity_err)
1251                 IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
1252         else if (fme_error0.fpgaseuerr)
1253                 fme_err_read_seu_emr(mgr);
1254
1255         /* clean the errors */
1256         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
1257                 return -EINVAL;
1258
1259         return 0;
1260 }
1261
1262 static int
1263 fme_err_handle_catfatal_error(struct opae_manager *mgr)
1264 {
1265         struct feature_fme_ras_catfaterror fme_catfatal;
1266         u64 val;
1267
1268         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
1269                 return -EINVAL;
1270
1271         fme_catfatal.csr = val;
1272
1273         if (fme_catfatal.cci_fatal_err)
1274                 IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
1275         else if (fme_catfatal.fabric_fatal_err)
1276                 IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
1277         else if (fme_catfatal.pcie_poison_err)
1278                 IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
1279         else if (fme_catfatal.inject_fata_err)
1280                 IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
1281         else if (fme_catfatal.crc_catast_err)
1282                 IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
1283         else if (fme_catfatal.injected_catast_err)
1284                 IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
1285         else if (fme_catfatal.bmc_seu_catast_err)
1286                 fme_err_read_seu_emr(mgr);
1287
1288         return 0;
1289 }
1290
1291 static int
1292 fme_err_handle_nonfaterror(struct opae_manager *mgr)
1293 {
1294         struct feature_fme_ras_nonfaterror nonfaterr;
1295         u64 val;
1296
1297         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1298                 return -EINVAL;
1299
1300         nonfaterr.csr = val;
1301
1302         if (nonfaterr.temp_thresh_ap1)
1303                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP1\n");
1304         else if (nonfaterr.temp_thresh_ap2)
1305                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP2\n");
1306         else if (nonfaterr.pcie_error)
1307                 IFPGA_RAWDEV_PMD_INFO("an error has occurred in pcie\n");
1308         else if (nonfaterr.portfatal_error)
1309                 IFPGA_RAWDEV_PMD_INFO("fatal error occurred in AFU port.\n");
1310         else if (nonfaterr.proc_hot)
1311                 IFPGA_RAWDEV_PMD_INFO("a ProcHot event\n");
1312         else if (nonfaterr.afu_acc_mode_err)
1313                 IFPGA_RAWDEV_PMD_INFO("an AFU PF/VF access mismatch\n");
1314         else if (nonfaterr.injected_nonfata_err) {
1315                 IFPGA_RAWDEV_PMD_INFO("Injected Warning Error\n");
1316                 fme_clear_warning_intr(mgr);
1317         } else if (nonfaterr.temp_thresh_AP6)
1318                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP6\n");
1319         else if (nonfaterr.power_thresh_AP1)
1320                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP1\n");
1321         else if (nonfaterr.power_thresh_AP2)
1322                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP2\n");
1323         else if (nonfaterr.mbp_err)
1324                 IFPGA_RAWDEV_PMD_INFO("an MBP event\n");
1325
1326         return 0;
1327 }
1328
1329 static void
1330 fme_interrupt_handler(void *param)
1331 {
1332         struct opae_manager *mgr = (struct opae_manager *)param;
1333
1334         IFPGA_RAWDEV_PMD_INFO("%s interrupt occurred\n", __func__);
1335
1336         fme_err_handle_error0(mgr);
1337         fme_err_handle_nonfaterror(mgr);
1338         fme_err_handle_catfatal_error(mgr);
1339 }
1340
1341 int
1342 ifpga_unregister_msix_irq(struct ifpga_rawdev *dev, enum ifpga_irq_type type,
1343                 int vec_start, rte_intr_callback_fn handler, void *arg)
1344 {
1345         struct rte_intr_handle **intr_handle;
1346         int rc = 0;
1347         int i = vec_start + 1;
1348
1349         if (!dev)
1350                 return -ENODEV;
1351
1352         if (type == IFPGA_FME_IRQ)
1353                 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[0];
1354         else if (type == IFPGA_AFU_IRQ)
1355                 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[i];
1356         else
1357                 return -EINVAL;
1358
1359         if ((*intr_handle) == NULL) {
1360                 IFPGA_RAWDEV_PMD_ERR("%s interrupt %d not registered\n",
1361                         type == IFPGA_FME_IRQ ? "FME" : "AFU",
1362                         type == IFPGA_FME_IRQ ? 0 : vec_start);
1363                 return -ENOENT;
1364         }
1365
1366         rte_intr_efd_disable(*intr_handle);
1367
1368         rc = rte_intr_callback_unregister(*intr_handle, handler, arg);
1369         if (rc < 0) {
1370                 IFPGA_RAWDEV_PMD_ERR("Failed to unregister %s interrupt %d\n",
1371                         type == IFPGA_FME_IRQ ? "FME" : "AFU",
1372                         type == IFPGA_FME_IRQ ? 0 : vec_start);
1373         } else {
1374                 rte_intr_instance_free(*intr_handle);
1375                 *intr_handle = NULL;
1376         }
1377
1378         return rc;
1379 }
1380
1381 int
1382 ifpga_register_msix_irq(struct ifpga_rawdev *dev, int port_id,
1383                 enum ifpga_irq_type type, int vec_start, int count,
1384                 rte_intr_callback_fn handler, const char *name,
1385                 void *arg)
1386 {
1387         int ret;
1388         struct rte_intr_handle **intr_handle;
1389         struct opae_adapter *adapter;
1390         struct opae_manager *mgr;
1391         struct opae_accelerator *acc;
1392         int *intr_efds = NULL, nb_intr, i;
1393
1394         if (!dev || !dev->rawdev)
1395                 return -ENODEV;
1396
1397         adapter = ifpga_rawdev_get_priv(dev->rawdev);
1398         if (!adapter)
1399                 return -ENODEV;
1400
1401         mgr = opae_adapter_get_mgr(adapter);
1402         if (!mgr)
1403                 return -ENODEV;
1404
1405         if (type == IFPGA_FME_IRQ) {
1406                 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[0];
1407                 count = 1;
1408         } else if (type == IFPGA_AFU_IRQ) {
1409                 i = vec_start + 1;
1410                 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[i];
1411         } else {
1412                 return -EINVAL;
1413         }
1414
1415         if (*intr_handle)
1416                 return -EBUSY;
1417
1418         *intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
1419         if (!(*intr_handle))
1420                 return -ENOMEM;
1421
1422         if (rte_intr_type_set(*intr_handle, RTE_INTR_HANDLE_VFIO_MSIX))
1423                 return -rte_errno;
1424
1425         ret = rte_intr_efd_enable(*intr_handle, count);
1426         if (ret)
1427                 return -ENODEV;
1428
1429         if (rte_intr_fd_set(*intr_handle,
1430                         rte_intr_efds_index_get(*intr_handle, 0)))
1431                 return -rte_errno;
1432
1433         IFPGA_RAWDEV_PMD_DEBUG("register %s irq, vfio_fd=%d, fd=%d\n",
1434                         name, rte_intr_dev_fd_get(*intr_handle),
1435                         rte_intr_fd_get(*intr_handle));
1436
1437         if (type == IFPGA_FME_IRQ) {
1438                 struct fpga_fme_err_irq_set err_irq_set;
1439                 err_irq_set.evtfd = rte_intr_efds_index_get(*intr_handle,
1440                                                                    0);
1441
1442                 ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
1443                 if (ret)
1444                         return -EINVAL;
1445         } else if (type == IFPGA_AFU_IRQ) {
1446                 acc = opae_adapter_get_acc(adapter, port_id);
1447                 if (!acc)
1448                         return -EINVAL;
1449
1450                 nb_intr = rte_intr_nb_intr_get(*intr_handle);
1451
1452                 intr_efds = calloc(nb_intr, sizeof(int));
1453                 if (!intr_efds)
1454                         return -ENOMEM;
1455
1456                 for (i = 0; i < nb_intr; i++)
1457                         intr_efds[i] = rte_intr_efds_index_get(*intr_handle, i);
1458
1459                 ret = opae_acc_set_irq(acc, vec_start, count, intr_efds);
1460                 if (ret) {
1461                         free(intr_efds);
1462                         return -EINVAL;
1463                 }
1464         }
1465
1466         /* register interrupt handler using DPDK API */
1467         ret = rte_intr_callback_register(*intr_handle,
1468                         handler, (void *)arg);
1469         if (ret) {
1470                 free(intr_efds);
1471                 return -EINVAL;
1472         }
1473
1474         IFPGA_RAWDEV_PMD_INFO("success register %s interrupt\n", name);
1475
1476         free(intr_efds);
1477         return 0;
1478 }
1479
1480 static int
1481 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
1482                         int socket_id)
1483 {
1484         int ret = 0;
1485         struct rte_rawdev *rawdev = NULL;
1486         struct ifpga_rawdev *dev = NULL;
1487         struct opae_adapter *adapter = NULL;
1488         struct opae_manager *mgr = NULL;
1489         struct opae_adapter_data_pci *data = NULL;
1490         char name[RTE_RAWDEV_NAME_MAX_LEN];
1491         int i;
1492
1493         if (!pci_dev) {
1494                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1495                 ret = -EINVAL;
1496                 goto cleanup;
1497         }
1498
1499         memset(name, 0, sizeof(name));
1500         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, IFPGA_RAWDEV_NAME_FMT,
1501                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1502
1503         IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
1504
1505         /* Allocate device structure */
1506         rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
1507                                          socket_id);
1508         if (rawdev == NULL) {
1509                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
1510                 ret = -EINVAL;
1511                 goto cleanup;
1512         }
1513
1514         ipn3ke_bridge_func.get_ifpga_rawdev = ifpga_rawdev_get;
1515         ipn3ke_bridge_func.set_i40e_sw_dev = rte_pmd_i40e_set_switch_dev;
1516
1517         dev = ifpga_rawdev_allocate(rawdev);
1518         if (dev == NULL) {
1519                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate ifpga_rawdevice");
1520                 ret = -EINVAL;
1521                 goto cleanup;
1522         }
1523         dev->aer_enable = 0;
1524
1525         /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
1526         data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
1527         if (!data) {
1528                 ret = -ENOMEM;
1529                 goto cleanup;
1530         }
1531
1532         /* init opae_adapter_data_pci for device specific information */
1533         for (i = 0; i < PCI_MAX_RESOURCE; i++) {
1534                 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
1535                 data->region[i].len = pci_dev->mem_resource[i].len;
1536                 data->region[i].addr = pci_dev->mem_resource[i].addr;
1537         }
1538         data->device_id = pci_dev->id.device_id;
1539         data->vendor_id = pci_dev->id.vendor_id;
1540         data->bus = pci_dev->addr.bus;
1541         data->devid = pci_dev->addr.devid;
1542         data->function = pci_dev->addr.function;
1543         data->vfio_dev_fd = rte_intr_dev_fd_get(pci_dev->intr_handle);
1544
1545         adapter = rawdev->dev_private;
1546         /* create a opae_adapter based on above device data */
1547         ret = opae_adapter_init(adapter, pci_dev->device.name, data);
1548         if (ret) {
1549                 ret = -ENOMEM;
1550                 goto free_adapter_data;
1551         }
1552
1553         rawdev->dev_ops = &ifpga_rawdev_ops;
1554         rawdev->device = &pci_dev->device;
1555         rawdev->driver_name = pci_dev->driver->driver.name;
1556
1557         /* must enumerate the adapter before use it */
1558         ret = opae_adapter_enumerate(adapter);
1559         if (ret)
1560                 goto free_adapter_data;
1561
1562         /* get opae_manager to rawdev */
1563         mgr = opae_adapter_get_mgr(adapter);
1564         if (mgr) {
1565                 /* PF function */
1566                 IFPGA_RAWDEV_PMD_INFO("this is a PF function");
1567         }
1568
1569         ret = ifpga_register_msix_irq(dev, 0, IFPGA_FME_IRQ, 0, 0,
1570                         fme_interrupt_handler, "fme_irq", mgr);
1571         if (ret)
1572                 goto free_adapter_data;
1573
1574         return ret;
1575
1576 free_adapter_data:
1577         if (data)
1578                 opae_adapter_data_free(data);
1579 cleanup:
1580         if (rawdev)
1581                 rte_rawdev_pmd_release(rawdev);
1582
1583         return ret;
1584 }
1585
1586 static int
1587 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
1588 {
1589         int ret;
1590         struct rte_rawdev *rawdev;
1591         char name[RTE_RAWDEV_NAME_MAX_LEN];
1592         struct opae_adapter *adapter;
1593         struct opae_manager *mgr;
1594         struct ifpga_rawdev *dev;
1595
1596         if (!pci_dev) {
1597                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1598                 ret = -EINVAL;
1599                 return ret;
1600         }
1601
1602         memset(name, 0, sizeof(name));
1603         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, IFPGA_RAWDEV_NAME_FMT,
1604                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1605
1606         IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
1607                 name, rte_socket_id());
1608
1609         rawdev = rte_rawdev_pmd_get_named_dev(name);
1610         if (!rawdev) {
1611                 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
1612                 return -EINVAL;
1613         }
1614         dev = ifpga_rawdev_get(rawdev);
1615         if (dev)
1616                 dev->rawdev = NULL;
1617
1618         adapter = ifpga_rawdev_get_priv(rawdev);
1619         if (!adapter)
1620                 return -ENODEV;
1621
1622         mgr = opae_adapter_get_mgr(adapter);
1623         if (!mgr)
1624                 return -ENODEV;
1625
1626         if (ifpga_unregister_msix_irq(dev, IFPGA_FME_IRQ, 0,
1627                                 fme_interrupt_handler, mgr) < 0)
1628                 return -EINVAL;
1629
1630         /* rte_rawdev_close is called by pmd_release */
1631         ret = rte_rawdev_pmd_release(rawdev);
1632         if (ret)
1633                 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
1634
1635         return ret;
1636 }
1637
1638 static int
1639 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1640         struct rte_pci_device *pci_dev)
1641 {
1642         IFPGA_RAWDEV_PMD_FUNC_TRACE();
1643         return ifpga_rawdev_create(pci_dev, rte_socket_id());
1644 }
1645
1646 static int
1647 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
1648 {
1649         ifpga_monitor_stop_func();
1650         return ifpga_rawdev_destroy(pci_dev);
1651 }
1652
1653 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
1654         .id_table  = pci_ifpga_map,
1655         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1656         .probe     = ifpga_rawdev_pci_probe,
1657         .remove    = ifpga_rawdev_pci_remove,
1658 };
1659
1660 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1661 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1662 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
1663 RTE_LOG_REGISTER_DEFAULT(ifpga_rawdev_logtype, NOTICE);
1664
1665 static const char * const valid_args[] = {
1666 #define IFPGA_ARG_NAME         "ifpga"
1667         IFPGA_ARG_NAME,
1668 #define IFPGA_ARG_PORT         "port"
1669         IFPGA_ARG_PORT,
1670 #define IFPGA_AFU_BTS          "afu_bts"
1671         IFPGA_AFU_BTS,
1672         NULL
1673 };
1674
1675 static int ifpga_rawdev_get_string_arg(const char *key __rte_unused,
1676         const char *value, void *extra_args)
1677 {
1678         int size;
1679         if (!value || !extra_args)
1680                 return -EINVAL;
1681
1682         size = strlen(value) + 1;
1683         *(char **)extra_args = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
1684         if (!*(char **)extra_args)
1685                 return -ENOMEM;
1686
1687         strlcpy(*(char **)extra_args, value, size);
1688
1689         return 0;
1690 }
1691 static int
1692 ifpga_cfg_probe(struct rte_vdev_device *dev)
1693 {
1694         struct rte_devargs *devargs;
1695         struct rte_kvargs *kvlist = NULL;
1696         struct rte_rawdev *rawdev = NULL;
1697         struct ifpga_rawdev *ifpga_dev;
1698         int port;
1699         char *name = NULL;
1700         const char *bdf;
1701         char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1702         int ret = -1;
1703
1704         devargs = dev->device.devargs;
1705
1706         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1707         if (!kvlist) {
1708                 IFPGA_RAWDEV_PMD_LOG(ERR, "error when parsing param");
1709                 goto end;
1710         }
1711
1712         if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
1713                 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
1714                                        &ifpga_rawdev_get_string_arg,
1715                                        &name) < 0) {
1716                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1717                                      IFPGA_ARG_NAME);
1718                         goto end;
1719                 }
1720         } else {
1721                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1722                           IFPGA_ARG_NAME);
1723                 goto end;
1724         }
1725
1726         if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
1727                 if (rte_kvargs_process(kvlist,
1728                         IFPGA_ARG_PORT,
1729                         &rte_ifpga_get_integer32_arg,
1730                         &port) < 0) {
1731                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1732                                 IFPGA_ARG_PORT);
1733                         goto end;
1734                 }
1735         } else {
1736                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1737                           IFPGA_ARG_PORT);
1738                 goto end;
1739         }
1740
1741         memset(dev_name, 0, sizeof(dev_name));
1742         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", name);
1743         rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1744         if (!rawdev)
1745                 goto end;
1746         ifpga_dev = ifpga_rawdev_get(rawdev);
1747         if (!ifpga_dev)
1748                 goto end;
1749         bdf = name;
1750         ifpga_rawdev_fill_info(ifpga_dev, bdf);
1751
1752         ifpga_monitor_start_func();
1753
1754         memset(dev_name, 0, sizeof(dev_name));
1755         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1756         port, name);
1757
1758         ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
1759                         dev_name, devargs->args);
1760 end:
1761         rte_kvargs_free(kvlist);
1762         free(name);
1763
1764         return ret;
1765 }
1766
1767 static int
1768 ifpga_cfg_remove(struct rte_vdev_device *vdev)
1769 {
1770         IFPGA_RAWDEV_PMD_INFO("Remove ifpga_cfg %p",
1771                 vdev);
1772
1773         return 0;
1774 }
1775
1776 static struct rte_vdev_driver ifpga_cfg_driver = {
1777         .probe = ifpga_cfg_probe,
1778         .remove = ifpga_cfg_remove,
1779 };
1780
1781 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
1782 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
1783 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,
1784         "ifpga=<string> "
1785         "port=<int> "
1786         "afu_bts=<path>");
1787
1788 struct rte_pci_bus *ifpga_get_pci_bus(void)
1789 {
1790         return rte_ifpga_rawdev_pmd.bus;
1791 }
1792
1793 int ifpga_rawdev_partial_reconfigure(struct rte_rawdev *dev, int port,
1794         const char *file)
1795 {
1796         if (!dev) {
1797                 IFPGA_RAWDEV_PMD_ERR("Input parameter is invalid");
1798                 return -EINVAL;
1799         }
1800
1801         return rte_fpga_do_pr(dev, port, file);
1802 }
1803
1804 void ifpga_rawdev_cleanup(void)
1805 {
1806         struct ifpga_rawdev *dev;
1807         unsigned int i;
1808
1809         for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
1810                 dev = &ifpga_rawdevices[i];
1811                 if (dev->rawdev) {
1812                         rte_rawdev_pmd_release(dev->rawdev);
1813                         dev->rawdev = NULL;
1814                 }
1815         }
1816 }