1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
11 #include <sys/ioctl.h>
12 #include <sys/epoll.h>
15 #include <rte_malloc.h>
16 #include <rte_devargs.h>
17 #include <rte_memcpy.h>
19 #include <rte_bus_pci.h>
20 #include <rte_kvargs.h>
21 #include <rte_alarm.h>
22 #include <rte_interrupts.h>
23 #include <rte_errno.h>
24 #include <rte_per_lcore.h>
25 #include <rte_memory.h>
26 #include <rte_memzone.h>
28 #include <rte_common.h>
29 #include <rte_bus_vdev.h>
30 #include <rte_string_fns.h>
32 #include "base/opae_hw_api.h"
33 #include "base/opae_ifpga_hw_api.h"
34 #include "base/ifpga_api.h"
35 #include "rte_rawdev.h"
36 #include "rte_rawdev_pmd.h"
37 #include "rte_bus_ifpga.h"
38 #include "ifpga_common.h"
39 #include "ifpga_logs.h"
40 #include "ifpga_rawdev.h"
41 #include "ipn3ke_rawdev_api.h"
43 #define RTE_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
44 #define RTE_PCI_CFG_SPACE_SIZE 256
45 #define RTE_PCI_CFG_SPACE_EXP_SIZE 4096
46 #define RTE_PCI_EXT_CAP_ID(header) (int)(header & 0x0000ffff)
47 #define RTE_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
49 int ifpga_rawdev_logtype;
51 #define PCI_VENDOR_ID_INTEL 0x8086
53 #define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
54 #define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
55 #define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
56 #define PCIE_DEVICE_ID_PAC_N3000 0x0B30
58 #define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
59 #define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
60 #define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
61 #define PCIE_DEVICE_ID_VF_PAC_N3000 0x0B31
62 #define RTE_MAX_RAW_DEVICE 10
64 static const struct rte_pci_id pci_ifpga_map[] = {
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
73 { .vendor_id = 0, /* sentinel */ },
76 static struct ifpga_rawdev ifpga_rawdevices[IFPGA_RAWDEV_NUM];
78 static int ifpga_monitor_start;
79 static pthread_t ifpga_monitor_start_thread;
81 static struct ifpga_rawdev *
82 ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
83 static int set_surprise_link_check_aer(
84 struct ifpga_rawdev *ifpga_rdev, int force_disable);
85 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
87 static int ifpga_pci_find_ext_capability(unsigned int fd, int cap);
90 ifpga_rawdev_get(const struct rte_rawdev *rawdev)
92 struct ifpga_rawdev *dev;
98 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
99 dev = &ifpga_rawdevices[i];
100 if (dev->rawdev == rawdev)
107 static inline uint8_t
108 ifpga_rawdev_find_free_device_index(void)
112 for (dev_id = 0; dev_id < IFPGA_RAWDEV_NUM; dev_id++) {
113 if (ifpga_rawdevices[dev_id].rawdev == NULL)
117 return IFPGA_RAWDEV_NUM;
119 static struct ifpga_rawdev *
120 ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
122 struct ifpga_rawdev *dev;
125 dev = ifpga_rawdev_get(rawdev);
127 IFPGA_RAWDEV_PMD_ERR("Event device already allocated!");
131 dev_id = ifpga_rawdev_find_free_device_index();
132 if (dev_id == IFPGA_RAWDEV_NUM) {
133 IFPGA_RAWDEV_PMD_ERR("Reached maximum number of raw devices");
137 dev = &ifpga_rawdevices[dev_id];
138 dev->rawdev = rawdev;
139 dev->dev_id = dev_id;
144 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
149 int pos = RTE_PCI_CFG_SPACE_SIZE;
152 /* minimum 8 bytes per capability */
153 ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
157 ret = pread(fd, &header, sizeof(header), pos);
162 * If we have no capabilities, this is indicated by cap ID,
163 * cap version and next pointer all being 0.
169 if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
172 pos = RTE_PCI_EXT_CAP_NEXT(header);
173 if (pos < RTE_PCI_CFG_SPACE_SIZE)
175 ret = pread(fd, &header, sizeof(header), pos);
183 static int ifpga_pci_find_ext_capability(unsigned int fd, int cap)
185 return ifpga_pci_find_next_ext_capability(fd, 0, cap);
188 static int ifpga_get_dev_vendor_id(const char *bdf,
189 uint32_t *dev_id, uint32_t *vendor_id)
196 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
197 strlcat(path, bdf, sizeof(path));
198 strlcat(path, "/config", sizeof(path));
199 fd = open(path, O_RDWR);
202 ret = pread(fd, &header, sizeof(header), 0);
207 (*vendor_id) = header & 0xffff;
208 (*dev_id) = (header >> 16) & 0xffff;
213 static int ifpga_rawdev_fill_info(struct ifpga_rawdev *ifpga_dev,
216 char path[1024] = "/sys/bus/pci/devices/0000:";
217 char link[1024], link1[1024];
218 char dir[1024] = "/sys/devices/";
221 char sub_brg_bdf[4][16];
224 struct dirent *entry;
227 unsigned int dom, bus, dev;
229 uint32_t dev_id, vendor_id;
231 strlcat(path, bdf, sizeof(path));
232 memset(link, 0, sizeof(link));
233 memset(link1, 0, sizeof(link1));
234 ret = readlink(path, link, (sizeof(link)-1));
237 strlcpy(link1, link, sizeof(link1));
238 memset(ifpga_dev->parent_bdf, 0, 16);
239 point = strlen(link);
247 rte_memcpy(ifpga_dev->parent_bdf, &link[point], 12);
249 point = strlen(link1);
257 c = strchr(link1, 'p');
260 strlcat(dir, c, sizeof(dir));
267 while ((entry = readdir(dp)) != NULL) {
270 if (entry->d_name[0] == '.')
272 if (strlen(entry->d_name) > 12)
274 if (sscanf(entry->d_name, "%x:%x:%x.%d",
275 &dom, &bus, &dev, &func) < 4)
278 strlcpy(sub_brg_bdf[i],
280 sizeof(sub_brg_bdf[i]));
286 /* get fpga and fvl */
288 for (i = 0; i < 4; i++) {
289 strlcpy(link, dir, sizeof(link));
290 strlcat(link, "/", sizeof(link));
291 strlcat(link, sub_brg_bdf[i], sizeof(link));
295 while ((entry = readdir(dp)) != NULL) {
298 if (entry->d_name[0] == '.')
301 if (strlen(entry->d_name) > 12)
303 if (sscanf(entry->d_name, "%x:%x:%x.%d",
304 &dom, &bus, &dev, &func) < 4)
307 if (ifpga_get_dev_vendor_id(entry->d_name,
308 &dev_id, &vendor_id))
310 if (vendor_id == 0x8086 &&
314 strlcpy(ifpga_dev->fvl_bdf[j],
316 sizeof(ifpga_dev->fvl_bdf[j]));
327 #define HIGH_FATAL(_sens, value)\
328 (((_sens)->flags & OPAE_SENSOR_HIGH_FATAL_VALID) &&\
329 (value > (_sens)->high_fatal))
331 #define HIGH_WARN(_sens, value)\
332 (((_sens)->flags & OPAE_SENSOR_HIGH_WARN_VALID) &&\
333 (value > (_sens)->high_warn))
335 #define LOW_FATAL(_sens, value)\
336 (((_sens)->flags & OPAE_SENSOR_LOW_FATAL_VALID) &&\
337 (value > (_sens)->low_fatal))
339 #define LOW_WARN(_sens, value)\
340 (((_sens)->flags & OPAE_SENSOR_LOW_WARN_VALID) &&\
341 (value > (_sens)->low_warn))
343 #define AUX_VOLTAGE_WARN 11400
346 ifpga_monitor_sensor(struct rte_rawdev *raw_dev,
349 struct opae_adapter *adapter;
350 struct opae_manager *mgr;
351 struct opae_sensor_info *sensor;
355 adapter = ifpga_rawdev_get_priv(raw_dev);
359 mgr = opae_adapter_get_mgr(adapter);
363 opae_mgr_for_each_sensor(sensor) {
364 if (!(sensor->flags & OPAE_SENSOR_VALID))
367 ret = opae_mgr_get_sensor_value(mgr, sensor, &value);
371 if (value == 0xdeadbeef) {
372 IFPGA_RAWDEV_PMD_ERR("sensor %s is invalid value %x\n",
373 sensor->name, value);
377 /* monitor temperature sensors */
378 if (!strcmp(sensor->name, "Board Temperature") ||
379 !strcmp(sensor->name, "FPGA Die Temperature")) {
380 IFPGA_RAWDEV_PMD_INFO("read sensor %s %d %d %d\n",
381 sensor->name, value, sensor->high_warn,
384 if (HIGH_WARN(sensor, value) ||
385 LOW_WARN(sensor, value)) {
386 IFPGA_RAWDEV_PMD_INFO("%s reach theshold %d\n",
387 sensor->name, value);
393 /* monitor 12V AUX sensor */
394 if (!strcmp(sensor->name, "12V AUX Voltage")) {
395 if (value < AUX_VOLTAGE_WARN) {
396 IFPGA_RAWDEV_PMD_INFO("%s reach theshold %d\n",
397 sensor->name, value);
409 static int set_surprise_link_check_aer(
410 struct ifpga_rawdev *ifpga_rdev, int force_disable)
412 struct rte_rawdev *rdev;
419 uint32_t aer_new0, aer_new1;
422 printf("\n device does not exist\n");
426 rdev = ifpga_rdev->rawdev;
427 if (ifpga_rdev->aer_enable)
429 if (ifpga_monitor_sensor(rdev, &enable))
431 if (enable || force_disable) {
432 IFPGA_RAWDEV_PMD_ERR("Set AER, pls graceful shutdown\n");
433 ifpga_rdev->aer_enable = 1;
435 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
436 strlcat(path, ifpga_rdev->parent_bdf, sizeof(path));
437 strlcat(path, "/config", sizeof(path));
438 fd = open(path, O_RDWR);
441 pos = ifpga_pci_find_ext_capability(fd, RTE_PCI_EXT_CAP_ID_ERR);
444 /* save previout ECAP_AER+0x08 */
445 ret = pread(fd, &data, sizeof(data), pos+0x08);
448 ifpga_rdev->aer_old[0] = data;
449 /* save previout ECAP_AER+0x14 */
450 ret = pread(fd, &data, sizeof(data), pos+0x14);
453 ifpga_rdev->aer_old[1] = data;
455 /* set ECAP_AER+0x08 to 0xFFFFFFFF */
457 ret = pwrite(fd, &data, 4, pos+0x08);
460 /* set ECAP_AER+0x14 to 0xFFFFFFFF */
461 ret = pwrite(fd, &data, 4, pos+0x14);
465 /* read current ECAP_AER+0x08 */
466 ret = pread(fd, &data, sizeof(data), pos+0x08);
470 /* read current ECAP_AER+0x14 */
471 ret = pread(fd, &data, sizeof(data), pos+0x14);
479 printf(">>>>>>Set AER %x,%x %x,%x\n",
480 ifpga_rdev->aer_old[0], ifpga_rdev->aer_old[1],
493 ifpga_rawdev_gsd_handle(__rte_unused void *param)
495 struct ifpga_rawdev *ifpga_rdev;
502 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
503 ifpga_rdev = &ifpga_rawdevices[i];
504 if (ifpga_rdev->rawdev) {
505 ret = set_surprise_link_check_aer(ifpga_rdev,
507 if (ret == 1 && !gsd_enable) {
515 printf(">>>>>>Pls Shutdown APP\n");
517 rte_delay_us(100 * MS);
524 ifpga_monitor_start_func(void)
528 if (ifpga_monitor_start == 0) {
529 ret = pthread_create(&ifpga_monitor_start_thread,
531 ifpga_rawdev_gsd_handle, NULL);
533 IFPGA_RAWDEV_PMD_ERR(
534 "Fail to create ifpga nonitor thread");
537 ifpga_monitor_start = 1;
543 ifpga_monitor_stop_func(void)
547 if (ifpga_monitor_start == 1) {
548 ret = pthread_cancel(ifpga_monitor_start_thread);
550 IFPGA_RAWDEV_PMD_ERR("Can't cancel the thread");
552 ret = pthread_join(ifpga_monitor_start_thread, NULL);
554 IFPGA_RAWDEV_PMD_ERR("Can't join the thread");
556 ifpga_monitor_start = 0;
565 ifpga_fill_afu_dev(struct opae_accelerator *acc,
566 struct rte_afu_device *afu_dev)
568 struct rte_mem_resource *res = afu_dev->mem_resource;
569 struct opae_acc_region_info region_info;
570 struct opae_acc_info info;
574 ret = opae_acc_get_info(acc, &info);
578 if (info.num_regions > PCI_MAX_RESOURCE)
581 afu_dev->num_region = info.num_regions;
583 for (i = 0; i < info.num_regions; i++) {
584 region_info.index = i;
585 ret = opae_acc_get_region_info(acc, ®ion_info);
589 if ((region_info.flags & ACC_REGION_MMIO) &&
590 (region_info.flags & ACC_REGION_READ) &&
591 (region_info.flags & ACC_REGION_WRITE)) {
592 res[i].phys_addr = region_info.phys_addr;
593 res[i].len = region_info.len;
594 res[i].addr = region_info.addr;
603 ifpga_rawdev_info_get(struct rte_rawdev *dev,
604 rte_rawdev_obj_t dev_info)
606 struct opae_adapter *adapter;
607 struct opae_accelerator *acc;
608 struct rte_afu_device *afu_dev;
609 struct opae_manager *mgr = NULL;
610 struct opae_eth_group_region_info opae_lside_eth_info;
611 struct opae_eth_group_region_info opae_nside_eth_info;
612 int lside_bar_idx, nside_bar_idx;
614 IFPGA_RAWDEV_PMD_FUNC_TRACE();
617 IFPGA_RAWDEV_PMD_ERR("Invalid request");
621 adapter = ifpga_rawdev_get_priv(dev);
626 afu_dev->rawdev = dev;
628 /* find opae_accelerator and fill info into afu_device */
629 opae_adapter_for_each_acc(adapter, acc) {
630 if (acc->index != afu_dev->id.port)
633 if (ifpga_fill_afu_dev(acc, afu_dev)) {
634 IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
639 /* get opae_manager to rawdev */
640 mgr = opae_adapter_get_mgr(adapter);
642 /* get LineSide BAR Index */
643 if (opae_manager_get_eth_group_region_info(mgr, 0,
644 &opae_lside_eth_info)) {
647 lside_bar_idx = opae_lside_eth_info.mem_idx;
649 /* get NICSide BAR Index */
650 if (opae_manager_get_eth_group_region_info(mgr, 1,
651 &opae_nside_eth_info)) {
654 nside_bar_idx = opae_nside_eth_info.mem_idx;
656 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
657 nside_bar_idx >= PCI_MAX_RESOURCE ||
658 lside_bar_idx == nside_bar_idx)
661 /* fill LineSide BAR Index */
662 afu_dev->mem_resource[lside_bar_idx].phys_addr =
663 opae_lside_eth_info.phys_addr;
664 afu_dev->mem_resource[lside_bar_idx].len =
665 opae_lside_eth_info.len;
666 afu_dev->mem_resource[lside_bar_idx].addr =
667 opae_lside_eth_info.addr;
669 /* fill NICSide BAR Index */
670 afu_dev->mem_resource[nside_bar_idx].phys_addr =
671 opae_nside_eth_info.phys_addr;
672 afu_dev->mem_resource[nside_bar_idx].len =
673 opae_nside_eth_info.len;
674 afu_dev->mem_resource[nside_bar_idx].addr =
675 opae_nside_eth_info.addr;
680 ifpga_rawdev_configure(const struct rte_rawdev *dev,
681 rte_rawdev_obj_t config)
683 IFPGA_RAWDEV_PMD_FUNC_TRACE();
685 RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
687 return config ? 0 : 1;
691 ifpga_rawdev_start(struct rte_rawdev *dev)
694 struct opae_adapter *adapter;
696 IFPGA_RAWDEV_PMD_FUNC_TRACE();
698 RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
700 adapter = ifpga_rawdev_get_priv(dev);
708 ifpga_rawdev_stop(struct rte_rawdev *dev)
714 ifpga_rawdev_close(struct rte_rawdev *dev)
720 ifpga_rawdev_reset(struct rte_rawdev *dev)
726 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size,
730 struct opae_adapter *adapter;
731 struct opae_manager *mgr;
732 struct opae_accelerator *acc;
733 struct opae_bridge *br;
736 adapter = ifpga_rawdev_get_priv(raw_dev);
740 mgr = opae_adapter_get_mgr(adapter);
744 acc = opae_adapter_get_acc(adapter, port_id);
748 br = opae_acc_get_br(acc);
752 ret = opae_manager_flash(mgr, port_id, buffer, size, status);
754 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
758 ret = opae_bridge_reset(br);
760 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
761 __func__, port_id, ret);
769 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
770 const char *file_name)
772 struct stat file_stat;
782 file_fd = open(file_name, O_RDONLY);
784 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
785 __func__, file_name);
786 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
789 ret = stat(file_name, &file_stat);
791 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
796 buffer_size = file_stat.st_size;
797 if (buffer_size <= 0) {
802 IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
803 buffer = rte_malloc(NULL, buffer_size, 0);
809 /*read the raw data*/
810 if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
816 ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
817 IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
818 ret ? "failed" : "success");
834 ifpga_rawdev_pr(struct rte_rawdev *dev,
835 rte_rawdev_obj_t pr_conf)
837 struct opae_adapter *adapter;
838 struct rte_afu_pr_conf *afu_pr_conf;
841 struct opae_accelerator *acc;
843 IFPGA_RAWDEV_PMD_FUNC_TRACE();
845 adapter = ifpga_rawdev_get_priv(dev);
852 afu_pr_conf = pr_conf;
854 if (afu_pr_conf->pr_enable) {
855 ret = rte_fpga_do_pr(dev,
856 afu_pr_conf->afu_id.port,
857 afu_pr_conf->bs_path);
859 IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
864 acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
868 ret = opae_acc_get_uuid(acc, &uuid);
872 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b, sizeof(u64));
873 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high,
874 uuid.b + 8, sizeof(u64));
876 IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n", __func__,
877 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
878 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
884 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
885 const char *attr_name, uint64_t *attr_value)
887 struct opae_adapter *adapter;
888 struct opae_manager *mgr;
889 struct opae_retimer_info opae_rtm_info;
890 struct opae_retimer_status opae_rtm_status;
891 struct opae_eth_group_info opae_eth_grp_info;
892 struct opae_eth_group_region_info opae_eth_grp_reg_info;
893 int eth_group_num = 0;
894 uint64_t port_link_bitmap = 0, port_link_bit;
897 #define MAX_PORT_PER_RETIMER 4
899 IFPGA_RAWDEV_PMD_FUNC_TRACE();
901 if (!dev || !attr_name || !attr_value) {
902 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
906 adapter = ifpga_rawdev_get_priv(dev);
908 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
912 mgr = opae_adapter_get_mgr(adapter);
914 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
918 /* currently, eth_group_num is always 2 */
919 eth_group_num = opae_manager_get_eth_group_nums(mgr);
920 if (eth_group_num < 0)
923 if (!strcmp(attr_name, "LineSideBaseMAC")) {
924 /* Currently FPGA not implement, so just set all zeros*/
925 *attr_value = (uint64_t)0;
928 if (!strcmp(attr_name, "LineSideMACType")) {
929 /* eth_group 0 on FPGA connect to LineSide */
930 if (opae_manager_get_eth_group_info(mgr, 0,
933 switch (opae_eth_grp_info.speed) {
936 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
940 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
944 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
949 if (!strcmp(attr_name, "LineSideLinkSpeed")) {
950 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
952 switch (opae_rtm_status.speed) {
955 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
959 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
963 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
967 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
971 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
975 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
979 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
981 case MXD_SPEED_UNKNOWN:
983 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
987 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
992 if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
993 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
995 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
998 if (!strcmp(attr_name, "LineSideLinkPortNum")) {
999 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1001 uint64_t tmp = (uint64_t)opae_rtm_info.ports_per_retimer *
1002 (uint64_t)opae_rtm_info.nums_retimer;
1006 if (!strcmp(attr_name, "LineSideLinkStatus")) {
1007 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1009 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1013 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
1014 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
1015 p = i * MAX_PORT_PER_RETIMER;
1016 for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
1018 IFPGA_BIT_SET(port_link_bit, (p+j));
1019 port_link_bit &= port_link_bitmap;
1021 IFPGA_BIT_SET((*attr_value), q);
1027 if (!strcmp(attr_name, "LineSideBARIndex")) {
1028 /* eth_group 0 on FPGA connect to LineSide */
1029 if (opae_manager_get_eth_group_region_info(mgr, 0,
1030 &opae_eth_grp_reg_info))
1032 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1035 if (!strcmp(attr_name, "NICSideMACType")) {
1036 /* eth_group 1 on FPGA connect to NicSide */
1037 if (opae_manager_get_eth_group_info(mgr, 1,
1038 &opae_eth_grp_info))
1040 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1043 if (!strcmp(attr_name, "NICSideLinkSpeed")) {
1044 /* eth_group 1 on FPGA connect to NicSide */
1045 if (opae_manager_get_eth_group_info(mgr, 1,
1046 &opae_eth_grp_info))
1048 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1051 if (!strcmp(attr_name, "NICSideLinkPortNum")) {
1052 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1054 uint64_t tmp = (uint64_t)opae_rtm_info.nums_fvl *
1055 (uint64_t)opae_rtm_info.ports_per_fvl;
1059 if (!strcmp(attr_name, "NICSideLinkStatus"))
1061 if (!strcmp(attr_name, "NICSideBARIndex")) {
1062 /* eth_group 1 on FPGA connect to NicSide */
1063 if (opae_manager_get_eth_group_region_info(mgr, 1,
1064 &opae_eth_grp_reg_info))
1066 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1070 IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
1074 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
1075 .dev_info_get = ifpga_rawdev_info_get,
1076 .dev_configure = ifpga_rawdev_configure,
1077 .dev_start = ifpga_rawdev_start,
1078 .dev_stop = ifpga_rawdev_stop,
1079 .dev_close = ifpga_rawdev_close,
1080 .dev_reset = ifpga_rawdev_reset,
1082 .queue_def_conf = NULL,
1083 .queue_setup = NULL,
1084 .queue_release = NULL,
1086 .attr_get = ifpga_rawdev_get_attr,
1089 .enqueue_bufs = NULL,
1090 .dequeue_bufs = NULL,
1095 .xstats_get_names = NULL,
1096 .xstats_get_by_name = NULL,
1097 .xstats_reset = NULL,
1099 .firmware_status_get = NULL,
1100 .firmware_version_get = NULL,
1101 .firmware_load = ifpga_rawdev_pr,
1102 .firmware_unload = NULL,
1104 .dev_selftest = NULL,
1108 ifpga_get_fme_error_prop(struct opae_manager *mgr,
1109 u64 prop_id, u64 *val)
1111 struct feature_prop prop;
1113 prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1114 prop.prop_id = prop_id;
1116 if (opae_manager_ifpga_get_prop(mgr, &prop))
1125 ifpga_set_fme_error_prop(struct opae_manager *mgr,
1126 u64 prop_id, u64 val)
1128 struct feature_prop prop;
1130 prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1131 prop.prop_id = prop_id;
1135 if (opae_manager_ifpga_set_prop(mgr, &prop))
1142 fme_err_read_seu_emr(struct opae_manager *mgr)
1147 ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
1151 IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%" PRIx64 "\n", val);
1153 ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
1157 IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%" PRIx64 "\n", val);
1162 static int fme_clear_warning_intr(struct opae_manager *mgr)
1166 if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
1169 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1171 if ((val & 0x40) != 0)
1172 IFPGA_RAWDEV_PMD_INFO("clean not done\n");
1178 fme_err_handle_error0(struct opae_manager *mgr)
1180 struct feature_fme_error0 fme_error0;
1183 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1186 fme_error0.csr = val;
1188 if (fme_error0.fabric_err)
1189 IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
1190 else if (fme_error0.fabfifo_overflow)
1191 IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
1192 else if (fme_error0.afu_acc_mode_err)
1193 IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
1194 else if (fme_error0.pcie0cdc_parity_err)
1195 IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
1196 else if (fme_error0.cvlcdc_parity_err)
1197 IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
1198 else if (fme_error0.fpgaseuerr)
1199 fme_err_read_seu_emr(mgr);
1201 /* clean the errors */
1202 if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
1209 fme_err_handle_catfatal_error(struct opae_manager *mgr)
1211 struct feature_fme_ras_catfaterror fme_catfatal;
1214 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
1217 fme_catfatal.csr = val;
1219 if (fme_catfatal.cci_fatal_err)
1220 IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
1221 else if (fme_catfatal.fabric_fatal_err)
1222 IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
1223 else if (fme_catfatal.pcie_poison_err)
1224 IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
1225 else if (fme_catfatal.inject_fata_err)
1226 IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
1227 else if (fme_catfatal.crc_catast_err)
1228 IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
1229 else if (fme_catfatal.injected_catast_err)
1230 IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
1231 else if (fme_catfatal.bmc_seu_catast_err)
1232 fme_err_read_seu_emr(mgr);
1238 fme_err_handle_nonfaterror(struct opae_manager *mgr)
1240 struct feature_fme_ras_nonfaterror nonfaterr;
1243 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1246 nonfaterr.csr = val;
1248 if (nonfaterr.temp_thresh_ap1)
1249 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP1\n");
1250 else if (nonfaterr.temp_thresh_ap2)
1251 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP2\n");
1252 else if (nonfaterr.pcie_error)
1253 IFPGA_RAWDEV_PMD_INFO("an error has occurred in pcie\n");
1254 else if (nonfaterr.portfatal_error)
1255 IFPGA_RAWDEV_PMD_INFO("fatal error occurred in AFU port.\n");
1256 else if (nonfaterr.proc_hot)
1257 IFPGA_RAWDEV_PMD_INFO("a ProcHot event\n");
1258 else if (nonfaterr.afu_acc_mode_err)
1259 IFPGA_RAWDEV_PMD_INFO("an AFU PF/VF access mismatch\n");
1260 else if (nonfaterr.injected_nonfata_err) {
1261 IFPGA_RAWDEV_PMD_INFO("Injected Warning Error\n");
1262 fme_clear_warning_intr(mgr);
1263 } else if (nonfaterr.temp_thresh_AP6)
1264 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP6\n");
1265 else if (nonfaterr.power_thresh_AP1)
1266 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP1\n");
1267 else if (nonfaterr.power_thresh_AP2)
1268 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP2\n");
1269 else if (nonfaterr.mbp_err)
1270 IFPGA_RAWDEV_PMD_INFO("an MBP event\n");
1276 fme_interrupt_handler(void *param)
1278 struct opae_manager *mgr = (struct opae_manager *)param;
1280 IFPGA_RAWDEV_PMD_INFO("%s interrupt occurred\n", __func__);
1282 fme_err_handle_error0(mgr);
1283 fme_err_handle_nonfaterror(mgr);
1284 fme_err_handle_catfatal_error(mgr);
1287 static struct rte_intr_handle fme_intr_handle;
1289 static int ifpga_register_fme_interrupt(struct opae_manager *mgr)
1292 struct fpga_fme_err_irq_set err_irq_set;
1294 fme_intr_handle.type = RTE_INTR_HANDLE_VFIO_MSIX;
1296 ret = rte_intr_efd_enable(&fme_intr_handle, 1);
1300 fme_intr_handle.fd = fme_intr_handle.efds[0];
1302 IFPGA_RAWDEV_PMD_DEBUG("vfio_dev_fd=%d, efd=%d, fd=%d\n",
1303 fme_intr_handle.vfio_dev_fd,
1304 fme_intr_handle.efds[0], fme_intr_handle.fd);
1306 err_irq_set.evtfd = fme_intr_handle.efds[0];
1307 ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
1311 /* register FME interrupt using DPDK API */
1312 ret = rte_intr_callback_register(&fme_intr_handle,
1313 fme_interrupt_handler,
1318 IFPGA_RAWDEV_PMD_INFO("success register fme interrupt\n");
1324 ifpga_unregister_fme_interrupt(struct opae_manager *mgr)
1326 rte_intr_efd_disable(&fme_intr_handle);
1328 return rte_intr_callback_unregister(&fme_intr_handle,
1329 fme_interrupt_handler,
1334 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
1338 struct rte_rawdev *rawdev = NULL;
1339 struct ifpga_rawdev *dev = NULL;
1340 struct opae_adapter *adapter = NULL;
1341 struct opae_manager *mgr = NULL;
1342 struct opae_adapter_data_pci *data = NULL;
1343 char name[RTE_RAWDEV_NAME_MAX_LEN];
1347 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1352 memset(name, 0, sizeof(name));
1353 snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%02x:%02x.%x",
1354 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1356 IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
1358 /* Allocate device structure */
1359 rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
1361 if (rawdev == NULL) {
1362 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
1367 dev = ifpga_rawdev_allocate(rawdev);
1369 IFPGA_RAWDEV_PMD_ERR("Unable to allocate ifpga_rawdevice");
1373 dev->aer_enable = 0;
1375 /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
1376 data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
1382 /* init opae_adapter_data_pci for device specific information */
1383 for (i = 0; i < PCI_MAX_RESOURCE; i++) {
1384 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
1385 data->region[i].len = pci_dev->mem_resource[i].len;
1386 data->region[i].addr = pci_dev->mem_resource[i].addr;
1388 data->device_id = pci_dev->id.device_id;
1389 data->vendor_id = pci_dev->id.vendor_id;
1390 data->vfio_dev_fd = pci_dev->intr_handle.vfio_dev_fd;
1392 adapter = rawdev->dev_private;
1393 /* create a opae_adapter based on above device data */
1394 ret = opae_adapter_init(adapter, pci_dev->device.name, data);
1397 goto free_adapter_data;
1400 rawdev->dev_ops = &ifpga_rawdev_ops;
1401 rawdev->device = &pci_dev->device;
1402 rawdev->driver_name = pci_dev->driver->driver.name;
1404 /* must enumerate the adapter before use it */
1405 ret = opae_adapter_enumerate(adapter);
1407 goto free_adapter_data;
1409 /* get opae_manager to rawdev */
1410 mgr = opae_adapter_get_mgr(adapter);
1413 IFPGA_RAWDEV_PMD_INFO("this is a PF function");
1416 ret = ifpga_register_fme_interrupt(mgr);
1418 goto free_adapter_data;
1424 opae_adapter_data_free(data);
1427 rte_rawdev_pmd_release(rawdev);
1433 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
1436 struct rte_rawdev *rawdev;
1437 char name[RTE_RAWDEV_NAME_MAX_LEN];
1438 struct opae_adapter *adapter;
1439 struct opae_manager *mgr;
1442 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1447 memset(name, 0, sizeof(name));
1448 snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%x:%02x.%x",
1449 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1451 IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
1452 name, rte_socket_id());
1454 rawdev = rte_rawdev_pmd_get_named_dev(name);
1456 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
1460 adapter = ifpga_rawdev_get_priv(rawdev);
1464 mgr = opae_adapter_get_mgr(adapter);
1468 if (ifpga_unregister_fme_interrupt(mgr))
1471 opae_adapter_data_free(adapter->data);
1472 opae_adapter_free(adapter);
1474 /* rte_rawdev_close is called by pmd_release */
1475 ret = rte_rawdev_pmd_release(rawdev);
1477 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
1483 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1484 struct rte_pci_device *pci_dev)
1486 IFPGA_RAWDEV_PMD_FUNC_TRACE();
1487 return ifpga_rawdev_create(pci_dev, rte_socket_id());
1491 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
1493 ifpga_monitor_stop_func();
1494 return ifpga_rawdev_destroy(pci_dev);
1497 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
1498 .id_table = pci_ifpga_map,
1499 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1500 .probe = ifpga_rawdev_pci_probe,
1501 .remove = ifpga_rawdev_pci_remove,
1504 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1505 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1506 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
1508 RTE_INIT(ifpga_rawdev_init_log)
1510 ifpga_rawdev_logtype = rte_log_register("driver.raw.init");
1511 if (ifpga_rawdev_logtype >= 0)
1512 rte_log_set_level(ifpga_rawdev_logtype, RTE_LOG_NOTICE);
1515 static const char * const valid_args[] = {
1516 #define IFPGA_ARG_NAME "ifpga"
1518 #define IFPGA_ARG_PORT "port"
1520 #define IFPGA_AFU_BTS "afu_bts"
1525 static int ifpga_rawdev_get_string_arg(const char *key __rte_unused,
1526 const char *value, void *extra_args)
1529 if (!value || !extra_args)
1532 size = strlen(value) + 1;
1533 *(char **)extra_args = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
1534 if (!*(char **)extra_args)
1537 strlcpy(*(char **)extra_args, value, size);
1542 ifpga_cfg_probe(struct rte_vdev_device *dev)
1544 struct rte_devargs *devargs;
1545 struct rte_kvargs *kvlist = NULL;
1546 struct rte_rawdev *rawdev = NULL;
1547 struct ifpga_rawdev *ifpga_dev;
1551 char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1554 devargs = dev->device.devargs;
1556 kvlist = rte_kvargs_parse(devargs->args, valid_args);
1558 IFPGA_RAWDEV_PMD_LOG(ERR, "error when parsing param");
1562 if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
1563 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
1564 &ifpga_rawdev_get_string_arg,
1566 IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1571 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1576 if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
1577 if (rte_kvargs_process(kvlist,
1579 &rte_ifpga_get_integer32_arg,
1581 IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1586 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1591 memset(dev_name, 0, sizeof(dev_name));
1592 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", name);
1593 rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1596 ifpga_dev = ifpga_rawdev_get(rawdev);
1600 ifpga_rawdev_fill_info(ifpga_dev, bdf);
1602 ifpga_monitor_start_func();
1604 memset(dev_name, 0, sizeof(dev_name));
1605 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1608 ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
1609 dev_name, devargs->args);
1612 rte_kvargs_free(kvlist);
1620 ifpga_cfg_remove(struct rte_vdev_device *vdev)
1622 IFPGA_RAWDEV_PMD_INFO("Remove ifpga_cfg %p",
1628 static struct rte_vdev_driver ifpga_cfg_driver = {
1629 .probe = ifpga_cfg_probe,
1630 .remove = ifpga_cfg_remove,
1633 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
1634 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
1635 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,