1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
11 #include <sys/ioctl.h>
12 #include <sys/epoll.h>
15 #include <rte_malloc.h>
16 #include <rte_devargs.h>
17 #include <rte_memcpy.h>
19 #include <rte_bus_pci.h>
20 #include <rte_kvargs.h>
21 #include <rte_alarm.h>
22 #include <rte_interrupts.h>
23 #include <rte_errno.h>
24 #include <rte_per_lcore.h>
25 #include <rte_memory.h>
26 #include <rte_memzone.h>
28 #include <rte_common.h>
29 #include <rte_bus_vdev.h>
30 #include <rte_string_fns.h>
31 #include <rte_pmd_i40e.h>
33 #include "base/opae_hw_api.h"
34 #include "base/opae_ifpga_hw_api.h"
35 #include "base/ifpga_api.h"
36 #include "rte_rawdev.h"
37 #include "rte_rawdev_pmd.h"
38 #include "rte_bus_ifpga.h"
39 #include "ifpga_common.h"
40 #include "ifpga_logs.h"
41 #include "ifpga_rawdev.h"
42 #include "ipn3ke_rawdev_api.h"
44 #define PCI_VENDOR_ID_INTEL 0x8086
46 #define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
47 #define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
48 #define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
49 #define PCIE_DEVICE_ID_PAC_N3000 0x0B30
51 #define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
52 #define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
53 #define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
54 #define PCIE_DEVICE_ID_VF_PAC_N3000 0x0B31
55 #define RTE_MAX_RAW_DEVICE 10
57 static const struct rte_pci_id pci_ifpga_map[] = {
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
66 { .vendor_id = 0, /* sentinel */ },
69 static struct ifpga_rawdev ifpga_rawdevices[IFPGA_RAWDEV_NUM];
71 static int ifpga_monitor_start;
72 static pthread_t ifpga_monitor_start_thread;
74 #define IFPGA_MAX_IRQ 12
75 /* 0 for FME interrupt, others are reserved for AFU irq */
76 static struct rte_intr_handle *ifpga_irq_handle[IFPGA_MAX_IRQ];
78 static struct ifpga_rawdev *
79 ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
80 static int set_surprise_link_check_aer(
81 struct ifpga_rawdev *ifpga_rdev, int force_disable);
82 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
83 int start, uint32_t cap);
84 static int ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap);
87 ifpga_rawdev_get(const struct rte_rawdev *rawdev)
89 struct ifpga_rawdev *dev;
95 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
96 dev = &ifpga_rawdevices[i];
97 if (dev->rawdev == rawdev)
104 static inline uint8_t
105 ifpga_rawdev_find_free_device_index(void)
109 for (dev_id = 0; dev_id < IFPGA_RAWDEV_NUM; dev_id++) {
110 if (ifpga_rawdevices[dev_id].rawdev == NULL)
114 return IFPGA_RAWDEV_NUM;
116 static struct ifpga_rawdev *
117 ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
119 struct ifpga_rawdev *dev;
122 dev = ifpga_rawdev_get(rawdev);
124 IFPGA_RAWDEV_PMD_ERR("Event device already allocated!");
128 dev_id = ifpga_rawdev_find_free_device_index();
129 if (dev_id == IFPGA_RAWDEV_NUM) {
130 IFPGA_RAWDEV_PMD_ERR("Reached maximum number of raw devices");
134 dev = &ifpga_rawdevices[dev_id];
135 dev->rawdev = rawdev;
136 dev->dev_id = dev_id;
142 ifpga_pci_find_next_ext_capability(unsigned int fd, int start, uint32_t cap)
146 int pos = RTE_PCI_CFG_SPACE_SIZE;
149 /* minimum 8 bytes per capability */
150 ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
154 ret = pread(fd, &header, sizeof(header), pos);
159 * If we have no capabilities, this is indicated by cap ID,
160 * cap version and next pointer all being 0.
166 if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
169 pos = RTE_PCI_EXT_CAP_NEXT(header);
170 if (pos < RTE_PCI_CFG_SPACE_SIZE)
172 ret = pread(fd, &header, sizeof(header), pos);
181 ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap)
183 return ifpga_pci_find_next_ext_capability(fd, 0, cap);
186 static int ifpga_get_dev_vendor_id(const char *bdf,
187 uint32_t *dev_id, uint32_t *vendor_id)
194 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
195 strlcat(path, bdf, sizeof(path));
196 strlcat(path, "/config", sizeof(path));
197 fd = open(path, O_RDWR);
200 ret = pread(fd, &header, sizeof(header), 0);
205 (*vendor_id) = header & 0xffff;
206 (*dev_id) = (header >> 16) & 0xffff;
211 static int ifpga_rawdev_fill_info(struct ifpga_rawdev *ifpga_dev,
214 char path[1024] = "/sys/bus/pci/devices/0000:";
215 char link[1024], link1[1024];
216 char dir[1024] = "/sys/devices/";
219 char sub_brg_bdf[4][16] = {{0}};
222 struct dirent *entry;
225 unsigned int dom, bus, dev;
227 uint32_t dev_id, vendor_id;
229 strlcat(path, bdf, sizeof(path));
230 memset(link, 0, sizeof(link));
231 memset(link1, 0, sizeof(link1));
232 ret = readlink(path, link, (sizeof(link)-1));
233 if ((ret < 0) || ((unsigned int)ret > (sizeof(link)-1)))
235 link[ret] = 0; /* terminate string with null character */
236 strlcpy(link1, link, sizeof(link1));
237 memset(ifpga_dev->parent_bdf, 0, 16);
238 point = strlen(link);
246 rte_memcpy(ifpga_dev->parent_bdf, &link[point], 12);
248 point = strlen(link1);
256 c = strchr(link1, 'p');
259 strlcat(dir, c, sizeof(dir));
266 while ((entry = readdir(dp)) != NULL) {
269 if (entry->d_name[0] == '.')
271 if (strlen(entry->d_name) > 12)
273 if (sscanf(entry->d_name, "%x:%x:%x.%d",
274 &dom, &bus, &dev, &func) < 4)
277 strlcpy(sub_brg_bdf[i],
279 sizeof(sub_brg_bdf[i]));
285 /* get fpga and fvl */
287 for (i = 0; i < 4; i++) {
288 strlcpy(link, dir, sizeof(link));
289 strlcat(link, "/", sizeof(link));
290 strlcat(link, sub_brg_bdf[i], sizeof(link));
294 while ((entry = readdir(dp)) != NULL) {
297 if (entry->d_name[0] == '.')
300 if (strlen(entry->d_name) > 12)
302 if (sscanf(entry->d_name, "%x:%x:%x.%d",
303 &dom, &bus, &dev, &func) < 4)
306 if (ifpga_get_dev_vendor_id(entry->d_name,
307 &dev_id, &vendor_id))
309 if (vendor_id == 0x8086 &&
313 strlcpy(ifpga_dev->fvl_bdf[j],
315 sizeof(ifpga_dev->fvl_bdf[j]));
326 #define HIGH_FATAL(_sens, value)\
327 (((_sens)->flags & OPAE_SENSOR_HIGH_FATAL_VALID) &&\
328 (value > (_sens)->high_fatal))
330 #define HIGH_WARN(_sens, value)\
331 (((_sens)->flags & OPAE_SENSOR_HIGH_WARN_VALID) &&\
332 (value > (_sens)->high_warn))
334 #define LOW_FATAL(_sens, value)\
335 (((_sens)->flags & OPAE_SENSOR_LOW_FATAL_VALID) &&\
336 (value > (_sens)->low_fatal))
338 #define LOW_WARN(_sens, value)\
339 (((_sens)->flags & OPAE_SENSOR_LOW_WARN_VALID) &&\
340 (value > (_sens)->low_warn))
342 #define AUX_VOLTAGE_WARN 11400
345 ifpga_monitor_sensor(struct rte_rawdev *raw_dev,
348 struct opae_adapter *adapter;
349 struct opae_manager *mgr;
350 struct opae_sensor_info *sensor;
354 adapter = ifpga_rawdev_get_priv(raw_dev);
358 mgr = opae_adapter_get_mgr(adapter);
362 opae_mgr_for_each_sensor(mgr, sensor) {
363 if (!(sensor->flags & OPAE_SENSOR_VALID))
366 ret = opae_mgr_get_sensor_value(mgr, sensor, &value);
370 if (value == 0xdeadbeef) {
371 IFPGA_RAWDEV_PMD_ERR("dev_id %d sensor %s value %x\n",
372 raw_dev->dev_id, sensor->name, value);
376 /* monitor temperature sensors */
377 if (!strcmp(sensor->name, "Board Temperature") ||
378 !strcmp(sensor->name, "FPGA Die Temperature")) {
379 IFPGA_RAWDEV_PMD_INFO("read sensor %s %d %d %d\n",
380 sensor->name, value, sensor->high_warn,
383 if (HIGH_WARN(sensor, value) ||
384 LOW_WARN(sensor, value)) {
385 IFPGA_RAWDEV_PMD_INFO("%s reach threshold %d\n",
386 sensor->name, value);
392 /* monitor 12V AUX sensor */
393 if (!strcmp(sensor->name, "12V AUX Voltage")) {
394 if (value < AUX_VOLTAGE_WARN) {
395 IFPGA_RAWDEV_PMD_INFO(
396 "%s reach threshold %d mV\n",
397 sensor->name, value);
409 static int set_surprise_link_check_aer(
410 struct ifpga_rawdev *ifpga_rdev, int force_disable)
412 struct rte_rawdev *rdev;
419 uint32_t aer_new0, aer_new1;
422 printf("\n device does not exist\n");
426 rdev = ifpga_rdev->rawdev;
427 if (ifpga_rdev->aer_enable)
429 if (ifpga_monitor_sensor(rdev, &enable))
431 if (enable || force_disable) {
432 IFPGA_RAWDEV_PMD_ERR("Set AER, pls graceful shutdown\n");
433 ifpga_rdev->aer_enable = 1;
435 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
436 strlcat(path, ifpga_rdev->parent_bdf, sizeof(path));
437 strlcat(path, "/config", sizeof(path));
438 fd = open(path, O_RDWR);
441 pos = ifpga_pci_find_ext_capability(fd, RTE_PCI_EXT_CAP_ID_ERR);
444 /* save previous ECAP_AER+0x08 */
445 ret = pread(fd, &data, sizeof(data), pos+0x08);
448 ifpga_rdev->aer_old[0] = data;
449 /* save previous ECAP_AER+0x14 */
450 ret = pread(fd, &data, sizeof(data), pos+0x14);
453 ifpga_rdev->aer_old[1] = data;
455 /* set ECAP_AER+0x08 to 0xFFFFFFFF */
457 ret = pwrite(fd, &data, 4, pos+0x08);
460 /* set ECAP_AER+0x14 to 0xFFFFFFFF */
461 ret = pwrite(fd, &data, 4, pos+0x14);
465 /* read current ECAP_AER+0x08 */
466 ret = pread(fd, &data, sizeof(data), pos+0x08);
470 /* read current ECAP_AER+0x14 */
471 ret = pread(fd, &data, sizeof(data), pos+0x14);
479 printf(">>>>>>Set AER %x,%x %x,%x\n",
480 ifpga_rdev->aer_old[0], ifpga_rdev->aer_old[1],
493 ifpga_rawdev_gsd_handle(__rte_unused void *param)
495 struct ifpga_rawdev *ifpga_rdev;
500 while (__atomic_load_n(&ifpga_monitor_start, __ATOMIC_RELAXED)) {
502 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
503 ifpga_rdev = &ifpga_rawdevices[i];
504 if (ifpga_rdev->rawdev) {
505 ret = set_surprise_link_check_aer(ifpga_rdev,
507 if (ret == 1 && !gsd_enable) {
515 printf(">>>>>>Pls Shutdown APP\n");
517 rte_delay_us(100 * MS);
524 ifpga_monitor_start_func(void)
528 if (!__atomic_load_n(&ifpga_monitor_start, __ATOMIC_RELAXED)) {
529 ret = rte_ctrl_thread_create(&ifpga_monitor_start_thread,
530 "ifpga-monitor", NULL,
531 ifpga_rawdev_gsd_handle, NULL);
533 IFPGA_RAWDEV_PMD_ERR(
534 "Fail to create ifpga monitor thread");
537 __atomic_store_n(&ifpga_monitor_start, 1, __ATOMIC_RELAXED);
543 ifpga_monitor_stop_func(void)
547 if (__atomic_load_n(&ifpga_monitor_start, __ATOMIC_RELAXED)) {
548 __atomic_store_n(&ifpga_monitor_start, 0, __ATOMIC_RELAXED);
550 ret = pthread_cancel(ifpga_monitor_start_thread);
552 IFPGA_RAWDEV_PMD_ERR("Can't cancel the thread");
554 ret = pthread_join(ifpga_monitor_start_thread, NULL);
556 IFPGA_RAWDEV_PMD_ERR("Can't join the thread");
565 ifpga_fill_afu_dev(struct opae_accelerator *acc,
566 struct rte_afu_device *afu_dev)
568 struct rte_mem_resource *res = afu_dev->mem_resource;
569 struct opae_acc_region_info region_info;
570 struct opae_acc_info info;
574 ret = opae_acc_get_info(acc, &info);
578 if (info.num_regions > PCI_MAX_RESOURCE)
581 afu_dev->num_region = info.num_regions;
583 for (i = 0; i < info.num_regions; i++) {
584 region_info.index = i;
585 ret = opae_acc_get_region_info(acc, ®ion_info);
589 if ((region_info.flags & ACC_REGION_MMIO) &&
590 (region_info.flags & ACC_REGION_READ) &&
591 (region_info.flags & ACC_REGION_WRITE)) {
592 res[i].phys_addr = region_info.phys_addr;
593 res[i].len = region_info.len;
594 res[i].addr = region_info.addr;
603 ifpga_rawdev_info_get(struct rte_rawdev *dev,
604 rte_rawdev_obj_t dev_info,
605 size_t dev_info_size)
607 struct opae_adapter *adapter;
608 struct opae_accelerator *acc;
609 struct rte_afu_device *afu_dev;
610 struct opae_manager *mgr = NULL;
611 struct opae_eth_group_region_info opae_lside_eth_info;
612 struct opae_eth_group_region_info opae_nside_eth_info;
613 int lside_bar_idx, nside_bar_idx;
615 IFPGA_RAWDEV_PMD_FUNC_TRACE();
617 if (!dev_info || dev_info_size != sizeof(*afu_dev)) {
618 IFPGA_RAWDEV_PMD_ERR("Invalid request");
622 adapter = ifpga_rawdev_get_priv(dev);
627 afu_dev->rawdev = dev;
629 /* find opae_accelerator and fill info into afu_device */
630 opae_adapter_for_each_acc(adapter, acc) {
631 if (acc->index != afu_dev->id.port)
634 if (ifpga_fill_afu_dev(acc, afu_dev)) {
635 IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
640 /* get opae_manager to rawdev */
641 mgr = opae_adapter_get_mgr(adapter);
643 /* get LineSide BAR Index */
644 if (opae_manager_get_eth_group_region_info(mgr, 0,
645 &opae_lside_eth_info)) {
648 lside_bar_idx = opae_lside_eth_info.mem_idx;
650 /* get NICSide BAR Index */
651 if (opae_manager_get_eth_group_region_info(mgr, 1,
652 &opae_nside_eth_info)) {
655 nside_bar_idx = opae_nside_eth_info.mem_idx;
657 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
658 nside_bar_idx >= PCI_MAX_RESOURCE ||
659 lside_bar_idx == nside_bar_idx)
662 /* fill LineSide BAR Index */
663 afu_dev->mem_resource[lside_bar_idx].phys_addr =
664 opae_lside_eth_info.phys_addr;
665 afu_dev->mem_resource[lside_bar_idx].len =
666 opae_lside_eth_info.len;
667 afu_dev->mem_resource[lside_bar_idx].addr =
668 opae_lside_eth_info.addr;
670 /* fill NICSide BAR Index */
671 afu_dev->mem_resource[nside_bar_idx].phys_addr =
672 opae_nside_eth_info.phys_addr;
673 afu_dev->mem_resource[nside_bar_idx].len =
674 opae_nside_eth_info.len;
675 afu_dev->mem_resource[nside_bar_idx].addr =
676 opae_nside_eth_info.addr;
682 ifpga_rawdev_configure(const struct rte_rawdev *dev,
683 rte_rawdev_obj_t config,
684 size_t config_size __rte_unused)
686 IFPGA_RAWDEV_PMD_FUNC_TRACE();
688 RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
690 return config ? 0 : 1;
694 ifpga_rawdev_start(struct rte_rawdev *dev)
697 struct opae_adapter *adapter;
699 IFPGA_RAWDEV_PMD_FUNC_TRACE();
701 RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
703 adapter = ifpga_rawdev_get_priv(dev);
711 ifpga_rawdev_stop(struct rte_rawdev *dev)
717 ifpga_rawdev_close(struct rte_rawdev *dev)
719 struct opae_adapter *adapter;
722 adapter = ifpga_rawdev_get_priv(dev);
724 opae_adapter_destroy(adapter);
725 opae_adapter_data_free(adapter->data);
733 ifpga_rawdev_reset(struct rte_rawdev *dev)
739 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size,
743 struct opae_adapter *adapter;
744 struct opae_manager *mgr;
745 struct opae_accelerator *acc;
746 struct opae_bridge *br;
749 adapter = ifpga_rawdev_get_priv(raw_dev);
753 mgr = opae_adapter_get_mgr(adapter);
757 acc = opae_adapter_get_acc(adapter, port_id);
761 br = opae_acc_get_br(acc);
765 ret = opae_manager_flash(mgr, port_id, buffer, size, status);
767 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
771 ret = opae_bridge_reset(br);
773 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
774 __func__, port_id, ret);
782 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
783 const char *file_name)
785 struct stat file_stat;
789 void *buffer, *buf_to_free;
795 file_fd = open(file_name, O_RDONLY);
797 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
798 __func__, file_name);
799 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
802 ret = stat(file_name, &file_stat);
804 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
809 buffer_size = file_stat.st_size;
810 if (buffer_size <= 0) {
815 IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
816 buffer = rte_malloc(NULL, buffer_size, 0);
821 buf_to_free = buffer;
823 /*read the raw data*/
824 if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
830 ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
831 IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
832 ret ? "failed" : "success");
839 rte_free(buf_to_free);
847 ifpga_rawdev_pr(struct rte_rawdev *dev,
848 rte_rawdev_obj_t pr_conf)
850 struct opae_adapter *adapter;
851 struct opae_manager *mgr;
852 struct opae_board_info *info;
853 struct rte_afu_pr_conf *afu_pr_conf;
856 struct opae_accelerator *acc;
858 IFPGA_RAWDEV_PMD_FUNC_TRACE();
860 adapter = ifpga_rawdev_get_priv(dev);
867 afu_pr_conf = pr_conf;
869 if (afu_pr_conf->pr_enable) {
870 ret = rte_fpga_do_pr(dev,
871 afu_pr_conf->afu_id.port,
872 afu_pr_conf->bs_path);
874 IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
879 mgr = opae_adapter_get_mgr(adapter);
881 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
885 if (ifpga_mgr_ops.get_board_info(mgr, &info)) {
886 IFPGA_RAWDEV_PMD_ERR("ifpga manager get_board_info fail!");
890 if (info->lightweight) {
891 /* set uuid to all 0, when fpga is lightweight image */
892 memset(&afu_pr_conf->afu_id.uuid.uuid_low, 0, sizeof(u64));
893 memset(&afu_pr_conf->afu_id.uuid.uuid_high, 0, sizeof(u64));
895 acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
899 ret = opae_acc_get_uuid(acc, &uuid);
903 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b,
905 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high, uuid.b + 8,
908 IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n",
910 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
911 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
917 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
918 const char *attr_name, uint64_t *attr_value)
920 struct opae_adapter *adapter;
921 struct opae_manager *mgr;
922 struct opae_retimer_info opae_rtm_info;
923 struct opae_retimer_status opae_rtm_status;
924 struct opae_eth_group_info opae_eth_grp_info;
925 struct opae_eth_group_region_info opae_eth_grp_reg_info;
926 int eth_group_num = 0;
927 uint64_t port_link_bitmap = 0, port_link_bit;
930 #define MAX_PORT_PER_RETIMER 4
932 IFPGA_RAWDEV_PMD_FUNC_TRACE();
934 if (!dev || !attr_name || !attr_value) {
935 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
939 adapter = ifpga_rawdev_get_priv(dev);
941 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
945 mgr = opae_adapter_get_mgr(adapter);
947 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
951 /* currently, eth_group_num is always 2 */
952 eth_group_num = opae_manager_get_eth_group_nums(mgr);
953 if (eth_group_num < 0)
956 if (!strcmp(attr_name, "LineSideBaseMAC")) {
957 /* Currently FPGA not implement, so just set all zeros*/
958 *attr_value = (uint64_t)0;
961 if (!strcmp(attr_name, "LineSideMACType")) {
962 /* eth_group 0 on FPGA connect to LineSide */
963 if (opae_manager_get_eth_group_info(mgr, 0,
966 switch (opae_eth_grp_info.speed) {
969 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
973 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
977 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
982 if (!strcmp(attr_name, "LineSideLinkSpeed")) {
983 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
985 switch (opae_rtm_status.speed) {
988 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
992 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
996 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1000 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
1004 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
1008 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
1012 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1014 case MXD_SPEED_UNKNOWN:
1016 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1020 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1025 if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
1026 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1028 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
1031 if (!strcmp(attr_name, "LineSideLinkPortNum")) {
1032 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1034 uint64_t tmp = (uint64_t)opae_rtm_info.ports_per_retimer *
1035 (uint64_t)opae_rtm_info.nums_retimer;
1039 if (!strcmp(attr_name, "LineSideLinkStatus")) {
1040 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1042 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1046 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
1047 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
1048 p = i * MAX_PORT_PER_RETIMER;
1049 for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
1051 IFPGA_BIT_SET(port_link_bit, (p+j));
1052 port_link_bit &= port_link_bitmap;
1054 IFPGA_BIT_SET((*attr_value), q);
1060 if (!strcmp(attr_name, "LineSideBARIndex")) {
1061 /* eth_group 0 on FPGA connect to LineSide */
1062 if (opae_manager_get_eth_group_region_info(mgr, 0,
1063 &opae_eth_grp_reg_info))
1065 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1068 if (!strcmp(attr_name, "NICSideMACType")) {
1069 /* eth_group 1 on FPGA connect to NicSide */
1070 if (opae_manager_get_eth_group_info(mgr, 1,
1071 &opae_eth_grp_info))
1073 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1076 if (!strcmp(attr_name, "NICSideLinkSpeed")) {
1077 /* eth_group 1 on FPGA connect to NicSide */
1078 if (opae_manager_get_eth_group_info(mgr, 1,
1079 &opae_eth_grp_info))
1081 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1084 if (!strcmp(attr_name, "NICSideLinkPortNum")) {
1085 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1087 uint64_t tmp = (uint64_t)opae_rtm_info.nums_fvl *
1088 (uint64_t)opae_rtm_info.ports_per_fvl;
1092 if (!strcmp(attr_name, "NICSideLinkStatus"))
1094 if (!strcmp(attr_name, "NICSideBARIndex")) {
1095 /* eth_group 1 on FPGA connect to NicSide */
1096 if (opae_manager_get_eth_group_region_info(mgr, 1,
1097 &opae_eth_grp_reg_info))
1099 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1103 IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
1107 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
1108 .dev_info_get = ifpga_rawdev_info_get,
1109 .dev_configure = ifpga_rawdev_configure,
1110 .dev_start = ifpga_rawdev_start,
1111 .dev_stop = ifpga_rawdev_stop,
1112 .dev_close = ifpga_rawdev_close,
1113 .dev_reset = ifpga_rawdev_reset,
1115 .queue_def_conf = NULL,
1116 .queue_setup = NULL,
1117 .queue_release = NULL,
1119 .attr_get = ifpga_rawdev_get_attr,
1122 .enqueue_bufs = NULL,
1123 .dequeue_bufs = NULL,
1128 .xstats_get_names = NULL,
1129 .xstats_get_by_name = NULL,
1130 .xstats_reset = NULL,
1132 .firmware_status_get = NULL,
1133 .firmware_version_get = NULL,
1134 .firmware_load = ifpga_rawdev_pr,
1135 .firmware_unload = NULL,
1137 .dev_selftest = NULL,
1141 ifpga_get_fme_error_prop(struct opae_manager *mgr,
1142 u64 prop_id, u64 *val)
1144 struct feature_prop prop;
1146 prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1147 prop.prop_id = prop_id;
1149 if (opae_manager_ifpga_get_prop(mgr, &prop))
1158 ifpga_set_fme_error_prop(struct opae_manager *mgr,
1159 u64 prop_id, u64 val)
1161 struct feature_prop prop;
1163 prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1164 prop.prop_id = prop_id;
1168 if (opae_manager_ifpga_set_prop(mgr, &prop))
1175 fme_err_read_seu_emr(struct opae_manager *mgr)
1180 ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
1184 IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%" PRIx64 "\n", val);
1186 ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
1190 IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%" PRIx64 "\n", val);
1195 static int fme_clear_warning_intr(struct opae_manager *mgr)
1199 if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
1202 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1204 if ((val & 0x40) != 0)
1205 IFPGA_RAWDEV_PMD_INFO("clean not done\n");
1210 static int fme_clean_fme_error(struct opae_manager *mgr)
1214 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1217 IFPGA_RAWDEV_PMD_DEBUG("before clean 0x%" PRIx64 "\n", val);
1219 ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_CLEAR, val);
1221 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1224 IFPGA_RAWDEV_PMD_DEBUG("after clean 0x%" PRIx64 "\n", val);
1230 fme_err_handle_error0(struct opae_manager *mgr)
1232 struct feature_fme_error0 fme_error0;
1235 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1238 if (fme_clean_fme_error(mgr))
1241 fme_error0.csr = val;
1243 if (fme_error0.fabric_err)
1244 IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
1245 else if (fme_error0.fabfifo_overflow)
1246 IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
1247 else if (fme_error0.afu_acc_mode_err)
1248 IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
1249 else if (fme_error0.pcie0cdc_parity_err)
1250 IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
1251 else if (fme_error0.cvlcdc_parity_err)
1252 IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
1253 else if (fme_error0.fpgaseuerr)
1254 fme_err_read_seu_emr(mgr);
1256 /* clean the errors */
1257 if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
1264 fme_err_handle_catfatal_error(struct opae_manager *mgr)
1266 struct feature_fme_ras_catfaterror fme_catfatal;
1269 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
1272 fme_catfatal.csr = val;
1274 if (fme_catfatal.cci_fatal_err)
1275 IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
1276 else if (fme_catfatal.fabric_fatal_err)
1277 IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
1278 else if (fme_catfatal.pcie_poison_err)
1279 IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
1280 else if (fme_catfatal.inject_fata_err)
1281 IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
1282 else if (fme_catfatal.crc_catast_err)
1283 IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
1284 else if (fme_catfatal.injected_catast_err)
1285 IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
1286 else if (fme_catfatal.bmc_seu_catast_err)
1287 fme_err_read_seu_emr(mgr);
1293 fme_err_handle_nonfaterror(struct opae_manager *mgr)
1295 struct feature_fme_ras_nonfaterror nonfaterr;
1298 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1301 nonfaterr.csr = val;
1303 if (nonfaterr.temp_thresh_ap1)
1304 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP1\n");
1305 else if (nonfaterr.temp_thresh_ap2)
1306 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP2\n");
1307 else if (nonfaterr.pcie_error)
1308 IFPGA_RAWDEV_PMD_INFO("an error has occurred in pcie\n");
1309 else if (nonfaterr.portfatal_error)
1310 IFPGA_RAWDEV_PMD_INFO("fatal error occurred in AFU port.\n");
1311 else if (nonfaterr.proc_hot)
1312 IFPGA_RAWDEV_PMD_INFO("a ProcHot event\n");
1313 else if (nonfaterr.afu_acc_mode_err)
1314 IFPGA_RAWDEV_PMD_INFO("an AFU PF/VF access mismatch\n");
1315 else if (nonfaterr.injected_nonfata_err) {
1316 IFPGA_RAWDEV_PMD_INFO("Injected Warning Error\n");
1317 fme_clear_warning_intr(mgr);
1318 } else if (nonfaterr.temp_thresh_AP6)
1319 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP6\n");
1320 else if (nonfaterr.power_thresh_AP1)
1321 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP1\n");
1322 else if (nonfaterr.power_thresh_AP2)
1323 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP2\n");
1324 else if (nonfaterr.mbp_err)
1325 IFPGA_RAWDEV_PMD_INFO("an MBP event\n");
1331 fme_interrupt_handler(void *param)
1333 struct opae_manager *mgr = (struct opae_manager *)param;
1335 IFPGA_RAWDEV_PMD_INFO("%s interrupt occurred\n", __func__);
1337 fme_err_handle_error0(mgr);
1338 fme_err_handle_nonfaterror(mgr);
1339 fme_err_handle_catfatal_error(mgr);
1343 ifpga_unregister_msix_irq(enum ifpga_irq_type type,
1344 int vec_start, rte_intr_callback_fn handler, void *arg)
1346 struct rte_intr_handle *intr_handle;
1349 if (type == IFPGA_FME_IRQ)
1350 intr_handle = ifpga_irq_handle[0];
1351 else if (type == IFPGA_AFU_IRQ)
1352 intr_handle = ifpga_irq_handle[vec_start + 1];
1356 rte_intr_efd_disable(intr_handle);
1358 rc = rte_intr_callback_unregister(intr_handle, handler, arg);
1360 for (i = 0; i < IFPGA_MAX_IRQ; i++)
1361 rte_intr_instance_free(ifpga_irq_handle[i]);
1366 ifpga_register_msix_irq(struct rte_rawdev *dev, int port_id,
1367 enum ifpga_irq_type type, int vec_start, int count,
1368 rte_intr_callback_fn handler, const char *name,
1372 struct rte_intr_handle *intr_handle;
1373 struct opae_adapter *adapter;
1374 struct opae_manager *mgr;
1375 struct opae_accelerator *acc;
1376 int *intr_efds = NULL, nb_intr, i;
1378 for (i = 0; i < IFPGA_MAX_IRQ; i++) {
1379 ifpga_irq_handle[i] =
1380 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
1381 if (ifpga_irq_handle[i] == NULL)
1385 adapter = ifpga_rawdev_get_priv(dev);
1389 mgr = opae_adapter_get_mgr(adapter);
1393 if (type == IFPGA_FME_IRQ) {
1394 intr_handle = ifpga_irq_handle[0];
1396 } else if (type == IFPGA_AFU_IRQ) {
1397 intr_handle = ifpga_irq_handle[vec_start + 1];
1402 if (rte_intr_type_set(intr_handle, RTE_INTR_HANDLE_VFIO_MSIX))
1405 ret = rte_intr_efd_enable(intr_handle, count);
1409 if (rte_intr_fd_set(intr_handle,
1410 rte_intr_efds_index_get(intr_handle, 0)))
1413 IFPGA_RAWDEV_PMD_DEBUG("register %s irq, vfio_fd=%d, fd=%d\n",
1414 name, rte_intr_dev_fd_get(intr_handle),
1415 rte_intr_fd_get(intr_handle));
1417 if (type == IFPGA_FME_IRQ) {
1418 struct fpga_fme_err_irq_set err_irq_set;
1419 err_irq_set.evtfd = rte_intr_efds_index_get(intr_handle,
1422 ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
1425 } else if (type == IFPGA_AFU_IRQ) {
1426 acc = opae_adapter_get_acc(adapter, port_id);
1430 nb_intr = rte_intr_nb_intr_get(intr_handle);
1432 intr_efds = calloc(nb_intr, sizeof(int));
1436 for (i = 0; i < nb_intr; i++)
1437 intr_efds[i] = rte_intr_efds_index_get(intr_handle, i);
1439 ret = opae_acc_set_irq(acc, vec_start, count, intr_efds);
1446 /* register interrupt handler using DPDK API */
1447 ret = rte_intr_callback_register(intr_handle,
1448 handler, (void *)arg);
1454 IFPGA_RAWDEV_PMD_INFO("success register %s interrupt\n", name);
1461 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
1465 struct rte_rawdev *rawdev = NULL;
1466 struct ifpga_rawdev *dev = NULL;
1467 struct opae_adapter *adapter = NULL;
1468 struct opae_manager *mgr = NULL;
1469 struct opae_adapter_data_pci *data = NULL;
1470 char name[RTE_RAWDEV_NAME_MAX_LEN];
1474 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1479 memset(name, 0, sizeof(name));
1480 snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, IFPGA_RAWDEV_NAME_FMT,
1481 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1483 IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
1485 /* Allocate device structure */
1486 rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
1488 if (rawdev == NULL) {
1489 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
1494 ipn3ke_bridge_func.get_ifpga_rawdev = ifpga_rawdev_get;
1495 ipn3ke_bridge_func.set_i40e_sw_dev = rte_pmd_i40e_set_switch_dev;
1497 dev = ifpga_rawdev_allocate(rawdev);
1499 IFPGA_RAWDEV_PMD_ERR("Unable to allocate ifpga_rawdevice");
1503 dev->aer_enable = 0;
1505 /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
1506 data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
1512 /* init opae_adapter_data_pci for device specific information */
1513 for (i = 0; i < PCI_MAX_RESOURCE; i++) {
1514 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
1515 data->region[i].len = pci_dev->mem_resource[i].len;
1516 data->region[i].addr = pci_dev->mem_resource[i].addr;
1518 data->device_id = pci_dev->id.device_id;
1519 data->vendor_id = pci_dev->id.vendor_id;
1520 data->bus = pci_dev->addr.bus;
1521 data->devid = pci_dev->addr.devid;
1522 data->function = pci_dev->addr.function;
1523 data->vfio_dev_fd = rte_intr_dev_fd_get(pci_dev->intr_handle);
1525 adapter = rawdev->dev_private;
1526 /* create a opae_adapter based on above device data */
1527 ret = opae_adapter_init(adapter, pci_dev->device.name, data);
1530 goto free_adapter_data;
1533 rawdev->dev_ops = &ifpga_rawdev_ops;
1534 rawdev->device = &pci_dev->device;
1535 rawdev->driver_name = pci_dev->driver->driver.name;
1537 /* must enumerate the adapter before use it */
1538 ret = opae_adapter_enumerate(adapter);
1540 goto free_adapter_data;
1542 /* get opae_manager to rawdev */
1543 mgr = opae_adapter_get_mgr(adapter);
1546 IFPGA_RAWDEV_PMD_INFO("this is a PF function");
1549 ret = ifpga_register_msix_irq(rawdev, 0, IFPGA_FME_IRQ, 0, 0,
1550 fme_interrupt_handler, "fme_irq", mgr);
1552 goto free_adapter_data;
1558 opae_adapter_data_free(data);
1561 rte_rawdev_pmd_release(rawdev);
1567 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
1570 struct rte_rawdev *rawdev;
1571 char name[RTE_RAWDEV_NAME_MAX_LEN];
1572 struct opae_adapter *adapter;
1573 struct opae_manager *mgr;
1574 struct ifpga_rawdev *dev;
1577 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1582 memset(name, 0, sizeof(name));
1583 snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, IFPGA_RAWDEV_NAME_FMT,
1584 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1586 IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
1587 name, rte_socket_id());
1589 rawdev = rte_rawdev_pmd_get_named_dev(name);
1591 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
1594 dev = ifpga_rawdev_get(rawdev);
1598 adapter = ifpga_rawdev_get_priv(rawdev);
1602 mgr = opae_adapter_get_mgr(adapter);
1606 if (ifpga_unregister_msix_irq(IFPGA_FME_IRQ, 0,
1607 fme_interrupt_handler, mgr) < 0)
1610 /* rte_rawdev_close is called by pmd_release */
1611 ret = rte_rawdev_pmd_release(rawdev);
1613 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
1619 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1620 struct rte_pci_device *pci_dev)
1622 IFPGA_RAWDEV_PMD_FUNC_TRACE();
1623 return ifpga_rawdev_create(pci_dev, rte_socket_id());
1627 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
1629 ifpga_monitor_stop_func();
1630 return ifpga_rawdev_destroy(pci_dev);
1633 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
1634 .id_table = pci_ifpga_map,
1635 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1636 .probe = ifpga_rawdev_pci_probe,
1637 .remove = ifpga_rawdev_pci_remove,
1640 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1641 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1642 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
1643 RTE_LOG_REGISTER_DEFAULT(ifpga_rawdev_logtype, NOTICE);
1645 static const char * const valid_args[] = {
1646 #define IFPGA_ARG_NAME "ifpga"
1648 #define IFPGA_ARG_PORT "port"
1650 #define IFPGA_AFU_BTS "afu_bts"
1655 static int ifpga_rawdev_get_string_arg(const char *key __rte_unused,
1656 const char *value, void *extra_args)
1659 if (!value || !extra_args)
1662 size = strlen(value) + 1;
1663 *(char **)extra_args = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
1664 if (!*(char **)extra_args)
1667 strlcpy(*(char **)extra_args, value, size);
1672 ifpga_cfg_probe(struct rte_vdev_device *dev)
1674 struct rte_devargs *devargs;
1675 struct rte_kvargs *kvlist = NULL;
1676 struct rte_rawdev *rawdev = NULL;
1677 struct ifpga_rawdev *ifpga_dev;
1681 char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1684 devargs = dev->device.devargs;
1686 kvlist = rte_kvargs_parse(devargs->args, valid_args);
1688 IFPGA_RAWDEV_PMD_LOG(ERR, "error when parsing param");
1692 if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
1693 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
1694 &ifpga_rawdev_get_string_arg,
1696 IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1701 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1706 if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
1707 if (rte_kvargs_process(kvlist,
1709 &rte_ifpga_get_integer32_arg,
1711 IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1716 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1721 memset(dev_name, 0, sizeof(dev_name));
1722 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", name);
1723 rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1726 ifpga_dev = ifpga_rawdev_get(rawdev);
1730 ifpga_rawdev_fill_info(ifpga_dev, bdf);
1732 ifpga_monitor_start_func();
1734 memset(dev_name, 0, sizeof(dev_name));
1735 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1738 ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
1739 dev_name, devargs->args);
1741 rte_kvargs_free(kvlist);
1748 ifpga_cfg_remove(struct rte_vdev_device *vdev)
1750 IFPGA_RAWDEV_PMD_INFO("Remove ifpga_cfg %p",
1756 static struct rte_vdev_driver ifpga_cfg_driver = {
1757 .probe = ifpga_cfg_probe,
1758 .remove = ifpga_cfg_remove,
1761 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
1762 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
1763 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,
1768 struct rte_pci_bus *ifpga_get_pci_bus(void)
1770 return rte_ifpga_rawdev_pmd.bus;
1773 int ifpga_rawdev_partial_reconfigure(struct rte_rawdev *dev, int port,
1777 IFPGA_RAWDEV_PMD_ERR("Input parameter is invalid");
1781 return rte_fpga_do_pr(dev, port, file);
1784 void ifpga_rawdev_cleanup(void)
1786 struct ifpga_rawdev *dev;
1789 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
1790 dev = &ifpga_rawdevices[i];
1792 rte_rawdev_pmd_release(dev->rawdev);