1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
5 #ifndef _IFPGA_DEFINES_H_
6 #define _IFPGA_DEFINES_H_
8 #include "ifpga_compat.h"
10 #define MAX_FPGA_PORT_NUM 4
12 #define FME_FEATURE_HEADER "fme_hdr"
13 #define FME_FEATURE_THERMAL_MGMT "fme_thermal"
14 #define FME_FEATURE_POWER_MGMT "fme_power"
15 #define FME_FEATURE_GLOBAL_IPERF "fme_iperf"
16 #define FME_FEATURE_GLOBAL_ERR "fme_error"
17 #define FME_FEATURE_PR_MGMT "fme_pr"
18 #define FME_FEATURE_EMIF_MGMT "fme_emif"
19 #define FME_FEATURE_HSSI_ETH "fme_hssi"
20 #define FME_FEATURE_GLOBAL_DPERF "fme_dperf"
21 #define FME_FEATURE_QSPI_FLASH "fme_qspi_flash"
22 #define FME_FEATURE_MAX10_SPI "fme_max10_spi"
23 #define FME_FEATURE_NIOS_SPI "fme_nios_spi"
25 #define PORT_FEATURE_HEADER "port_hdr"
26 #define PORT_FEATURE_UAFU "port_uafu"
27 #define PORT_FEATURE_ERR "port_err"
28 #define PORT_FEATURE_UMSG "port_umsg"
29 #define PORT_FEATURE_PR "port_pr"
30 #define PORT_FEATURE_UINT "port_uint"
31 #define PORT_FEATURE_STP "port_stp"
34 * do not check the revision id as id may be dynamic under
35 * some cases, e.g, UAFU.
37 #define SKIP_REVISION_CHECK 0xff
39 #define FME_HEADER_REVISION 1
40 #define FME_THERMAL_MGMT_REVISION 0
41 #define FME_POWER_MGMT_REVISION 1
42 #define FME_GLOBAL_IPERF_REVISION 1
43 #define FME_GLOBAL_ERR_REVISION 1
44 #define FME_PR_MGMT_REVISION 2
45 #define FME_HSSI_ETH_REVISION 0
46 #define FME_GLOBAL_DPERF_REVISION 0
47 #define FME_QSPI_REVISION 0
48 #define FME_MAX10_SPI 0
50 #define PORT_HEADER_REVISION 0
51 /* UAFU's header info depends on the downloaded GBS */
52 #define PORT_UAFU_REVISION SKIP_REVISION_CHECK
53 #define PORT_ERR_REVISION 1
54 #define PORT_UMSG_REVISION 0
55 #define PORT_UINT_REVISION 0
56 #define PORT_STP_REVISION 1
58 #define FEATURE_TYPE_AFU 0x1
59 #define FEATURE_TYPE_BBB 0x2
60 #define FEATURE_TYPE_PRIVATE 0x3
61 #define FEATURE_TYPE_FIU 0x4
63 #define FEATURE_FIU_ID_FME 0x0
64 #define FEATURE_FIU_ID_PORT 0x1
66 /* Reserved 0xfe for Header, 0xff for AFU*/
67 #define FEATURE_ID_FIU_HEADER 0xfe
68 #define FEATURE_ID_AFU 0xff
76 #define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
77 #define FME_FEATURE_ID_THERMAL_MGMT 0x1
78 #define FME_FEATURE_ID_POWER_MGMT 0x2
79 #define FME_FEATURE_ID_GLOBAL_IPERF 0x3
80 #define FME_FEATURE_ID_GLOBAL_ERR 0x4
81 #define FME_FEATURE_ID_PR_MGMT 0x5
82 #define FME_FEATURE_ID_HSSI_ETH 0x6
83 #define FME_FEATURE_ID_GLOBAL_DPERF 0x7
84 #define FME_FEATURE_ID_QSPI_FLASH 0x8
85 #define FME_FEATURE_ID_EMIF_MGMT 0x9
86 #define FME_FEATURE_ID_MAX10_SPI 0xe
87 #define FME_FEATURE_ID_NIOS_SPI 0xd
89 #define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
90 #define PORT_FEATURE_ID_ERROR 0x10
91 #define PORT_FEATURE_ID_UMSG 0x12
92 #define PORT_FEATURE_ID_UINT 0x13
93 #define PORT_FEATURE_ID_STP 0x14
94 #define PORT_FEATURE_ID_UAFU FEATURE_ID_AFU
97 * All headers and structures must be byte-packed to match the spec.
101 struct feature_header {
107 u32 next_header_offset:24;
115 struct feature_bbb_header {
119 struct feature_afu_header {
130 struct feature_fiu_header {
141 struct feature_fme_capability {
145 u8 fabric_verid; /* Fabric version ID */
146 u8 socket_id:1; /* Socket id */
147 u8 rsvd1:3; /* Reserved */
148 /* pci0 link available yes /no */
149 u8 pci0_link_avile:1;
150 /* pci1 link available yes /no */
151 u8 pci1_link_avile:1;
152 /* Coherent (QPI/UPI) link available yes /no */
154 u8 rsvd2:1; /* Reserved */
155 /* IOMMU or VT-d supported yes/no */
157 u8 num_ports:3; /* Number of ports */
158 u8 sf_fab_ctl:1; /* Internal validation bit */
159 u8 rsvd3:3; /* Reserved */
161 * Address width supported in bits
162 * BXT -0x26 , SKX -0x30
164 u8 address_width_bits:6;
165 u8 rsvd4:2; /* Reserved */
166 /* Size of cache supported in kb */
168 u8 cache_assoc:4; /* Cache Associativity */
169 u16 rsvd5:15; /* Reserved */
170 u8 lock_bit:1; /* Lock bit */
175 #define FME_AFU_ACCESS_PF 0
176 #define FME_AFU_ACCESS_VF 1
178 struct feature_fme_port {
186 u8 afu_access_control:1;
188 u8 port_implemented:1;
194 struct feature_fme_fab_status {
198 u8 upilink_status:4; /* UPI Link Status */
199 u8 rsvd1:4; /* Reserved */
200 u8 pci0link_status:1; /* pci0 link status */
201 u8 rsvd2:3; /* Reserved */
202 u8 pci1link_status:1; /* pci1 link status */
203 u64 rsvd3:51; /* Reserved */
208 struct feature_fme_genprotrange2_base {
212 u16 rsvd1; /* Reserved */
213 /* Base Address of memory range */
214 u8 protected_base_addrss:4;
215 u64 rsvd2:44; /* Reserved */
220 struct feature_fme_genprotrange2_limit {
224 u16 rsvd1; /* Reserved */
225 /* Limit Address of memory range */
226 u8 protected_limit_addrss:4;
227 u16 rsvd2:11; /* Reserved */
228 u8 enable:1; /* Enable GENPROTRANGE check */
229 u32 rsvd3; /* Reserved */
234 struct feature_fme_dxe_lock {
239 * Determines write access to the DXE region CSRs
240 * 1 - CSR region is locked;
241 * 0 - it is open for write access.
245 * Determines write access to the HSSI CSR
246 * 1 - CSR region is locked;
247 * 0 - it is open for write access.
255 #define HSSI_ID_NO_HASSI 0
256 #define HSSI_ID_PCIE_RP 1
257 #define HSSI_ID_ETHERNET 2
259 struct feature_fme_bitstream_id {
263 u32 gitrepo_hash:32; /* GIT repository hash */
265 * HSSI configuration identifier:
271 u16 rsvd1:12; /* Reserved */
272 /* Bitstream version patch number */
274 /* Bitstream version minor number */
276 /* Bitstream version major number */
278 /* Bitstream version debug number */
284 struct feature_fme_bitstream_md {
288 /* Seed number userd for synthesis flow */
290 /* Synthesis date(day number - 2 digits) */
292 /* Synthesis date(month number - 2 digits) */
294 /* Synthesis date(year number - 2 digits) */
296 u64 rsvd:36; /* Reserved */
301 struct feature_fme_iommu_ctrl {
305 /* Disables IOMMU prefetcher for C0 channel */
306 u8 prefetch_disableC0:1;
307 /* Disables IOMMU prefetcher for C1 channel */
308 u8 prefetch_disableC1:1;
309 /* Disables IOMMU partial cache line writes */
310 u8 prefetch_wrdisable:1;
311 u8 rsvd1:1; /* Reserved */
313 * Select counter and read value from register
314 * iommu_stat.dbg_counters
315 * 0 - Number of 4K page translation response
316 * 1 - Number of 2M page translation response
317 * 2 - Number of 1G page translation response
320 u32 rsvd2:26; /* Reserved */
321 /* Connected to IOMMU SIP Capabilities */
322 u32 capecap_defeature;
327 struct feature_fme_iommu_stat {
331 /* Translation Enable bit from IOMMU SIP */
332 u8 translation_enable:1;
333 /* Drain request in progress */
334 u8 drain_req_inprog:1;
335 /* Invalidation current state */
337 /* C0 Response Buffer current state */
338 u8 respbuffer_stateC0:3;
339 /* C1 Response Buffer current state */
340 u8 respbuffer_stateC1:3;
341 /* Last request ID to IOMMU SIP */
343 /* Last IOMMU SIP response ID value */
345 /* Last IOMMU SIP response status value */
346 u8 last_respstatus:3;
347 /* C0 Transaction Buffer is not empty */
348 u8 transbuf_notEmptyC0:1;
349 /* C1 Transaction Buffer is not empty */
350 u8 transbuf_notEmptyC1:1;
351 /* C0 Request FIFO is not empty */
352 u8 reqFIFO_notemptyC0:1;
353 /* C1 Request FIFO is not empty */
354 u8 reqFIFO_notemptyC1:1;
355 /* C0 Response FIFO is not empty */
356 u8 respFIFO_notemptyC0:1;
357 /* C1 Response FIFO is not empty */
358 u8 respFIFO_notemptyC1:1;
359 /* C0 Response FIFO overflow detected */
360 u8 respFIFO_overflowC0:1;
361 /* C1 Response FIFO overflow detected */
362 u8 respFIFO_overflowC1:1;
363 /* C0 Transaction Buffer overflow detected */
364 u8 tranbuf_overflowC0:1;
365 /* C1 Transaction Buffer overflow detected */
366 u8 tranbuf_overflowC1:1;
367 /* Request FIFO overflow detected */
368 u8 reqFIFO_overflow:1;
369 /* IOMMU memory read in progress */
371 /* IOMMU memory write in progress */
373 u8 rsvd1:1; /* Reserved */
374 /* Value of counter selected by iommu_ctl.counter_sel */
376 u16 rsvd2:12; /* Reserved */
381 struct feature_fme_pcie0_ctrl {
385 u64 vtd_bar_lock:1; /* Lock VT-D BAR register */
387 u64 rciep:1; /* Configure PCIE0 as RCiEP */
393 struct feature_fme_llpr_smrr_base {
398 u64 base:20; /* SMRR2 memory range base address */
404 struct feature_fme_llpr_smrr_mask {
409 u64 valid:1; /* LLPR_SMRR rule is valid or not */
411 * SMRR memory range mask which determines the range
412 * of region being mapped
420 struct feature_fme_llpr_smrr2_base {
425 u64 base:20; /* SMRR2 memory range base address */
431 struct feature_fme_llpr_smrr2_mask {
436 u64 valid:1; /* LLPR_SMRR2 rule is valid or not */
438 * SMRR2 memory range mask which determines the range
439 * of region being mapped
447 struct feature_fme_llpr_meseg_base {
451 /* A[45:19] of base address memory range */
458 struct feature_fme_llpr_meseg_limit {
462 /* A[45:19] of limit address memory range */
465 u64 enable:1; /* Enable LLPR MESEG rule */
471 struct feature_fme_header {
472 struct feature_header header;
473 struct feature_afu_header afu_header;
476 struct feature_fme_capability capability;
477 struct feature_fme_port port[MAX_FPGA_PORT_NUM];
478 struct feature_fme_fab_status fab_status;
479 struct feature_fme_bitstream_id bitstream_id;
480 struct feature_fme_bitstream_md bitstream_md;
481 struct feature_fme_genprotrange2_base genprotrange2_base;
482 struct feature_fme_genprotrange2_limit genprotrange2_limit;
483 struct feature_fme_dxe_lock dxe_lock;
484 struct feature_fme_iommu_ctrl iommu_ctrl;
485 struct feature_fme_iommu_stat iommu_stat;
486 struct feature_fme_pcie0_ctrl pcie0_control;
487 struct feature_fme_llpr_smrr_base smrr_base;
488 struct feature_fme_llpr_smrr_mask smrr_mask;
489 struct feature_fme_llpr_smrr2_base smrr2_base;
490 struct feature_fme_llpr_smrr2_mask smrr2_mask;
491 struct feature_fme_llpr_meseg_base meseg_base;
492 struct feature_fme_llpr_meseg_limit meseg_limit;
495 struct feature_port_capability {
499 u8 port_number:2; /* Port Number 0-3 */
500 u8 rsvd1:6; /* Reserved */
501 u16 mmio_size; /* User MMIO size in KB */
502 u8 rsvd2; /* Reserved */
503 u8 sp_intr_num:4; /* Supported interrupts num */
504 u32 rsvd3:28; /* Reserved */
509 struct feature_port_control {
513 u8 port_sftrst:1; /* Port Soft Reset */
514 u8 rsvd1:1; /* Reserved */
515 u8 latency_tolerance:1;/* '1' >= 40us, '0' < 40us */
516 u8 rsvd2:1; /* Reserved */
517 u8 port_sftrst_ack:1; /* HW ACK for Soft Reset */
518 u64 rsvd3:59; /* Reserved */
523 #define PORT_POWER_STATE_NORMAL 0
524 #define PORT_POWER_STATE_AP1 1
525 #define PORT_POWER_STATE_AP2 2
526 #define PORT_POWER_STATE_AP6 6
528 struct feature_port_status {
532 u8 port_freeze:1; /* '1' - freezed '0' - normal */
533 u8 rsvd1:7; /* Reserved */
534 u8 power_state:4; /* Power State */
535 u8 ap1_event:1; /* AP1 event was detected */
536 u8 ap2_event:1; /* AP2 event was detected */
537 u64 rsvd2:50; /* Reserved */
542 /* Port Header Register Set */
543 struct feature_port_header {
544 struct feature_header header;
545 struct feature_afu_header afu_header;
548 struct feature_port_capability capability;
549 struct feature_port_control control;
550 struct feature_port_status status;
552 u64 user_clk_freq_cmd0;
553 u64 user_clk_freq_cmd1;
554 u64 user_clk_freq_sts0;
555 u64 user_clk_freq_sts1;
558 struct feature_fme_tmp_threshold {
562 u8 tmp_thshold1:7; /* temperature Threshold 1 */
563 /* temperature Threshold 1 enable/disable */
564 u8 tmp_thshold1_enable:1;
565 u8 tmp_thshold2:7; /* temperature Threshold 2 */
566 /* temperature Threshold 2 enable /disable */
567 u8 tmp_thshold2_enable:1;
568 u8 pro_hot_setpoint:7; /* Proc Hot set point */
569 u8 rsvd4:1; /* Reserved */
570 u8 therm_trip_thshold:7; /* Thermeal Trip Threshold */
571 u8 rsvd3:1; /* Reserved */
572 u8 thshold1_status:1; /* Threshold 1 Status */
573 u8 thshold2_status:1; /* Threshold 2 Status */
574 u8 rsvd5:1; /* Reserved */
575 /* Thermeal Trip Threshold status */
576 u8 therm_trip_thshold_status:1;
577 u8 rsvd6:4; /* Reserved */
578 /* Validation mode- Force Proc Hot */
580 /* Validation mode - Therm trip Hot */
582 u8 rsvd2:2; /* Reserved */
583 u8 thshold_policy:1; /* threshold policy */
584 u32 rsvd:19; /* Reserved */
589 /* Temperature Sensor Read values format 1 */
590 struct feature_fme_temp_rdsensor_fmt1 {
594 /* Reads out FPGA temperature in celsius */
596 u8 rsvd0:1; /* Reserved */
597 /* Temperature reading sequence number */
598 u16 tmp_reading_seq_num;
599 /* Temperature reading is valid */
600 u8 tmp_reading_valid:1;
601 u8 rsvd1:7; /* Reserved */
602 u16 dbg_mode:10; /* Debug mode */
603 u32 rsvd2:22; /* Reserved */
608 /* Temperature sensor read values format 2 */
609 struct feature_fme_temp_rdsensor_fmt2 {
610 u64 rsvd; /* Reserved */
613 /* Temperature Threshold Capability Register */
614 struct feature_fme_tmp_threshold_cap {
618 /* Temperature Threshold Unsupported */
619 u8 tmp_thshold_disabled:1;
620 u64 rsvd:63; /* Reserved */
625 /* FME THERNAL FEATURE */
626 struct feature_fme_thermal {
627 struct feature_header header;
628 struct feature_fme_tmp_threshold threshold;
629 struct feature_fme_temp_rdsensor_fmt1 rdsensor_fm1;
630 struct feature_fme_temp_rdsensor_fmt2 rdsensor_fm2;
631 struct feature_fme_tmp_threshold_cap threshold_cap;
634 /* Power Status register */
635 struct feature_fme_pm_status {
639 /* FPGA Power consumed, The format is to be defined */
641 /* FPGA Latency Tolerance Reporting */
642 u8 fpga_latency_report:1;
643 u64 rsvd:45; /* Reserved */
649 struct feature_fme_pm_ap_threshold {
654 * Number of clocks (5ns period) for assertion
661 u8 threshold1_status:1;
662 u8 threshold2_status:1;
663 u64 rsvd3:46; /* Reserved */
668 /* Xeon Power Limit */
669 struct feature_fme_pm_xeon_limit {
673 /* Power limit in Watts in 12.3 format */
675 /* Indicates that power limit has been written */
677 /* 0 - Turbe range, 1 - Entire range */
679 /* Time constant in XXYYY format */
681 u64 rsvd:40; /* Reserved */
686 /* FPGA Power Limit */
687 struct feature_fme_pm_fpga_limit {
691 /* Power limit in Watts in 12.3 format */
693 /* Indicates that power limit has been written */
695 /* 0 - Turbe range, 1 - Entire range */
697 /* Time constant in XXYYY format */
699 u64 rsvd:40; /* Reserved */
704 /* FME POWER FEATURE */
705 struct feature_fme_power {
706 struct feature_header header;
707 struct feature_fme_pm_status status;
708 struct feature_fme_pm_ap_threshold threshold;
709 struct feature_fme_pm_xeon_limit xeon_limit;
710 struct feature_fme_pm_fpga_limit fpga_limit;
713 #define CACHE_CHANNEL_RD 0
714 #define CACHE_CHANNEL_WR 1
716 enum iperf_cache_events {
721 IPERF_CACHE_RSVD, /* reserved */
722 IPERF_CACHE_HOLD_REQ,
723 IPERF_CACHE_DATA_WR_PORT_CONTEN,
724 IPERF_CACHE_TAG_WR_PORT_CONTEN,
725 IPERF_CACHE_TX_REQ_STALL,
726 IPERF_CACHE_RX_REQ_STALL,
727 IPERF_CACHE_EVICTIONS,
730 /* FPMON Cache Control */
731 struct feature_fme_ifpmon_ch_ctl {
735 u8 reset_counters:1; /* Reset Counters */
736 u8 rsvd1:7; /* Reserved */
737 u8 freeze:1; /* Freeze if set to 1 */
738 u8 rsvd2:7; /* Reserved */
739 u8 cache_event:4; /* Select the cache event */
740 u8 cci_chsel:1; /* Select the channel */
741 u64 rsvd3:43; /* Reserved */
746 /* FPMON Cache Counter */
747 struct feature_fme_ifpmon_ch_ctr {
751 /* Cache Counter for even addresse */
752 u64 cache_counter:48;
753 u16 rsvd:12; /* Reserved */
754 /* Cache Event being reported */
760 enum iperf_fab_events {
771 #define FAB_DISABLE_FILTER 0
772 #define FAB_ENABLE_FILTER 1
774 /* FPMON FAB Control */
775 struct feature_fme_ifpmon_fab_ctl {
779 u8 reset_counters:1; /* Reset Counters */
780 u8 rsvd:7; /* Reserved */
781 u8 freeze:1; /* Set to 1 frozen counter */
782 u8 rsvd1:7; /* Reserved */
783 u8 fab_evtcode:4; /* Fabric Event Code */
784 u8 port_id:2; /* Port ID */
785 u8 rsvd2:1; /* Reserved */
786 u8 port_filter:1; /* Port Filter */
787 u64 rsvd3:40; /* Reserved */
792 /* FPMON Event Counter */
793 struct feature_fme_ifpmon_fab_ctr {
797 u64 fab_cnt:60; /* Fabric event counter */
798 /* Fabric event code being reported */
804 /* FPMON Clock Counter */
805 struct feature_fme_ifpmon_clk_ctr {
806 u64 afu_interf_clock; /* Clk_16UI (AFU clock) counter. */
809 enum iperf_vtd_events {
810 IPERF_VTD_AFU_MEM_RD_TRANS,
811 IPERF_VTD_AFU_MEM_WR_TRANS,
812 IPERF_VTD_AFU_DEVTLB_RD_HIT,
813 IPERF_VTD_AFU_DEVTLB_WR_HIT,
814 IPERF_VTD_DEVTLB_4K_FILL,
815 IPERF_VTD_DEVTLB_2M_FILL,
816 IPERF_VTD_DEVTLB_1G_FILL,
819 /* VT-d control register */
820 struct feature_fme_ifpmon_vtd_ctl {
824 u8 reset_counters:1; /* Reset Counters */
825 u8 rsvd:7; /* Reserved */
826 u8 freeze:1; /* Set to 1 frozen counter */
827 u8 rsvd1:7; /* Reserved */
828 u8 vtd_evtcode:4; /* VTd and TLB event code */
829 u64 rsvd2:44; /* Reserved */
834 /* VT-d event counter */
835 struct feature_fme_ifpmon_vtd_ctr {
839 u64 vtd_counter:48; /* VTd event counter */
840 u16 rsvd:12; /* Reserved */
841 u8 event_code:4; /* VTd event code */
846 enum iperf_vtd_sip_events {
847 IPERF_VTD_SIP_IOTLB_4K_HIT,
848 IPERF_VTD_SIP_IOTLB_2M_HIT,
849 IPERF_VTD_SIP_IOTLB_1G_HIT,
850 IPERF_VTD_SIP_SLPWC_L3_HIT,
851 IPERF_VTD_SIP_SLPWC_L4_HIT,
852 IPERF_VTD_SIP_RCC_HIT,
853 IPERF_VTD_SIP_IOTLB_4K_MISS,
854 IPERF_VTD_SIP_IOTLB_2M_MISS,
855 IPERF_VTD_SIP_IOTLB_1G_MISS,
856 IPERF_VTD_SIP_SLPWC_L3_MISS,
857 IPERF_VTD_SIP_SLPWC_L4_MISS,
858 IPERF_VTD_SIP_RCC_MISS,
861 /* VT-d SIP control register */
862 struct feature_fme_ifpmon_vtd_sip_ctl {
866 u8 reset_counters:1; /* Reset Counters */
867 u8 rsvd:7; /* Reserved */
868 u8 freeze:1; /* Set to 1 frozen counter */
869 u8 rsvd1:7; /* Reserved */
870 u8 vtd_evtcode:4; /* VTd and TLB event code */
871 u64 rsvd2:44; /* Reserved */
876 /* VT-d SIP event counter */
877 struct feature_fme_ifpmon_vtd_sip_ctr {
881 u64 vtd_counter:48; /* VTd event counter */
882 u16 rsvd:12; /* Reserved */
883 u8 event_code:4; /* VTd event code */
888 /* FME IPERF FEATURE */
889 struct feature_fme_iperf {
890 struct feature_header header;
891 struct feature_fme_ifpmon_ch_ctl ch_ctl;
892 struct feature_fme_ifpmon_ch_ctr ch_ctr0;
893 struct feature_fme_ifpmon_ch_ctr ch_ctr1;
894 struct feature_fme_ifpmon_fab_ctl fab_ctl;
895 struct feature_fme_ifpmon_fab_ctr fab_ctr;
896 struct feature_fme_ifpmon_clk_ctr clk;
897 struct feature_fme_ifpmon_vtd_ctl vtd_ctl;
898 struct feature_fme_ifpmon_vtd_ctr vtd_ctr;
899 struct feature_fme_ifpmon_vtd_sip_ctl vtd_sip_ctl;
900 struct feature_fme_ifpmon_vtd_sip_ctr vtd_sip_ctr;
903 enum dperf_fab_events {
906 DPERF_FAB_MMIO_RD = 6,
910 /* FPMON FAB Control */
911 struct feature_fme_dfpmon_fab_ctl {
915 u8 reset_counters:1; /* Reset Counters */
916 u8 rsvd:7; /* Reserved */
917 u8 freeze:1; /* Set to 1 frozen counter */
918 u8 rsvd1:7; /* Reserved */
919 u8 fab_evtcode:4; /* Fabric Event Code */
920 u8 port_id:2; /* Port ID */
921 u8 rsvd2:1; /* Reserved */
922 u8 port_filter:1; /* Port Filter */
923 u64 rsvd3:40; /* Reserved */
928 /* FPMON Event Counter */
929 struct feature_fme_dfpmon_fab_ctr {
933 u64 fab_cnt:60; /* Fabric event counter */
934 /* Fabric event code being reported */
940 /* FPMON Clock Counter */
941 struct feature_fme_dfpmon_clk_ctr {
942 u64 afu_interf_clock; /* Clk_16UI (AFU clock) counter. */
945 /* FME DPERF FEATURE */
946 struct feature_fme_dperf {
947 struct feature_header header;
949 struct feature_fme_dfpmon_fab_ctl fab_ctl;
950 struct feature_fme_dfpmon_fab_ctr fab_ctr;
951 struct feature_fme_dfpmon_clk_ctr clk;
954 struct feature_fme_error0 {
955 #define FME_ERROR0_MASK 0xFFUL
956 #define FME_ERROR0_MASK_DEFAULT 0x40UL /* pcode workaround */
960 u8 fabric_err:1; /* Fabric error */
961 u8 fabfifo_overflow:1; /* Fabric fifo overflow */
962 u8 kticdc_parity_err:2;/* KTI CDC Parity Error */
963 u8 iommu_parity_err:1; /* IOMMU Parity error */
964 /* AFU PF/VF access mismatch detected */
965 u8 afu_acc_mode_err:1;
966 u8 mbp_err:1; /* Indicates an MBP event */
967 /* PCIE0 CDC Parity Error */
968 u8 pcie0cdc_parity_err:5;
969 /* PCIE1 CDC Parity Error */
970 u8 pcie1cdc_parity_err:5;
971 /* CVL CDC Parity Error */
972 u8 cvlcdc_parity_err:3;
973 u64 rsvd:44; /* Reserved */
978 /* PCIe0 Error Status register */
979 struct feature_fme_pcie0_error {
980 #define FME_PCIE0_ERROR_MASK 0xFFUL
984 u8 formattype_err:1; /* TLP format/type error */
985 u8 MWAddr_err:1; /* TLP MW address error */
986 u8 MWAddrLength_err:1; /* TLP MW length error */
987 u8 MRAddr_err:1; /* TLP MR address error */
988 u8 MRAddrLength_err:1; /* TLP MR length error */
989 u8 cpl_tag_err:1; /* TLP CPL tag error */
990 u8 cpl_status_err:1; /* TLP CPL status error */
991 u8 cpl_timeout_err:1; /* TLP CPL timeout */
992 u8 cci_parity_err:1; /* CCI bridge parity error */
993 u8 rxpoison_tlp_err:1; /* Received a TLP with EP set */
994 u64 rsvd:52; /* Reserved */
995 u8 vfnumb_err:1; /* Number of error VF */
996 u8 funct_type_err:1; /* Virtual (1) or Physical */
1001 /* PCIe1 Error Status register */
1002 struct feature_fme_pcie1_error {
1003 #define FME_PCIE1_ERROR_MASK 0xFFUL
1007 u8 formattype_err:1; /* TLP format/type error */
1008 u8 MWAddr_err:1; /* TLP MW address error */
1009 u8 MWAddrLength_err:1; /* TLP MW length error */
1010 u8 MRAddr_err:1; /* TLP MR address error */
1011 u8 MRAddrLength_err:1; /* TLP MR length error */
1012 u8 cpl_tag_err:1; /* TLP CPL tag error */
1013 u8 cpl_status_err:1; /* TLP CPL status error */
1014 u8 cpl_timeout_err:1; /* TLP CPL timeout */
1015 u8 cci_parity_err:1; /* CCI bridge parity error */
1016 u8 rxpoison_tlp_err:1; /* Received a TLP with EP set */
1017 u64 rsvd:54; /* Reserved */
1022 /* FME First Error register */
1023 struct feature_fme_first_error {
1024 #define FME_FIRST_ERROR_MASK ((1ULL << 60) - 1)
1029 * Indicates the Error Register that was
1032 u64 err_reg_status:60;
1034 * Holds 60 LSBs from the Error register that was
1042 /* FME Next Error register */
1043 struct feature_fme_next_error {
1044 #define FME_NEXT_ERROR_MASK ((1ULL << 60) - 1)
1049 * Indicates the Error Register that was
1052 u64 err_reg_status:60;
1054 * Holds 60 LSBs from the Error register that was
1062 /* RAS Non Fatal Error Status register */
1063 struct feature_fme_ras_nonfaterror {
1067 /* thremal threshold AP1 */
1068 u8 temp_thresh_ap1:1;
1069 /* thremal threshold AP2 */
1070 u8 temp_thresh_ap2:1;
1071 u8 pcie_error:1; /* pcie Error */
1072 u8 portfatal_error:1; /* port fatal error */
1073 u8 proc_hot:1; /* Indicates a ProcHot event */
1074 /* Indicates an AFU PF/VF access mismatch */
1075 u8 afu_acc_mode_err:1;
1076 /* Injected nonfata Error */
1077 u8 injected_nonfata_err:1;
1079 /* Temperature threshold triggered AP6*/
1080 u8 temp_thresh_AP6:1;
1081 /* Power threshold triggered AP1 */
1082 u8 power_thresh_AP1:1;
1083 /* Power threshold triggered AP2 */
1084 u8 power_thresh_AP2:1;
1085 /* Indicates a MBP event */
1087 u64 rsvd2:51; /* Reserved */
1092 /* RAS Catastrophic Fatal Error Status register */
1093 struct feature_fme_ras_catfaterror {
1097 /* KTI Link layer error detected */
1098 u8 ktilink_fatal_err:1;
1099 /* tag-n-cache error detected */
1100 u8 tagcch_fatal_err:1;
1101 /* CCI error detected */
1103 /* KTI Protocol error detected */
1104 u8 ktiprpto_fatal_err:1;
1105 /* Fatal DRAM error detected */
1106 u8 dram_fatal_err:1;
1107 /* IOMMU detected */
1108 u8 iommu_fatal_err:1;
1109 /* Fabric Fatal Error */
1110 u8 fabric_fatal_err:1;
1111 /* PCIe possion Error */
1112 u8 pcie_poison_err:1;
1113 /* Injected fatal Error */
1114 u8 inject_fata_err:1;
1115 /* Catastrophic CRC Error */
1116 u8 crc_catast_err:1;
1117 /* Catastrophic Thermal Error */
1118 u8 therm_catast_err:1;
1119 /* Injected Catastrophic Error */
1120 u8 injected_catast_err:1;
1126 /* RAS Error injection register */
1127 struct feature_fme_ras_error_inj {
1128 #define FME_RAS_ERROR_INJ_MASK 0x7UL
1132 u8 catast_error:1; /* Catastrophic error flag */
1133 u8 fatal_error:1; /* Fatal error flag */
1134 u8 nonfatal_error:1; /* NonFatal error flag */
1135 u64 rsvd:61; /* Reserved */
1140 /* FME error capabilities */
1141 struct feature_fme_error_capability {
1146 /* MSI-X vector table entry number */
1147 u16 intr_vector_num:12;
1148 u64 rsvd:51; /* Reserved */
1153 /* FME ERR FEATURE */
1154 struct feature_fme_err {
1155 struct feature_header header;
1156 struct feature_fme_error0 fme_err_mask;
1157 struct feature_fme_error0 fme_err;
1158 struct feature_fme_pcie0_error pcie0_err_mask;
1159 struct feature_fme_pcie0_error pcie0_err;
1160 struct feature_fme_pcie1_error pcie1_err_mask;
1161 struct feature_fme_pcie1_error pcie1_err;
1162 struct feature_fme_first_error fme_first_err;
1163 struct feature_fme_next_error fme_next_err;
1164 struct feature_fme_ras_nonfaterror ras_nonfat_mask;
1165 struct feature_fme_ras_nonfaterror ras_nonfaterr;
1166 struct feature_fme_ras_catfaterror ras_catfat_mask;
1167 struct feature_fme_ras_catfaterror ras_catfaterr;
1168 struct feature_fme_ras_error_inj ras_error_inj;
1169 struct feature_fme_error_capability fme_err_capability;
1172 /* FME Partial Reconfiguration Control */
1173 struct feature_fme_pr_ctl {
1177 u8 pr_reset:1; /* Reset PR Engine */
1178 u8 rsvd3:3; /* Reserved */
1179 u8 pr_reset_ack:1; /* Reset PR Engine Ack */
1180 u8 rsvd4:3; /* Reserved */
1181 u8 pr_regionid:2; /* PR Region ID */
1182 u8 rsvd1:2; /* Reserved */
1183 u8 pr_start_req:1; /* PR Start Request */
1184 u8 pr_push_complete:1; /* PR Data push complete */
1185 u8 pr_kind:1; /* PR Data push complete */
1186 u32 rsvd:17; /* Reserved */
1187 u32 config_data; /* Config data TBD */
1192 /* FME Partial Reconfiguration Status */
1193 struct feature_fme_pr_status {
1197 u16 pr_credit:9; /* PR Credits */
1198 u8 rsvd2:7; /* Reserved */
1199 u8 pr_status:1; /* PR status */
1200 u8 rsvd:3; /* Reserved */
1201 /* Altra PR Controller Block status */
1202 u8 pr_controller_status:3;
1203 u8 rsvd1:1; /* Reserved */
1204 u8 pr_host_status:4; /* PR Host status */
1205 u8 rsvd3:4; /* Reserved */
1206 /* Security Block Status fields (TBD) */
1207 u32 security_bstatus;
1212 /* FME Partial Reconfiguration Data */
1213 struct feature_fme_pr_data {
1215 u64 csr; /* PR data from the raw-binary file */
1217 /* PR data from the raw-binary file */
1224 /* FME PR Public Key */
1225 struct feature_fme_pr_key {
1226 u64 key; /* FME PR Public Hash */
1229 /* FME PR FEATURE */
1230 struct feature_fme_pr {
1231 struct feature_header header;
1232 /*Partial Reconfiguration control */
1233 struct feature_fme_pr_ctl ccip_fme_pr_control;
1235 /* Partial Reconfiguration Status */
1236 struct feature_fme_pr_status ccip_fme_pr_status;
1238 /* Partial Reconfiguration data */
1239 struct feature_fme_pr_data ccip_fme_pr_data;
1241 /* Partial Reconfiguration data */
1242 u64 ccip_fme_pr_err;
1246 /* Partial Reconfiguration data registers */
1258 /* PR Interface ID */
1259 u64 fme_pr_intfc_id_l;
1260 u64 fme_pr_intfc_id_h;
1262 /* MSIX filed to be Added */
1265 /* FME HSSI Control */
1266 struct feature_fme_hssi_eth_ctrl {
1270 u32 data:32; /* HSSI data */
1271 u16 address:16; /* HSSI address */
1275 * 0x08 - SW register RD request
1276 * 0x10 - SW register WR request
1277 * 0x40 - Auxiliar bus RD request
1278 * 0x80 - Auxiliar bus WR request
1285 /* FME HSSI Status */
1286 struct feature_fme_hssi_eth_stat {
1290 u32 data:32; /* HSSI data */
1291 u8 acknowledge:1; /* HSSI acknowledge */
1292 u8 spare:1; /* HSSI spare */
1293 u32 rsvd:30; /* Reserved */
1298 /* FME HSSI FEATURE */
1299 struct feature_fme_hssi {
1300 struct feature_header header;
1301 struct feature_fme_hssi_eth_ctrl hssi_control;
1302 struct feature_fme_hssi_eth_stat hssi_status;
1305 #define PORT_ERR_MASK 0xfff0703ff001f
1306 struct feature_port_err_key {
1310 /* Tx Channel0: Overflow */
1311 u8 tx_ch0_overflow:1;
1312 /* Tx Channel0: Invalid request encoding */
1313 u8 tx_ch0_invaldreq :1;
1314 /* Tx Channel0: Request with cl_len=3 not supported */
1315 u8 tx_ch0_cl_len3:1;
1316 /* Tx Channel0: Request with cl_len=2 not aligned 2CL */
1317 u8 tx_ch0_cl_len2:1;
1318 /* Tx Channel0: Request with cl_len=4 not aligned 4CL */
1319 u8 tx_ch0_cl_len4:1;
1321 u16 rsvd1:4; /* Reserved */
1323 /* AFU MMIO RD received while PORT is in reset */
1324 u8 mmio_rd_whilerst:1;
1325 /* AFU MMIO WR received while PORT is in reset */
1326 u8 mmio_wr_whilerst:1;
1328 u16 rsvd2:5; /* Reserved */
1330 /* Tx Channel1: Overflow */
1331 u8 tx_ch1_overflow:1;
1332 /* Tx Channel1: Invalid request encoding */
1333 u8 tx_ch1_invaldreq:1;
1334 /* Tx Channel1: Request with cl_len=3 not supported */
1335 u8 tx_ch1_cl_len3:1;
1336 /* Tx Channel1: Request with cl_len=2 not aligned 2CL */
1337 u8 tx_ch1_cl_len2:1;
1338 /* Tx Channel1: Request with cl_len=4 not aligned 4CL */
1339 u8 tx_ch1_cl_len4:1;
1341 /* Tx Channel1: Insufficient data payload */
1342 u8 tx_ch1_insuff_data:1;
1343 /* Tx Channel1: Data payload overrun */
1344 u8 tx_ch1_data_overrun:1;
1345 /* Tx Channel1 : Incorrect address */
1346 u8 tx_ch1_incorr_addr:1;
1347 /* Tx Channel1 : NON-Zero SOP Detected */
1349 /* Tx Channel1 : Illegal VC_SEL, atomic request VLO */
1350 u8 tx_ch1_illegal_vcsel:1;
1352 u8 rsvd3:6; /* Reserved */
1354 /* MMIO Read Timeout in AFU */
1355 u8 mmioread_timeout:1;
1357 /* Tx Channel2: FIFO Overflow */
1358 u8 tx_ch2_fifo_overflow:1;
1360 /* MMIO read is not matching pending request */
1361 u8 unexp_mmio_resp:1;
1363 u8 rsvd4:5; /* Reserved */
1365 /* Number of pending Requests: counter overflow */
1366 u8 tx_req_counter_overflow:1;
1367 /* Req with Address violating SMM Range */
1369 /* Req with Address violating second SMM Range */
1370 u8 llpr_smrr2_err:1;
1371 /* Req with Address violating ME Stolen message */
1373 /* Req with Address violating Generic Protected Range */
1374 u8 genprot_range_err:1;
1375 /* Req with Address violating Legacy Range low */
1376 u8 legrange_low_err:1;
1377 /* Req with Address violating Legacy Range High */
1378 u8 legrange_high_err:1;
1379 /* Req with Address violating VGA memory range */
1380 u8 vgmem_range_err:1;
1381 u8 page_fault_err:1; /* Page fault */
1382 u8 pmr_err:1; /* PMR Error */
1383 u8 ap6_event:1; /* AP6 event */
1384 /* VF FLR detected on Port with PF access control */
1385 u8 vfflr_access_err:1;
1386 u16 rsvd5:12; /* Reserved */
1391 /* Port first error register, not contain all error bits in error register. */
1392 struct feature_port_first_err_key {
1396 u8 tx_ch0_overflow:1;
1397 u8 tx_ch0_invaldreq :1;
1398 u8 tx_ch0_cl_len3:1;
1399 u8 tx_ch0_cl_len2:1;
1400 u8 tx_ch0_cl_len4:1;
1401 u8 rsvd1:4; /* Reserved */
1402 u8 mmio_rd_whilerst:1;
1403 u8 mmio_wr_whilerst:1;
1404 u8 rsvd2:5; /* Reserved */
1405 u8 tx_ch1_overflow:1;
1406 u8 tx_ch1_invaldreq:1;
1407 u8 tx_ch1_cl_len3:1;
1408 u8 tx_ch1_cl_len2:1;
1409 u8 tx_ch1_cl_len4:1;
1410 u8 tx_ch1_insuff_data:1;
1411 u8 tx_ch1_data_overrun:1;
1412 u8 tx_ch1_incorr_addr:1;
1414 u8 tx_ch1_illegal_vcsel:1;
1415 u8 rsvd3:6; /* Reserved */
1416 u8 mmioread_timeout:1;
1417 u8 tx_ch2_fifo_overflow:1;
1418 u8 rsvd4:6; /* Reserved */
1419 u8 tx_req_counter_overflow:1;
1420 u32 rsvd5:23; /* Reserved */
1425 /* Port malformed Req0 */
1426 struct feature_port_malformed_req0 {
1430 /* Port malformed Req1 */
1431 struct feature_port_malformed_req1 {
1435 /* Port debug register */
1436 struct feature_port_debug {
1440 /* Port error capabilities */
1441 struct feature_port_err_capability {
1446 /* MSI-X vector table entry number */
1447 u16 intr_vector_num:12;
1448 u64 rsvd:51; /* Reserved */
1453 /* PORT FEATURE ERROR */
1454 struct feature_port_error {
1455 struct feature_header header;
1456 struct feature_port_err_key error_mask;
1457 struct feature_port_err_key port_error;
1458 struct feature_port_first_err_key port_first_error;
1459 struct feature_port_malformed_req0 malreq0;
1460 struct feature_port_malformed_req1 malreq1;
1461 struct feature_port_debug port_debug;
1462 struct feature_port_err_capability error_capability;
1465 /* Port UMSG Capability */
1466 struct feature_port_umsg_cap {
1470 /* Number of umsg allocated to this port */
1472 /* Enable / Disable UMsg engine for this port */
1474 /* Usmg initialization status */
1475 u8 umsg_init_complete:1;
1476 /* IOMMU can not translate the umsg base address */
1477 u8 umsg_trans_error:1;
1478 u64 rsvd:53; /* Reserved */
1483 /* Port UMSG base address */
1484 struct feature_port_umsg_baseaddr {
1488 u64 base_addr:48; /* 48 bit physical address */
1489 u16 rsvd; /* Reserved */
1494 struct feature_port_umsg_mode {
1498 u32 umsg_hint_enable; /* UMSG hint enable/disable */
1499 u32 rsvd; /* Reserved */
1504 /* PORT FEATURE UMSG */
1505 struct feature_port_umsg {
1506 struct feature_header header;
1507 struct feature_port_umsg_cap capability;
1508 struct feature_port_umsg_baseaddr baseaddr;
1509 struct feature_port_umsg_mode mode;
1512 #define UMSG_EN_POLL_INVL 10 /* us */
1513 #define UMSG_EN_POLL_TIMEOUT 1000 /* us */
1515 /* Port UINT Capability */
1516 struct feature_port_uint_cap {
1520 u16 intr_num:12; /* Supported interrupts num */
1521 /* First MSI-X vector table entry number */
1522 u16 first_vec_num:12;
1528 /* PORT FEATURE UINT */
1529 struct feature_port_uint {
1530 struct feature_header header;
1531 struct feature_port_uint_cap capability;
1534 /* STP region supports mmap operation, so use page aligned size. */
1535 #define PORT_FEATURE_STP_REGION_SIZE \
1536 IFPGA_PAGE_ALIGN(sizeof(struct feature_port_stp))
1538 /* Port STP status register (for debug only)*/
1539 struct feature_port_stp_status {
1543 /* SLD Hub end-point read/write timeout */
1544 u8 sld_ep_timeout:1;
1545 /* Remote STP in reset/disable */
1547 u8 unsupported_read:1;
1548 /* MMIO timeout detected and faked with a response */
1552 u8 txfifo_overflow:1;
1553 u8 txfifo_underflow:1;
1554 u8 rxfifo_overflow:1;
1555 u8 rxfifo_underflow:1;
1556 /* Number of MMIO write requests */
1558 /* Number of MMIO read requests */
1560 /* Number of MMIO read responses */
1568 * Most registers in STP region are not touched by driver, but mmapped to user
1569 * space. So they are not defined in below data structure, as its actual size
1570 * is 0x18c per spec.
1572 struct feature_port_stp {
1573 struct feature_header header;
1574 struct feature_port_stp_status stp_status;
1578 * enum fpga_pr_states - fpga PR states
1579 * @FPGA_PR_STATE_UNKNOWN: can't determine state
1580 * @FPGA_PR_STATE_WRITE_INIT: preparing FPGA for programming
1581 * @FPGA_PR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage
1582 * @FPGA_PR_STATE_WRITE: writing image to FPGA
1583 * @FPGA_PR_STATE_WRITE_ERR: Error while writing FPGA
1584 * @FPGA_PR_STATE_WRITE_COMPLETE: Doing post programming steps
1585 * @FPGA_PR_STATE_WRITE_COMPLETE_ERR: Error during WRITE_COMPLETE
1586 * @FPGA_PR_STATE_OPERATING: FPGA PR done
1588 enum fpga_pr_states {
1589 /* canot determine state states */
1590 FPGA_PR_STATE_UNKNOWN,
1592 /* write sequence: init, write, complete */
1593 FPGA_PR_STATE_WRITE_INIT,
1594 FPGA_PR_STATE_WRITE_INIT_ERR,
1595 FPGA_PR_STATE_WRITE,
1596 FPGA_PR_STATE_WRITE_ERR,
1597 FPGA_PR_STATE_WRITE_COMPLETE,
1598 FPGA_PR_STATE_WRITE_COMPLETE_ERR,
1605 * FPGA Manager flags
1606 * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported
1608 #define FPGA_MGR_PARTIAL_RECONFIG BIT(0)
1611 * struct fpga_pr_info - specific information to a FPGA PR
1612 * @flags: boolean flags as defined above
1613 * @pr_err: PR error code
1614 * @state: fpga manager state
1617 struct fpga_pr_info {
1620 enum fpga_pr_states state;
1624 #define DEFINE_FPGA_PR_ERR_MSG(_name_) \
1625 static const char * const _name_[] = { \
1626 "PR operation error detected", \
1627 "PR CRC error detected", \
1628 "PR incompatiable bitstream error detected", \
1629 "PR IP protocol error detected", \
1630 "PR FIFO overflow error detected", \
1631 "PR timeout error detected", \
1632 "PR secure load error detected", \
1635 #define RST_POLL_INVL 10 /* us */
1636 #define RST_POLL_TIMEOUT 1000 /* us */
1638 #define PR_WAIT_TIMEOUT 15000000
1640 #define PR_HOST_STATUS_IDLE 0
1641 #define PR_MAX_ERR_NUM 7
1643 DEFINE_FPGA_PR_ERR_MSG(pr_err_msg);
1646 * green bitstream header must be byte-packed to match the
1655 #define GBS_GUID_H 0x414750466e6f6558
1656 #define GBS_GUID_L 0x31303076534247b7
1657 #define is_valid_bts(bts_hdr) \
1658 (((bts_hdr)->guid_h == GBS_GUID_H) && \
1659 ((bts_hdr)->guid_l == GBS_GUID_L))
1662 #endif /* _BASE_IFPGA_DEFINES_H_ */