drivers/raw/ifpga_rawdev/base/ifpga_defines.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2018 Intel Corporation
   3  */
   4
   5 #ifndef _IFPGA_DEFINES_H_
   6 #define _IFPGA_DEFINES_H_
   7
   8 #include "ifpga_compat.h"
   9
  10 #define MAX_FPGA_PORT_NUM  4
  11
  12 #define FME_FEATURE_HEADER          "fme_hdr"
  13 #define FME_FEATURE_THERMAL_MGMT    "fme_thermal"
  14 #define FME_FEATURE_POWER_MGMT      "fme_power"
  15 #define FME_FEATURE_GLOBAL_IPERF    "fme_iperf"
  16 #define FME_FEATURE_GLOBAL_ERR      "fme_error"
  17 #define FME_FEATURE_PR_MGMT         "fme_pr"
  18 #define FME_FEATURE_EMIF_MGMT       "fme_emif"
  19 #define FME_FEATURE_HSSI_ETH        "fme_hssi"
  20 #define FME_FEATURE_GLOBAL_DPERF    "fme_dperf"
  21 #define FME_FEATURE_QSPI_FLASH      "fme_qspi_flash"
  22 #define FME_FEATURE_MAX10_SPI       "fme_max10_spi"
  23 #define FME_FEATURE_NIOS_SPI        "fme_nios_spi"
  24 #define FME_FEATURE_I2C_MASTER      "fme_i2c_master"
  25
  26 #define PORT_FEATURE_HEADER         "port_hdr"
  27 #define PORT_FEATURE_UAFU           "port_uafu"
  28 #define PORT_FEATURE_ERR            "port_err"
  29 #define PORT_FEATURE_UMSG           "port_umsg"
  30 #define PORT_FEATURE_PR             "port_pr"
  31 #define PORT_FEATURE_UINT           "port_uint"
  32 #define PORT_FEATURE_STP            "port_stp"
  33
  34 /*
  35  * do not check the revision id as id may be dynamic under
  36  * some cases, e.g, UAFU.
  37  */
  38 #define SKIP_REVISION_CHECK             0xff
  39
  40 #define FME_HEADER_REVISION             1
  41 #define FME_THERMAL_MGMT_REVISION       0
  42 #define FME_POWER_MGMT_REVISION         1
  43 #define FME_GLOBAL_IPERF_REVISION       1
  44 #define FME_GLOBAL_ERR_REVISION         1
  45 #define FME_PR_MGMT_REVISION            2
  46 #define FME_HSSI_ETH_REVISION           0
  47 #define FME_GLOBAL_DPERF_REVISION       0
  48 #define FME_QSPI_REVISION               0
  49 #define FME_MAX10_SPI                   0
  50 #define FME_I2C_MASTER                  0
  51
  52 #define PORT_HEADER_REVISION            0
  53 /* UAFU's header info depends on the downloaded GBS */
  54 #define PORT_UAFU_REVISION              SKIP_REVISION_CHECK
  55 #define PORT_ERR_REVISION               1
  56 #define PORT_UMSG_REVISION              0
  57 #define PORT_UINT_REVISION              0
  58 #define PORT_STP_REVISION               1
  59
  60 #define FEATURE_TYPE_AFU        0x1
  61 #define FEATURE_TYPE_BBB        0x2
  62 #define FEATURE_TYPE_PRIVATE    0x3
  63 #define FEATURE_TYPE_FIU        0x4
  64
  65 #define FEATURE_FIU_ID_FME      0x0
  66 #define FEATURE_FIU_ID_PORT     0x1
  67
  68 /* Reserved 0xfe for Header, 0xff for AFU*/
  69 #define FEATURE_ID_FIU_HEADER   0xfe
  70 #define FEATURE_ID_AFU          0xff
  71
  72 enum fpga_id_type {
  73         FME_ID,
  74         PORT_ID,
  75         FPGA_ID_MAX,
  76 };
  77
  78 #define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
  79 #define FME_FEATURE_ID_THERMAL_MGMT 0x1
  80 #define FME_FEATURE_ID_POWER_MGMT 0x2
  81 #define FME_FEATURE_ID_GLOBAL_IPERF 0x3
  82 #define FME_FEATURE_ID_GLOBAL_ERR 0x4
  83 #define FME_FEATURE_ID_PR_MGMT 0x5
  84 #define FME_FEATURE_ID_HSSI_ETH 0x6
  85 #define FME_FEATURE_ID_GLOBAL_DPERF 0x7
  86 #define FME_FEATURE_ID_QSPI_FLASH 0x8
  87 #define FME_FEATURE_ID_EMIF_MGMT  0x9
  88 #define FME_FEATURE_ID_MAX10_SPI  0xe
  89 #define FME_FEATURE_ID_NIOS_SPI 0xd
  90 #define FME_FEATURE_ID_I2C_MASTER  0xf
  91
  92 #define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
  93 #define PORT_FEATURE_ID_ERROR 0x10
  94 #define PORT_FEATURE_ID_UMSG 0x12
  95 #define PORT_FEATURE_ID_UINT 0x13
  96 #define PORT_FEATURE_ID_STP 0x14
  97 #define PORT_FEATURE_ID_UAFU FEATURE_ID_AFU
  98
  99 /*
 100  * All headers and structures must be byte-packed to match the spec.
 101  */
 102 #pragma pack(push, 1)
 103
 104 struct feature_header {
 105         union {
 106                 u64 csr;
 107                 struct {
 108                         u16 id:12;
 109                         u8  revision:4;
 110                         u32 next_header_offset:24;
 111                         u8  end_of_list:1;
 112                         u32 reserved:19;
 113                         u8  type:4;
 114                 };
 115         };
 116 };
 117
 118 struct feature_bbb_header {
 119         struct uuid guid;
 120 };
 121
 122 struct feature_afu_header {
 123         struct uuid guid;
 124         union {
 125                 u64 csr;
 126                 struct {
 127                         u64 next_afu:24;
 128                         u64 reserved:40;
 129                 };
 130         };
 131 };
 132
 133 struct feature_fiu_header {
 134         struct uuid guid;
 135         union {
 136                 u64 csr;
 137                 struct {
 138                         u64 next_afu:24;
 139                         u64 reserved:40;
 140                 };
 141         };
 142 };
 143
 144 struct feature_fme_capability {
 145         union {
 146                 u64 csr;
 147                 struct {
 148                         u8  fabric_verid;       /* Fabric version ID */
 149                         u8  socket_id:1;        /* Socket id */
 150                         u8  rsvd1:3;            /* Reserved */
 151                         /* pci0 link available yes /no */
 152                         u8  pci0_link_avile:1;
 153                         /* pci1 link available yes /no */
 154                         u8  pci1_link_avile:1;
 155                         /* Coherent (QPI/UPI) link available yes /no */
 156                         u8  qpi_link_avile:1;
 157                         u8  rsvd2:1;            /* Reserved */
 158                         /* IOMMU or VT-d supported  yes/no */
 159                         u8  iommu_support:1;
 160                         u8  num_ports:3;        /* Number of ports */
 161                         u8  sf_fab_ctl:1;       /* Internal validation bit */
 162                         u8  rsvd3:3;            /* Reserved */
 163                         /*
 164                          * Address width supported in bits
 165                          * BXT -0x26 , SKX -0x30
 166                          */
 167                         u8  address_width_bits:6;
 168                         u8  rsvd4:2;            /* Reserved */
 169                         /* Size of cache supported in kb */
 170                         u16 cache_size:12;
 171                         u8  cache_assoc:4;      /* Cache Associativity */
 172                         u16 rsvd5:15;           /* Reserved */
 173                         u8  lock_bit:1;         /* Lock bit */
 174                 };
 175         };
 176 };
 177
 178 #define FME_AFU_ACCESS_PF               0
 179 #define FME_AFU_ACCESS_VF               1
 180
 181 struct feature_fme_port {
 182         union {
 183                 u64 csr;
 184                 struct {
 185                         u32 port_offset:24;
 186                         u8  reserved1;
 187                         u8  port_bar:3;
 188                         u32 reserved2:20;
 189                         u8  afu_access_control:1;
 190                         u8  reserved3:4;
 191                         u8  port_implemented:1;
 192                         u8  reserved4:3;
 193                 };
 194         };
 195 };
 196
 197 struct feature_fme_fab_status {
 198         union {
 199                 u64 csr;
 200                 struct {
 201                         u8  upilink_status:4;   /* UPI Link Status */
 202                         u8  rsvd1:4;            /* Reserved */
 203                         u8  pci0link_status:1;  /* pci0 link status */
 204                         u8  rsvd2:3;            /* Reserved */
 205                         u8  pci1link_status:1;  /* pci1 link status */
 206                         u64 rsvd3:51;           /* Reserved */
 207                 };
 208         };
 209 };
 210
 211 struct feature_fme_genprotrange2_base {
 212         union {
 213                 u64 csr;
 214                 struct {
 215                         u16 rsvd1;           /* Reserved */
 216                         /* Base Address of memory range */
 217                         u8  protected_base_addrss:4;
 218                         u64 rsvd2:44;           /* Reserved */
 219                 };
 220         };
 221 };
 222
 223 struct feature_fme_genprotrange2_limit {
 224         union {
 225                 u64 csr;
 226                 struct {
 227                         u16 rsvd1;           /* Reserved */
 228                         /* Limit Address of memory range */
 229                         u8  protected_limit_addrss:4;
 230                         u16 rsvd2:11;           /* Reserved */
 231                         u8  enable:1;        /* Enable GENPROTRANGE check */
 232                         u32 rsvd3;           /* Reserved */
 233                 };
 234         };
 235 };
 236
 237 struct feature_fme_dxe_lock {
 238         union {
 239                 u64 csr;
 240                 struct {
 241                         /*
 242                          * Determines write access to the DXE region CSRs
 243                          * 1 - CSR region is locked;
 244                          * 0 - it is open for write access.
 245                          */
 246                         u8  dxe_early_lock:1;
 247                         /*
 248                          * Determines write access to the HSSI CSR
 249                          * 1 - CSR region is locked;
 250                          * 0 - it is open for write access.
 251                          */
 252                         u8  dxe_late_lock:1;
 253                         u64 rsvd:62;
 254                 };
 255         };
 256 };
 257
 258 #define HSSI_ID_NO_HASSI        0
 259 #define HSSI_ID_PCIE_RP         1
 260 #define HSSI_ID_ETHERNET        2
 261
 262 struct feature_fme_bitstream_id {
 263         union {
 264                 u64 csr;
 265                 struct {
 266                         u32 gitrepo_hash:32;    /* GIT repository hash */
 267                         /*
 268                          * HSSI configuration identifier:
 269                          * 0 - No HSSI
 270                          * 1 - PCIe-RP
 271                          * 2 - Ethernet
 272                          */
 273                         u8  hssi_id:4;
 274                         u16 rsvd1:12;           /* Reserved */
 275                         /* Bitstream version patch number */
 276                         u8  bs_verpatch:4;
 277                         /* Bitstream version minor number */
 278                         u8  bs_verminor:4;
 279                         /* Bitstream version major number */
 280                         u8  bs_vermajor:4;
 281                         /* Bitstream version debug number */
 282                         u8  bs_verdebug:4;
 283                 };
 284         };
 285 };
 286
 287 struct feature_fme_bitstream_md {
 288         union {
 289                 u64 csr;
 290                 struct {
 291                         /* Seed number userd for synthesis flow */
 292                         u8  synth_seed:4;
 293                         /* Synthesis date(day number - 2 digits) */
 294                         u8  synth_day:8;
 295                         /* Synthesis date(month number - 2 digits) */
 296                         u8  synth_month:8;
 297                         /* Synthesis date(year number - 2 digits) */
 298                         u8  synth_year:8;
 299                         u64 rsvd:36;            /* Reserved */
 300                 };
 301         };
 302 };
 303
 304 struct feature_fme_iommu_ctrl {
 305         union {
 306                 u64 csr;
 307                 struct {
 308                         /* Disables IOMMU prefetcher for C0 channel */
 309                         u8 prefetch_disableC0:1;
 310                         /* Disables IOMMU prefetcher for C1 channel */
 311                         u8 prefetch_disableC1:1;
 312                         /* Disables IOMMU partial cache line writes */
 313                         u8 prefetch_wrdisable:1;
 314                         u8 rsvd1:1;             /* Reserved */
 315                         /*
 316                          * Select counter and read value from register
 317                          * iommu_stat.dbg_counters
 318                          * 0 - Number of 4K page translation response
 319                          * 1 - Number of 2M page translation response
 320                          * 2 - Number of 1G page translation response
 321                          */
 322                         u8 counter_sel:2;
 323                         u32 rsvd2:26;           /* Reserved */
 324                         /* Connected to IOMMU SIP Capabilities */
 325                         u32 capecap_defeature;
 326                 };
 327         };
 328 };
 329
 330 struct feature_fme_iommu_stat {
 331         union {
 332                 u64 csr;
 333                 struct {
 334                         /* Translation Enable bit from IOMMU SIP */
 335                         u8 translation_enable:1;
 336                         /* Drain request in progress */
 337                         u8 drain_req_inprog:1;
 338                         /* Invalidation current state */
 339                         u8 inv_state:3;
 340                         /* C0 Response Buffer current state */
 341                         u8 respbuffer_stateC0:3;
 342                         /* C1 Response Buffer current state */
 343                         u8 respbuffer_stateC1:3;
 344                         /* Last request ID to IOMMU SIP */
 345                         u8 last_reqID:4;
 346                         /* Last IOMMU SIP response ID value */
 347                         u8 last_respID:4;
 348                         /* Last IOMMU SIP response status value */
 349                         u8 last_respstatus:3;
 350                         /* C0 Transaction Buffer is not empty */
 351                         u8 transbuf_notEmptyC0:1;
 352                         /* C1 Transaction Buffer is not empty */
 353                         u8 transbuf_notEmptyC1:1;
 354                         /* C0 Request FIFO is not empty */
 355                         u8 reqFIFO_notemptyC0:1;
 356                         /* C1 Request FIFO is not empty */
 357                         u8 reqFIFO_notemptyC1:1;
 358                         /* C0 Response FIFO is not empty */
 359                         u8 respFIFO_notemptyC0:1;
 360                         /* C1 Response FIFO is not empty */
 361                         u8 respFIFO_notemptyC1:1;
 362                         /* C0 Response FIFO overflow detected */
 363                         u8 respFIFO_overflowC0:1;
 364                         /* C1 Response FIFO overflow detected */
 365                         u8 respFIFO_overflowC1:1;
 366                         /* C0 Transaction Buffer overflow detected */
 367                         u8 tranbuf_overflowC0:1;
 368                         /* C1 Transaction Buffer overflow detected */
 369                         u8 tranbuf_overflowC1:1;
 370                         /* Request FIFO overflow detected */
 371                         u8 reqFIFO_overflow:1;
 372                         /* IOMMU memory read in progress */
 373                         u8 memrd_inprog:1;
 374                         /* IOMMU memory write in progress */
 375                         u8 memwr_inprog:1;
 376                         u8 rsvd1:1;     /* Reserved */
 377                         /* Value of counter selected by iommu_ctl.counter_sel */
 378                         u16 dbg_counters:16;
 379                         u16 rsvd2:12;   /* Reserved */
 380                 };
 381         };
 382 };
 383
 384 struct feature_fme_pcie0_ctrl {
 385         union {
 386                 u64 csr;
 387                 struct {
 388                         u64 vtd_bar_lock:1;     /* Lock VT-D BAR register */
 389                         u64 rsvd1:3;
 390                         u64 rciep:1;            /* Configure PCIE0 as RCiEP */
 391                         u64 rsvd2:59;
 392                 };
 393         };
 394 };
 395
 396 struct feature_fme_llpr_smrr_base {
 397         union {
 398                 u64 csr;
 399                 struct {
 400                         u64 rsvd1:12;
 401                         u64 base:20;    /* SMRR2 memory range base address */
 402                         u64 rsvd2:32;
 403                 };
 404         };
 405 };
 406
 407 struct feature_fme_llpr_smrr_mask {
 408         union {
 409                 u64 csr;
 410                 struct {
 411                         u64 rsvd1:11;
 412                         u64 valid:1;    /* LLPR_SMRR rule is valid or not */
 413                         /*
 414                          * SMRR memory range mask which determines the range
 415                          * of region being mapped
 416                          */
 417                         u64 phys_mask:20;
 418                         u64 rsvd2:32;
 419                 };
 420         };
 421 };
 422
 423 struct feature_fme_llpr_smrr2_base {
 424         union {
 425                 u64 csr;
 426                 struct {
 427                         u64 rsvd1:12;
 428                         u64 base:20;    /* SMRR2 memory range base address */
 429                         u64 rsvd2:32;
 430                 };
 431         };
 432 };
 433
 434 struct feature_fme_llpr_smrr2_mask {
 435         union {
 436                 u64 csr;
 437                 struct {
 438                         u64 rsvd1:11;
 439                         u64 valid:1;    /* LLPR_SMRR2 rule is valid or not */
 440                         /*
 441                          * SMRR2 memory range mask which determines the range
 442                          * of region being mapped
 443                          */
 444                         u64 phys_mask:20;
 445                         u64 rsvd2:32;
 446                 };
 447         };
 448 };
 449
 450 struct feature_fme_llpr_meseg_base {
 451         union {
 452                 u64 csr;
 453                 struct {
 454                         /* A[45:19] of base address memory range */
 455                         u64 me_base:27;
 456                         u64 rsvd:37;
 457                 };
 458         };
 459 };
 460
 461 struct feature_fme_llpr_meseg_limit {
 462         union {
 463                 u64 csr;
 464                 struct {
 465                         /* A[45:19] of limit address memory range */
 466                         u64 me_limit:27;
 467                         u64 rsvd1:4;
 468                         u64 enable:1;   /* Enable LLPR MESEG rule */
 469                         u64 rsvd2:32;
 470                 };
 471         };
 472 };
 473
 474 struct feature_fme_header {
 475         struct feature_header header;
 476         struct feature_afu_header afu_header;
 477         u64 reserved;
 478         u64 scratchpad;
 479         struct feature_fme_capability capability;
 480         struct feature_fme_port port[MAX_FPGA_PORT_NUM];
 481         struct feature_fme_fab_status fab_status;
 482         struct feature_fme_bitstream_id bitstream_id;
 483         struct feature_fme_bitstream_md bitstream_md;
 484         struct feature_fme_genprotrange2_base genprotrange2_base;
 485         struct feature_fme_genprotrange2_limit genprotrange2_limit;
 486         struct feature_fme_dxe_lock dxe_lock;
 487         struct feature_fme_iommu_ctrl iommu_ctrl;
 488         struct feature_fme_iommu_stat iommu_stat;
 489         struct feature_fme_pcie0_ctrl pcie0_control;
 490         struct feature_fme_llpr_smrr_base smrr_base;
 491         struct feature_fme_llpr_smrr_mask smrr_mask;
 492         struct feature_fme_llpr_smrr2_base smrr2_base;
 493         struct feature_fme_llpr_smrr2_mask smrr2_mask;
 494         struct feature_fme_llpr_meseg_base meseg_base;
 495         struct feature_fme_llpr_meseg_limit meseg_limit;
 496 };
 497
 498 struct feature_port_capability {
 499         union {
 500                 u64 csr;
 501                 struct {
 502                         u8 port_number:2;       /* Port Number 0-3 */
 503                         u8 rsvd1:6;             /* Reserved */
 504                         u16 mmio_size;          /* User MMIO size in KB */
 505                         u8 rsvd2;               /* Reserved */
 506                         u8 sp_intr_num:4;       /* Supported interrupts num */
 507                         u32 rsvd3:28;           /* Reserved */
 508                 };
 509         };
 510 };
 511
 512 struct feature_port_control {
 513         union {
 514                 u64 csr;
 515                 struct {
 516                         u8 port_sftrst:1;       /* Port Soft Reset */
 517                         u8 rsvd1:1;             /* Reserved */
 518                         u8 latency_tolerance:1;/* '1' >= 40us, '0' < 40us */
 519                         u8 rsvd2:1;             /* Reserved */
 520                         u8 port_sftrst_ack:1;   /* HW ACK for Soft Reset */
 521                         u64 rsvd3:59;           /* Reserved */
 522                 };
 523         };
 524 };
 525
 526 #define PORT_POWER_STATE_NORMAL         0
 527 #define PORT_POWER_STATE_AP1            1
 528 #define PORT_POWER_STATE_AP2            2
 529 #define PORT_POWER_STATE_AP6            6
 530
 531 struct feature_port_status {
 532         union {
 533                 u64 csr;
 534                 struct {
 535                         u8 port_freeze:1;       /* '1' - freezed '0' - normal */
 536                         u8 rsvd1:7;             /* Reserved */
 537                         u8 power_state:4;       /* Power State */
 538                         u8 ap1_event:1;         /* AP1 event was detected  */
 539                         u8 ap2_event:1;         /* AP2 event was detected  */
 540                         u64 rsvd2:50;           /* Reserved */
 541                 };
 542         };
 543 };
 544
 545 /* Port Header Register Set */
 546 struct feature_port_header {
 547         struct feature_header header;
 548         struct feature_afu_header afu_header;
 549         u64 port_mailbox;
 550         u64 scratchpad;
 551         struct feature_port_capability capability;
 552         struct feature_port_control control;
 553         struct feature_port_status status;
 554         u64 rsvd2;
 555         u64 user_clk_freq_cmd0;
 556         u64 user_clk_freq_cmd1;
 557         u64 user_clk_freq_sts0;
 558         u64 user_clk_freq_sts1;
 559 };
 560
 561 struct feature_fme_tmp_threshold {
 562         union {
 563                 u64 csr;
 564                 struct {
 565                         u8  tmp_thshold1:7;       /* temperature Threshold 1 */
 566                         /* temperature Threshold 1 enable/disable */
 567                         u8  tmp_thshold1_enable:1;
 568                         u8  tmp_thshold2:7;       /* temperature Threshold 2 */
 569                         /* temperature Threshold 2 enable /disable */
 570                         u8  tmp_thshold2_enable:1;
 571                         u8  pro_hot_setpoint:7;   /* Proc Hot set point */
 572                         u8  rsvd4:1;              /* Reserved */
 573                         u8  therm_trip_thshold:7; /* Thermeal Trip Threshold */
 574                         u8  rsvd3:1;              /* Reserved */
 575                         u8  thshold1_status:1;    /* Threshold 1 Status */
 576                         u8  thshold2_status:1;    /* Threshold 2 Status */
 577                         u8  rsvd5:1;              /* Reserved */
 578                         /* Thermeal Trip Threshold status */
 579                         u8  therm_trip_thshold_status:1;
 580                         u8  rsvd6:4;              /* Reserved */
 581                         /* Validation mode- Force Proc Hot */
 582                         u8  valmodeforce:1;
 583                         /* Validation mode - Therm trip Hot */
 584                         u8  valmodetherm:1;
 585                         u8  rsvd2:2;              /* Reserved */
 586                         u8  thshold_policy:1;     /* threshold policy */
 587                         u32 rsvd:19;              /* Reserved */
 588                 };
 589         };
 590 };
 591
 592 /* Temperature Sensor Read values format 1 */
 593 struct feature_fme_temp_rdsensor_fmt1 {
 594         union {
 595                 u64 csr;
 596                 struct {
 597                         /* Reads out FPGA temperature in celsius */
 598                         u8  fpga_temp:7;
 599                         u8  rsvd0:1;                    /* Reserved */
 600                         /* Temperature reading sequence number */
 601                         u16 tmp_reading_seq_num;
 602                         /* Temperature reading is valid */
 603                         u8  tmp_reading_valid:1;
 604                         u8  rsvd1:7;                    /* Reserved */
 605                         u16 dbg_mode:10;                /* Debug mode */
 606                         u32 rsvd2:22;                   /* Reserved */
 607                 };
 608         };
 609 };
 610
 611 /* Temperature sensor read values format 2 */
 612 struct feature_fme_temp_rdsensor_fmt2 {
 613         u64 rsvd;       /* Reserved */
 614 };
 615
 616 /* Temperature Threshold Capability Register */
 617 struct feature_fme_tmp_threshold_cap {
 618         union {
 619                 u64 csr;
 620                 struct {
 621                         /* Temperature Threshold Unsupported */
 622                         u8  tmp_thshold_disabled:1;
 623                         u64 rsvd:63;                    /* Reserved */
 624                 };
 625         };
 626 };
 627
 628 /* FME THERNAL FEATURE */
 629 struct feature_fme_thermal {
 630         struct feature_header header;
 631         struct feature_fme_tmp_threshold threshold;
 632         struct feature_fme_temp_rdsensor_fmt1 rdsensor_fm1;
 633         struct feature_fme_temp_rdsensor_fmt2 rdsensor_fm2;
 634         struct feature_fme_tmp_threshold_cap threshold_cap;
 635 };
 636
 637 /* Power Status register */
 638 struct feature_fme_pm_status {
 639         union {
 640                 u64 csr;
 641                 struct {
 642                         /* FPGA Power consumed, The format is to be defined */
 643                         u32 pwr_consumed:18;
 644                         /* FPGA Latency Tolerance Reporting */
 645                         u8  fpga_latency_report:1;
 646                         u64 rsvd:45;                    /* Reserved */
 647                 };
 648         };
 649 };
 650
 651 /* AP Thresholds */
 652 struct feature_fme_pm_ap_threshold {
 653         union {
 654                 u64 csr;
 655                 struct {
 656                         /*
 657                          * Number of clocks (5ns period) for assertion
 658                          * of FME_data
 659                          */
 660                         u8  threshold1:7;
 661                         u8  rsvd1:1;
 662                         u8  threshold2:7;
 663                         u8  rsvd2:1;
 664                         u8  threshold1_status:1;
 665                         u8  threshold2_status:1;
 666                         u64 rsvd3:46;           /* Reserved */
 667                 };
 668         };
 669 };
 670
 671 /* Xeon Power Limit */
 672 struct feature_fme_pm_xeon_limit {
 673         union {
 674                 u64 csr;
 675                 struct {
 676                         /* Power limit in Watts in 12.3 format */
 677                         u16 pwr_limit:15;
 678                         /* Indicates that power limit has been written */
 679                         u8  enable:1;
 680                         /* 0 - Turbe range, 1 - Entire range */
 681                         u8  clamping:1;
 682                         /* Time constant in XXYYY format */
 683                         u8  time:7;
 684                         u64 rsvd:40;            /* Reserved */
 685                 };
 686         };
 687 };
 688
 689 /* FPGA Power Limit */
 690 struct feature_fme_pm_fpga_limit {
 691         union {
 692                 u64 csr;
 693                 struct {
 694                         /* Power limit in Watts in 12.3 format */
 695                         u16 pwr_limit:15;
 696                         /* Indicates that power limit has been written */
 697                         u8  enable:1;
 698                         /* 0 - Turbe range, 1 - Entire range */
 699                         u8  clamping:1;
 700                         /* Time constant in XXYYY format */
 701                         u8  time:7;
 702                         u64 rsvd:40;            /* Reserved */
 703                 };
 704         };
 705 };
 706
 707 /* FME POWER FEATURE */
 708 struct feature_fme_power {
 709         struct feature_header header;
 710         struct feature_fme_pm_status status;
 711         struct feature_fme_pm_ap_threshold threshold;
 712         struct feature_fme_pm_xeon_limit xeon_limit;
 713         struct feature_fme_pm_fpga_limit fpga_limit;
 714 };
 715
 716 #define CACHE_CHANNEL_RD        0
 717 #define CACHE_CHANNEL_WR        1
 718
 719 enum iperf_cache_events {
 720         IPERF_CACHE_RD_HIT,
 721         IPERF_CACHE_WR_HIT,
 722         IPERF_CACHE_RD_MISS,
 723         IPERF_CACHE_WR_MISS,
 724         IPERF_CACHE_RSVD, /* reserved */
 725         IPERF_CACHE_HOLD_REQ,
 726         IPERF_CACHE_DATA_WR_PORT_CONTEN,
 727         IPERF_CACHE_TAG_WR_PORT_CONTEN,
 728         IPERF_CACHE_TX_REQ_STALL,
 729         IPERF_CACHE_RX_REQ_STALL,
 730         IPERF_CACHE_EVICTIONS,
 731 };
 732
 733 /* FPMON Cache Control */
 734 struct feature_fme_ifpmon_ch_ctl {
 735         union {
 736                 u64 csr;
 737                 struct {
 738                         u8  reset_counters:1;   /* Reset Counters */
 739                         u8  rsvd1:7;            /* Reserved */
 740                         u8  freeze:1;           /* Freeze if set to 1 */
 741                         u8  rsvd2:7;            /* Reserved */
 742                         u8  cache_event:4;      /* Select the cache event */
 743                         u8  cci_chsel:1;        /* Select the channel */
 744                         u64 rsvd3:43;           /* Reserved */
 745                 };
 746         };
 747 };
 748
 749 /* FPMON Cache Counter */
 750 struct feature_fme_ifpmon_ch_ctr {
 751         union {
 752                 u64 csr;
 753                 struct {
 754                         /* Cache Counter for even addresse */
 755                         u64 cache_counter:48;
 756                         u16 rsvd:12;            /* Reserved */
 757                         /* Cache Event being reported */
 758                         u8  event_code:4;
 759                 };
 760         };
 761 };
 762
 763 enum iperf_fab_events {
 764         IPERF_FAB_PCIE0_RD,
 765         IPERF_FAB_PCIE0_WR,
 766         IPERF_FAB_PCIE1_RD,
 767         IPERF_FAB_PCIE1_WR,
 768         IPERF_FAB_UPI_RD,
 769         IPERF_FAB_UPI_WR,
 770         IPERF_FAB_MMIO_RD,
 771         IPERF_FAB_MMIO_WR,
 772 };
 773
 774 #define FAB_DISABLE_FILTER     0
 775 #define FAB_ENABLE_FILTER      1
 776
 777 /* FPMON FAB Control */
 778 struct feature_fme_ifpmon_fab_ctl {
 779         union {
 780                 u64 csr;
 781                 struct {
 782                         u8  reset_counters:1;   /* Reset Counters */
 783                         u8  rsvd:7;             /* Reserved */
 784                         u8  freeze:1;           /* Set to 1 frozen counter */
 785                         u8  rsvd1:7;            /* Reserved */
 786                         u8  fab_evtcode:4;      /* Fabric Event Code */
 787                         u8  port_id:2;          /* Port ID */
 788                         u8  rsvd2:1;            /* Reserved */
 789                         u8  port_filter:1;      /* Port Filter */
 790                         u64 rsvd3:40;           /* Reserved */
 791                 };
 792         };
 793 };
 794
 795 /* FPMON Event Counter */
 796 struct feature_fme_ifpmon_fab_ctr {
 797         union {
 798                 u64 csr;
 799                 struct {
 800                         u64 fab_cnt:60; /* Fabric event counter */
 801                         /* Fabric event code being reported */
 802                         u8  event_code:4;
 803                 };
 804         };
 805 };
 806
 807 /* FPMON Clock Counter */
 808 struct feature_fme_ifpmon_clk_ctr {
 809         u64 afu_interf_clock;           /* Clk_16UI (AFU clock) counter. */
 810 };
 811
 812 enum iperf_vtd_events {
 813         IPERF_VTD_AFU_MEM_RD_TRANS,
 814         IPERF_VTD_AFU_MEM_WR_TRANS,
 815         IPERF_VTD_AFU_DEVTLB_RD_HIT,
 816         IPERF_VTD_AFU_DEVTLB_WR_HIT,
 817         IPERF_VTD_DEVTLB_4K_FILL,
 818         IPERF_VTD_DEVTLB_2M_FILL,
 819         IPERF_VTD_DEVTLB_1G_FILL,
 820 };
 821
 822 /* VT-d control register */
 823 struct feature_fme_ifpmon_vtd_ctl {
 824         union {
 825                 u64 csr;
 826                 struct {
 827                         u8  reset_counters:1;   /* Reset Counters */
 828                         u8  rsvd:7;             /* Reserved */
 829                         u8  freeze:1;           /* Set to 1 frozen counter */
 830                         u8  rsvd1:7;            /* Reserved */
 831                         u8  vtd_evtcode:4;      /* VTd and TLB event code */
 832                         u64 rsvd2:44;           /* Reserved */
 833                 };
 834         };
 835 };
 836
 837 /* VT-d event counter */
 838 struct feature_fme_ifpmon_vtd_ctr {
 839         union {
 840                 u64 csr;
 841                 struct {
 842                         u64 vtd_counter:48;     /* VTd event counter */
 843                         u16 rsvd:12;            /* Reserved */
 844                         u8  event_code:4;       /* VTd event code */
 845                 };
 846         };
 847 };
 848
 849 enum iperf_vtd_sip_events {
 850         IPERF_VTD_SIP_IOTLB_4K_HIT,
 851         IPERF_VTD_SIP_IOTLB_2M_HIT,
 852         IPERF_VTD_SIP_IOTLB_1G_HIT,
 853         IPERF_VTD_SIP_SLPWC_L3_HIT,
 854         IPERF_VTD_SIP_SLPWC_L4_HIT,
 855         IPERF_VTD_SIP_RCC_HIT,
 856         IPERF_VTD_SIP_IOTLB_4K_MISS,
 857         IPERF_VTD_SIP_IOTLB_2M_MISS,
 858         IPERF_VTD_SIP_IOTLB_1G_MISS,
 859         IPERF_VTD_SIP_SLPWC_L3_MISS,
 860         IPERF_VTD_SIP_SLPWC_L4_MISS,
 861         IPERF_VTD_SIP_RCC_MISS,
 862 };
 863
 864 /* VT-d SIP control register */
 865 struct feature_fme_ifpmon_vtd_sip_ctl {
 866         union {
 867                 u64 csr;
 868                 struct {
 869                         u8  reset_counters:1;   /* Reset Counters */
 870                         u8  rsvd:7;             /* Reserved */
 871                         u8  freeze:1;           /* Set to 1 frozen counter */
 872                         u8  rsvd1:7;            /* Reserved */
 873                         u8  vtd_evtcode:4;      /* VTd and TLB event code */
 874                         u64 rsvd2:44;           /* Reserved */
 875                 };
 876         };
 877 };
 878
 879 /* VT-d SIP event counter */
 880 struct feature_fme_ifpmon_vtd_sip_ctr {
 881         union {
 882                 u64 csr;
 883                 struct {
 884                         u64 vtd_counter:48;     /* VTd event counter */
 885                         u16 rsvd:12;            /* Reserved */
 886                         u8 event_code:4;        /* VTd event code */
 887                 };
 888         };
 889 };
 890
 891 /* FME IPERF FEATURE */
 892 struct feature_fme_iperf {
 893         struct feature_header header;
 894         struct feature_fme_ifpmon_ch_ctl ch_ctl;
 895         struct feature_fme_ifpmon_ch_ctr ch_ctr0;
 896         struct feature_fme_ifpmon_ch_ctr ch_ctr1;
 897         struct feature_fme_ifpmon_fab_ctl fab_ctl;
 898         struct feature_fme_ifpmon_fab_ctr fab_ctr;
 899         struct feature_fme_ifpmon_clk_ctr clk;
 900         struct feature_fme_ifpmon_vtd_ctl vtd_ctl;
 901         struct feature_fme_ifpmon_vtd_ctr vtd_ctr;
 902         struct feature_fme_ifpmon_vtd_sip_ctl vtd_sip_ctl;
 903         struct feature_fme_ifpmon_vtd_sip_ctr vtd_sip_ctr;
 904 };
 905
 906 enum dperf_fab_events {
 907         DPERF_FAB_PCIE0_RD,
 908         DPERF_FAB_PCIE0_WR,
 909         DPERF_FAB_MMIO_RD = 6,
 910         DPERF_FAB_MMIO_WR,
 911 };
 912
 913 /* FPMON FAB Control */
 914 struct feature_fme_dfpmon_fab_ctl {
 915         union {
 916                 u64 csr;
 917                 struct {
 918                         u8  reset_counters:1;   /* Reset Counters */
 919                         u8  rsvd:7;             /* Reserved */
 920                         u8  freeze:1;           /* Set to 1 frozen counter */
 921                         u8  rsvd1:7;            /* Reserved */
 922                         u8  fab_evtcode:4;      /* Fabric Event Code */
 923                         u8  port_id:2;          /* Port ID */
 924                         u8  rsvd2:1;            /* Reserved */
 925                         u8  port_filter:1;      /* Port Filter */
 926                         u64 rsvd3:40;           /* Reserved */
 927                 };
 928         };
 929 };
 930
 931 /* FPMON Event Counter */
 932 struct feature_fme_dfpmon_fab_ctr {
 933         union {
 934                 u64 csr;
 935                 struct {
 936                         u64 fab_cnt:60; /* Fabric event counter */
 937                         /* Fabric event code being reported */
 938                         u8  event_code:4;
 939                 };
 940         };
 941 };
 942
 943 /* FPMON Clock Counter */
 944 struct feature_fme_dfpmon_clk_ctr {
 945         u64 afu_interf_clock;           /* Clk_16UI (AFU clock) counter. */
 946 };
 947
 948 /* FME DPERF FEATURE */
 949 struct feature_fme_dperf {
 950         struct feature_header header;
 951         u64 rsvd[3];
 952         struct feature_fme_dfpmon_fab_ctl fab_ctl;
 953         struct feature_fme_dfpmon_fab_ctr fab_ctr;
 954         struct feature_fme_dfpmon_clk_ctr clk;
 955 };
 956
 957 struct feature_fme_error0 {
 958 #define FME_ERROR0_MASK        0xFFUL
 959 #define FME_ERROR0_MASK_DEFAULT 0x40UL  /* pcode workaround */
 960         union {
 961                 u64 csr;
 962                 struct {
 963                         u8  fabric_err:1;       /* Fabric error */
 964                         u8  fabfifo_overflow:1; /* Fabric fifo overflow */
 965                         u8  kticdc_parity_err:2;/* KTI CDC Parity Error */
 966                         u8  iommu_parity_err:1; /* IOMMU Parity error */
 967                         /* AFU PF/VF access mismatch detected */
 968                         u8  afu_acc_mode_err:1;
 969                         u8  mbp_err:1;          /* Indicates an MBP event */
 970                         /* PCIE0 CDC Parity Error */
 971                         u8  pcie0cdc_parity_err:5;
 972                         /* PCIE1 CDC Parity Error */
 973                         u8  pcie1cdc_parity_err:5;
 974                         /* CVL CDC Parity Error */
 975                         u8  cvlcdc_parity_err:3;
 976                         u64 rsvd:44;            /* Reserved */
 977                 };
 978         };
 979 };
 980
 981 /* PCIe0 Error Status register */
 982 struct feature_fme_pcie0_error {
 983 #define FME_PCIE0_ERROR_MASK   0xFFUL
 984         union {
 985                 u64 csr;
 986                 struct {
 987                         u8  formattype_err:1;   /* TLP format/type error */
 988                         u8  MWAddr_err:1;       /* TLP MW address error */
 989                         u8  MWAddrLength_err:1; /* TLP MW length error */
 990                         u8  MRAddr_err:1;       /* TLP MR address error */
 991                         u8  MRAddrLength_err:1; /* TLP MR length error */
 992                         u8  cpl_tag_err:1;      /* TLP CPL tag error */
 993                         u8  cpl_status_err:1;   /* TLP CPL status error */
 994                         u8  cpl_timeout_err:1;  /* TLP CPL timeout */
 995                         u8  cci_parity_err:1;   /* CCI bridge parity error */
 996                         u8  rxpoison_tlp_err:1; /* Received a TLP with EP set */
 997                         u64 rsvd:52;            /* Reserved */
 998                         u8  vfnumb_err:1;       /* Number of error VF */
 999                         u8  funct_type_err:1;   /* Virtual (1) or Physical */
1000                 };
1001         };
1002 };
1003
1004 /* PCIe1 Error Status register */
1005 struct feature_fme_pcie1_error {
1006 #define FME_PCIE1_ERROR_MASK   0xFFUL
1007         union {
1008                 u64 csr;
1009                 struct {
1010                         u8  formattype_err:1;   /* TLP format/type error */
1011                         u8  MWAddr_err:1;       /* TLP MW address error */
1012                         u8  MWAddrLength_err:1; /* TLP MW length error */
1013                         u8  MRAddr_err:1;       /* TLP MR address error */
1014                         u8  MRAddrLength_err:1; /* TLP MR length error */
1015                         u8  cpl_tag_err:1;      /* TLP CPL tag error */
1016                         u8  cpl_status_err:1;   /* TLP CPL status error */
1017                         u8  cpl_timeout_err:1;  /* TLP CPL timeout */
1018                         u8  cci_parity_err:1;   /* CCI bridge parity error */
1019                         u8  rxpoison_tlp_err:1; /* Received a TLP with EP set */
1020                         u64 rsvd:54;            /* Reserved */
1021                 };
1022         };
1023 };
1024
1025 /* FME First Error register */
1026 struct feature_fme_first_error {
1027 #define FME_FIRST_ERROR_MASK   ((1ULL << 60) - 1)
1028         union {
1029                 u64 csr;
1030                 struct {
1031                         /*
1032                          * Indicates the Error Register that was
1033                          * triggered first
1034                          */
1035                         u64 err_reg_status:60;
1036                         /*
1037                          * Holds 60 LSBs from the Error register that was
1038                          * triggered first
1039                          */
1040                         u8 errReg_id:4;
1041                 };
1042         };
1043 };
1044
1045 /* FME Next Error register */
1046 struct feature_fme_next_error {
1047 #define FME_NEXT_ERROR_MASK    ((1ULL << 60) - 1)
1048         union {
1049                 u64 csr;
1050                 struct {
1051                         /*
1052                          * Indicates the Error Register that was
1053                          * triggered second
1054                          */
1055                         u64 err_reg_status:60;
1056                         /*
1057                          * Holds 60 LSBs from the Error register that was
1058                          * triggered second
1059                          */
1060                         u8  errReg_id:4;
1061                 };
1062         };
1063 };
1064
1065 /* RAS Non Fatal Error Status register */
1066 struct feature_fme_ras_nonfaterror {
1067         union {
1068                 u64 csr;
1069                 struct {
1070                         /* thremal threshold AP1 */
1071                         u8  temp_thresh_ap1:1;
1072                         /* thremal threshold AP2 */
1073                         u8  temp_thresh_ap2:1;
1074                         u8  pcie_error:1;       /* pcie Error */
1075                         u8  portfatal_error:1;  /* port fatal error */
1076                         u8  proc_hot:1;         /* Indicates a ProcHot event */
1077                         /* Indicates an AFU PF/VF access mismatch */
1078                         u8  afu_acc_mode_err:1;
1079                         /* Injected nonfata Error */
1080                         u8  injected_nonfata_err:1;
1081                         u8  rsvd1:2;
1082                         /* Temperature threshold triggered AP6*/
1083                         u8  temp_thresh_AP6:1;
1084                         /* Power threshold triggered AP1 */
1085                         u8  power_thresh_AP1:1;
1086                         /* Power threshold triggered AP2 */
1087                         u8  power_thresh_AP2:1;
1088                         /* Indicates a MBP event */
1089                         u8  mbp_err:1;
1090                         u64 rsvd2:51;           /* Reserved */
1091                 };
1092         };
1093 };
1094
1095 /* RAS Catastrophic Fatal Error Status register */
1096 struct feature_fme_ras_catfaterror {
1097         union {
1098                 u64 csr;
1099                 struct {
1100                         /* KTI Link layer error detected */
1101                         u8  ktilink_fatal_err:1;
1102                         /* tag-n-cache error detected */
1103                         u8  tagcch_fatal_err:1;
1104                         /* CCI error detected */
1105                         u8  cci_fatal_err:1;
1106                         /* KTI Protocol error detected */
1107                         u8  ktiprpto_fatal_err:1;
1108                         /* Fatal DRAM error detected */
1109                         u8  dram_fatal_err:1;
1110                         /* IOMMU detected */
1111                         u8  iommu_fatal_err:1;
1112                         /* Fabric Fatal Error */
1113                         u8  fabric_fatal_err:1;
1114                         /* PCIe possion Error */
1115                         u8  pcie_poison_err:1;
1116                         /* Injected fatal Error */
1117                         u8  inject_fata_err:1;
1118                         /* Catastrophic CRC Error */
1119                         u8  crc_catast_err:1;
1120                         /* Catastrophic Thermal Error */
1121                         u8  therm_catast_err:1;
1122                         /* Injected Catastrophic Error */
1123                         u8  injected_catast_err:1;
1124                         u64 rsvd:52;
1125                 };
1126         };
1127 };
1128
1129 /* RAS Error injection register */
1130 struct feature_fme_ras_error_inj {
1131 #define FME_RAS_ERROR_INJ_MASK      0x7UL
1132         union {
1133                 u64 csr;
1134                 struct {
1135                         u8  catast_error:1;     /* Catastrophic error flag */
1136                         u8  fatal_error:1;      /* Fatal error flag */
1137                         u8  nonfatal_error:1;   /* NonFatal error flag */
1138                         u64 rsvd:61;            /* Reserved */
1139                 };
1140         };
1141 };
1142
1143 /* FME error capabilities */
1144 struct feature_fme_error_capability {
1145         union {
1146         u64 csr;
1147                 struct {
1148                         u8 support_intr:1;
1149                         /* MSI-X vector table entry number */
1150                         u16 intr_vector_num:12;
1151                         u64 rsvd:51;    /* Reserved */
1152                 };
1153         };
1154 };
1155
1156 /* FME ERR FEATURE */
1157 struct feature_fme_err {
1158         struct feature_header header;
1159         struct feature_fme_error0 fme_err_mask;
1160         struct feature_fme_error0 fme_err;
1161         struct feature_fme_pcie0_error pcie0_err_mask;
1162         struct feature_fme_pcie0_error pcie0_err;
1163         struct feature_fme_pcie1_error pcie1_err_mask;
1164         struct feature_fme_pcie1_error pcie1_err;
1165         struct feature_fme_first_error fme_first_err;
1166         struct feature_fme_next_error fme_next_err;
1167         struct feature_fme_ras_nonfaterror ras_nonfat_mask;
1168         struct feature_fme_ras_nonfaterror ras_nonfaterr;
1169         struct feature_fme_ras_catfaterror ras_catfat_mask;
1170         struct feature_fme_ras_catfaterror ras_catfaterr;
1171         struct feature_fme_ras_error_inj ras_error_inj;
1172         struct feature_fme_error_capability fme_err_capability;
1173 };
1174
1175 /* FME Partial Reconfiguration Control */
1176 struct feature_fme_pr_ctl {
1177         union {
1178                 u64 csr;
1179                 struct {
1180                         u8  pr_reset:1;         /* Reset PR Engine */
1181                         u8  rsvd3:3;            /* Reserved */
1182                         u8  pr_reset_ack:1;     /* Reset PR Engine Ack */
1183                         u8  rsvd4:3;            /* Reserved */
1184                         u8  pr_regionid:2;      /* PR Region ID */
1185                         u8  rsvd1:2;            /* Reserved */
1186                         u8  pr_start_req:1;     /* PR Start Request */
1187                         u8  pr_push_complete:1; /* PR Data push complete */
1188                         u8  pr_kind:1;          /* PR Data push complete */
1189                         u32 rsvd:17;            /* Reserved */
1190                         u32 config_data;        /* Config data TBD */
1191                 };
1192         };
1193 };
1194
1195 /* FME Partial Reconfiguration Status */
1196 struct feature_fme_pr_status {
1197         union {
1198                 u64 csr;
1199                 struct {
1200                         u16 pr_credit:9;        /* PR Credits */
1201                         u8  rsvd2:7;            /* Reserved */
1202                         u8  pr_status:1;        /* PR status */
1203                         u8  rsvd:3;             /* Reserved */
1204                         /* Altra PR Controller Block status */
1205                         u8  pr_controller_status:3;
1206                         u8  rsvd1:1;            /* Reserved */
1207                         u8  pr_host_status:4;   /* PR Host status */
1208                         u8  rsvd3:4;            /* Reserved */
1209                         /* Security Block Status fields (TBD) */
1210                         u32 security_bstatus;
1211                 };
1212         };
1213 };
1214
1215 /* FME Partial Reconfiguration Data */
1216 struct feature_fme_pr_data {
1217         union {
1218                 u64 csr;        /* PR data from the raw-binary file */
1219                 struct {
1220                         /* PR data from the raw-binary file */
1221                         u32 pr_data_raw;
1222                         u32 rsvd;
1223                 };
1224         };
1225 };
1226
1227 /* FME PR Public Key */
1228 struct feature_fme_pr_key {
1229         u64 key;                /* FME PR Public Hash */
1230 };
1231
1232 /* FME PR FEATURE */
1233 struct feature_fme_pr {
1234         struct feature_header header;
1235         /*Partial Reconfiguration control */
1236         struct feature_fme_pr_ctl       ccip_fme_pr_control;
1237
1238         /* Partial Reconfiguration Status */
1239         struct feature_fme_pr_status    ccip_fme_pr_status;
1240
1241         /* Partial Reconfiguration data */
1242         struct feature_fme_pr_data      ccip_fme_pr_data;
1243
1244         /* Partial Reconfiguration data */
1245         u64                             ccip_fme_pr_err;
1246
1247         u64 rsvd1[3];
1248
1249         /* Partial Reconfiguration data registers */
1250         u64 fme_pr_data1;
1251         u64 fme_pr_data2;
1252         u64 fme_pr_data3;
1253         u64 fme_pr_data4;
1254         u64 fme_pr_data5;
1255         u64 fme_pr_data6;
1256         u64 fme_pr_data7;
1257         u64 fme_pr_data8;
1258
1259         u64 rsvd2[5];
1260
1261         /* PR Interface ID */
1262         u64 fme_pr_intfc_id_l;
1263         u64 fme_pr_intfc_id_h;
1264
1265         /* MSIX filed to be Added */
1266 };
1267
1268 /* FME HSSI Control */
1269 struct feature_fme_hssi_eth_ctrl {
1270         union {
1271                 u64 csr;
1272                 struct {
1273                         u32 data:32;            /* HSSI data */
1274                         u16 address:16;         /* HSSI address */
1275                         /*
1276                          * HSSI comamnd
1277                          * 0x0 - No request
1278                          * 0x08 - SW register RD request
1279                          * 0x10 - SW register WR request
1280                          * 0x40 - Auxiliar bus RD request
1281                          * 0x80 - Auxiliar bus WR request
1282                          */
1283                         u16 cmd:16;
1284                 };
1285         };
1286 };
1287
1288 /* FME HSSI Status */
1289 struct feature_fme_hssi_eth_stat {
1290         union {
1291                 u64 csr;
1292                 struct {
1293                         u32 data:32;            /* HSSI data */
1294                         u8  acknowledge:1;      /* HSSI acknowledge */
1295                         u8  spare:1;            /* HSSI spare */
1296                         u32 rsvd:30;            /* Reserved */
1297                 };
1298         };
1299 };
1300
1301 /* FME HSSI FEATURE */
1302 struct feature_fme_hssi {
1303         struct feature_header header;
1304         struct feature_fme_hssi_eth_ctrl        hssi_control;
1305         struct feature_fme_hssi_eth_stat        hssi_status;
1306 };
1307
1308 #define PORT_ERR_MASK           0xfff0703ff001f
1309 struct feature_port_err_key {
1310         union {
1311                 u64 csr;
1312                 struct {
1313                         /* Tx Channel0: Overflow */
1314                         u8 tx_ch0_overflow:1;
1315                         /* Tx Channel0: Invalid request encoding */
1316                         u8 tx_ch0_invaldreq :1;
1317                         /* Tx Channel0: Request with cl_len=3 not supported */
1318                         u8 tx_ch0_cl_len3:1;
1319                         /* Tx Channel0: Request with cl_len=2 not aligned 2CL */
1320                         u8 tx_ch0_cl_len2:1;
1321                         /* Tx Channel0: Request with cl_len=4 not aligned 4CL */
1322                         u8 tx_ch0_cl_len4:1;
1323
1324                         u16 rsvd1:4;                    /* Reserved */
1325
1326                         /* AFU MMIO RD received while PORT is in reset */
1327                         u8 mmio_rd_whilerst:1;
1328                         /* AFU MMIO WR received while PORT is in reset */
1329                         u8 mmio_wr_whilerst:1;
1330
1331                         u16 rsvd2:5;                    /* Reserved */
1332
1333                         /* Tx Channel1: Overflow */
1334                         u8 tx_ch1_overflow:1;
1335                         /* Tx Channel1: Invalid request encoding */
1336                         u8 tx_ch1_invaldreq:1;
1337                         /* Tx Channel1: Request with cl_len=3 not supported */
1338                         u8 tx_ch1_cl_len3:1;
1339                         /* Tx Channel1: Request with cl_len=2 not aligned 2CL */
1340                         u8 tx_ch1_cl_len2:1;
1341                         /* Tx Channel1: Request with cl_len=4 not aligned 4CL */
1342                         u8 tx_ch1_cl_len4:1;
1343
1344                         /* Tx Channel1: Insufficient data payload */
1345                         u8 tx_ch1_insuff_data:1;
1346                         /* Tx Channel1: Data payload overrun */
1347                         u8 tx_ch1_data_overrun:1;
1348                         /* Tx Channel1 : Incorrect address */
1349                         u8 tx_ch1_incorr_addr:1;
1350                         /* Tx Channel1 : NON-Zero SOP Detected */
1351                         u8 tx_ch1_nzsop:1;
1352                         /* Tx Channel1 : Illegal VC_SEL, atomic request VLO */
1353                         u8 tx_ch1_illegal_vcsel:1;
1354
1355                         u8 rsvd3:6;                     /* Reserved */
1356
1357                         /* MMIO Read Timeout in AFU */
1358                         u8 mmioread_timeout:1;
1359
1360                         /* Tx Channel2: FIFO Overflow */
1361                         u8 tx_ch2_fifo_overflow:1;
1362
1363                         /* MMIO read is not matching pending request */
1364                         u8 unexp_mmio_resp:1;
1365
1366                         u8 rsvd4:5;                     /* Reserved */
1367
1368                         /* Number of pending Requests: counter overflow */
1369                         u8 tx_req_counter_overflow:1;
1370                         /* Req with Address violating SMM Range */
1371                         u8 llpr_smrr_err:1;
1372                         /* Req with Address violating second SMM Range */
1373                         u8 llpr_smrr2_err:1;
1374                         /* Req with Address violating ME Stolen message */
1375                         u8 llpr_mesg_err:1;
1376                         /* Req with Address violating Generic Protected Range */
1377                         u8 genprot_range_err:1;
1378                         /* Req with Address violating Legacy Range low */
1379                         u8 legrange_low_err:1;
1380                         /* Req with Address violating Legacy Range High */
1381                         u8 legrange_high_err:1;
1382                         /* Req with Address violating VGA memory range */
1383                         u8 vgmem_range_err:1;
1384                         u8 page_fault_err:1;            /* Page fault */
1385                         u8 pmr_err:1;                   /* PMR Error */
1386                         u8 ap6_event:1;                 /* AP6 event */
1387                         /* VF FLR detected on Port with PF access control */
1388                         u8 vfflr_access_err:1;
1389                         u16 rsvd5:12;                   /* Reserved */
1390                 };
1391         };
1392 };
1393
1394 /* Port first error register, not contain all error bits in error register. */
1395 struct feature_port_first_err_key {
1396         union {
1397                 u64 csr;
1398                 struct {
1399                         u8 tx_ch0_overflow:1;
1400                         u8 tx_ch0_invaldreq :1;
1401                         u8 tx_ch0_cl_len3:1;
1402                         u8 tx_ch0_cl_len2:1;
1403                         u8 tx_ch0_cl_len4:1;
1404                         u8 rsvd1:4;                     /* Reserved */
1405                         u8 mmio_rd_whilerst:1;
1406                         u8 mmio_wr_whilerst:1;
1407                         u8 rsvd2:5;                     /* Reserved */
1408                         u8 tx_ch1_overflow:1;
1409                         u8 tx_ch1_invaldreq:1;
1410                         u8 tx_ch1_cl_len3:1;
1411                         u8 tx_ch1_cl_len2:1;
1412                         u8 tx_ch1_cl_len4:1;
1413                         u8 tx_ch1_insuff_data:1;
1414                         u8 tx_ch1_data_overrun:1;
1415                         u8 tx_ch1_incorr_addr:1;
1416                         u8 tx_ch1_nzsop:1;
1417                         u8 tx_ch1_illegal_vcsel:1;
1418                         u8 rsvd3:6;                     /* Reserved */
1419                         u8 mmioread_timeout:1;
1420                         u8 tx_ch2_fifo_overflow:1;
1421                         u8 rsvd4:6;                     /* Reserved */
1422                         u8 tx_req_counter_overflow:1;
1423                         u32 rsvd5:23;                   /* Reserved */
1424                 };
1425         };
1426 };
1427
1428 /* Port malformed Req0 */
1429 struct feature_port_malformed_req0 {
1430         u64 header_lsb;
1431 };
1432
1433 /* Port malformed Req1 */
1434 struct feature_port_malformed_req1 {
1435         u64 header_msb;
1436 };
1437
1438 /* Port debug register */
1439 struct feature_port_debug {
1440         u64 port_debug;
1441 };
1442
1443 /* Port error capabilities */
1444 struct feature_port_err_capability {
1445         union {
1446                 u64 csr;
1447                 struct {
1448                         u8  support_intr:1;
1449                         /* MSI-X vector table entry number */
1450                         u16 intr_vector_num:12;
1451                         u64 rsvd:51;            /* Reserved */
1452                 };
1453         };
1454 };
1455
1456 /* PORT FEATURE ERROR */
1457 struct feature_port_error {
1458         struct feature_header header;
1459         struct feature_port_err_key error_mask;
1460         struct feature_port_err_key port_error;
1461         struct feature_port_first_err_key port_first_error;
1462         struct feature_port_malformed_req0 malreq0;
1463         struct feature_port_malformed_req1 malreq1;
1464         struct feature_port_debug port_debug;
1465         struct feature_port_err_capability error_capability;
1466 };
1467
1468 /* Port UMSG Capability */
1469 struct feature_port_umsg_cap {
1470         union {
1471                 u64 csr;
1472                 struct {
1473                         /* Number of umsg allocated to this port */
1474                         u8 umsg_allocated;
1475                         /* Enable / Disable UMsg engine for this port */
1476                         u8 umsg_enable:1;
1477                         /* Usmg initialization status */
1478                         u8 umsg_init_complete:1;
1479                         /* IOMMU can not translate the umsg base address */
1480                         u8 umsg_trans_error:1;
1481                         u64 rsvd:53;            /* Reserved */
1482                 };
1483         };
1484 };
1485
1486 /* Port UMSG base address */
1487 struct feature_port_umsg_baseaddr {
1488         union {
1489                 u64 csr;
1490                 struct {
1491                         u64 base_addr:48;       /* 48 bit physical address */
1492                         u16 rsvd;               /* Reserved */
1493                 };
1494         };
1495 };
1496
1497 struct feature_port_umsg_mode {
1498         union {
1499                 u64 csr;
1500                 struct {
1501                         u32 umsg_hint_enable;   /* UMSG hint enable/disable */
1502                         u32 rsvd;               /* Reserved */
1503                 };
1504         };
1505 };
1506
1507 /* PORT FEATURE UMSG */
1508 struct feature_port_umsg {
1509         struct feature_header header;
1510         struct feature_port_umsg_cap capability;
1511         struct feature_port_umsg_baseaddr baseaddr;
1512         struct feature_port_umsg_mode mode;
1513 };
1514
1515 #define UMSG_EN_POLL_INVL 10 /* us */
1516 #define UMSG_EN_POLL_TIMEOUT 1000 /* us */
1517
1518 /* Port UINT Capability */
1519 struct feature_port_uint_cap {
1520         union {
1521                 u64 csr;
1522                 struct {
1523                         u16 intr_num:12;        /* Supported interrupts num */
1524                         /* First MSI-X vector table entry number */
1525                         u16 first_vec_num:12;
1526                         u64 rsvd:40;
1527                 };
1528         };
1529 };
1530
1531 /* PORT FEATURE UINT */
1532 struct feature_port_uint {
1533         struct feature_header header;
1534         struct feature_port_uint_cap capability;
1535 };
1536
1537 /* STP region supports mmap operation, so use page aligned size. */
1538 #define PORT_FEATURE_STP_REGION_SIZE \
1539         IFPGA_PAGE_ALIGN(sizeof(struct feature_port_stp))
1540
1541 /* Port STP status register (for debug only)*/
1542 struct feature_port_stp_status {
1543         union {
1544                 u64 csr;
1545                 struct {
1546                         /* SLD Hub end-point read/write timeout */
1547                         u8 sld_ep_timeout:1;
1548                         /* Remote STP in reset/disable */
1549                         u8 rstp_disabled:1;
1550                         u8 unsupported_read:1;
1551                         /* MMIO timeout detected and faked with a response */
1552                         u8 mmio_timeout:1;
1553                         u8 txfifo_count:4;
1554                         u8 rxfifo_count:4;
1555                         u8 txfifo_overflow:1;
1556                         u8 txfifo_underflow:1;
1557                         u8 rxfifo_overflow:1;
1558                         u8 rxfifo_underflow:1;
1559                         /* Number of MMIO write requests */
1560                         u16 write_requests;
1561                         /* Number of MMIO read requests */
1562                         u16 read_requests;
1563                         /* Number of MMIO read responses */
1564                         u16 read_responses;
1565                 };
1566         };
1567 };
1568
1569 /*
1570  * PORT FEATURE STP
1571  * Most registers in STP region are not touched by driver, but mmapped to user
1572  * space. So they are not defined in below data structure, as its actual size
1573  * is 0x18c per spec.
1574  */
1575 struct feature_port_stp {
1576         struct feature_header header;
1577         struct feature_port_stp_status stp_status;
1578 };
1579
1580 /**
1581  * enum fpga_pr_states - fpga PR states
1582  * @FPGA_PR_STATE_UNKNOWN: can't determine state
1583  * @FPGA_PR_STATE_WRITE_INIT: preparing FPGA for programming
1584  * @FPGA_PR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage
1585  * @FPGA_PR_STATE_WRITE: writing image to FPGA
1586  * @FPGA_PR_STATE_WRITE_ERR: Error while writing FPGA
1587  * @FPGA_PR_STATE_WRITE_COMPLETE: Doing post programming steps
1588  * @FPGA_PR_STATE_WRITE_COMPLETE_ERR: Error during WRITE_COMPLETE
1589  * @FPGA_PR_STATE_OPERATING: FPGA PR done
1590  */
1591 enum fpga_pr_states {
1592         /* canot determine state states */
1593         FPGA_PR_STATE_UNKNOWN,
1594
1595         /* write sequence: init, write, complete */
1596         FPGA_PR_STATE_WRITE_INIT,
1597         FPGA_PR_STATE_WRITE_INIT_ERR,
1598         FPGA_PR_STATE_WRITE,
1599         FPGA_PR_STATE_WRITE_ERR,
1600         FPGA_PR_STATE_WRITE_COMPLETE,
1601         FPGA_PR_STATE_WRITE_COMPLETE_ERR,
1602
1603         /* FPGA PR done */
1604         FPGA_PR_STATE_DONE,
1605 };
1606
1607 /*
1608  * FPGA Manager flags
1609  * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported
1610  */
1611 #define FPGA_MGR_PARTIAL_RECONFIG       BIT(0)
1612
1613 /**
1614  * struct fpga_pr_info - specific information to a FPGA PR
1615  * @flags: boolean flags as defined above
1616  * @pr_err: PR error code
1617  * @state: fpga manager state
1618  * @port_id: port id
1619  */
1620 struct fpga_pr_info {
1621         u32 flags;
1622         u64 pr_err;
1623         enum fpga_pr_states state;
1624         int port_id;
1625 };
1626
1627 #define DEFINE_FPGA_PR_ERR_MSG(_name_)                  \
1628 static const char * const _name_[] = {                  \
1629         "PR operation error detected",                  \
1630         "PR CRC error detected",                        \
1631         "PR incompatiable bitstream error detected",    \
1632         "PR IP protocol error detected",                \
1633         "PR FIFO overflow error detected",              \
1634         "PR timeout error detected",                    \
1635         "PR secure load error detected",                \
1636 }
1637
1638 #define RST_POLL_INVL 10 /* us */
1639 #define RST_POLL_TIMEOUT 1000 /* us */
1640
1641 #define PR_WAIT_TIMEOUT   15000000
1642
1643 #define PR_HOST_STATUS_IDLE     0
1644 #define PR_MAX_ERR_NUM  7
1645
1646 DEFINE_FPGA_PR_ERR_MSG(pr_err_msg);
1647
1648 /*
1649  * green bitstream header must be byte-packed to match the
1650  * real file format.
1651  */
1652 struct bts_header {
1653         u64 guid_h;
1654         u64 guid_l;
1655         u32 metadata_len;
1656 };
1657
1658 #define GBS_GUID_H              0x414750466e6f6558
1659 #define GBS_GUID_L              0x31303076534247b7
1660 #define is_valid_bts(bts_hdr)                           \
1661         (((bts_hdr)->guid_h == GBS_GUID_H) &&           \
1662         ((bts_hdr)->guid_l == GBS_GUID_L))
1663
1664 #pragma pack(pop)
1665 #endif /* _BASE_IFPGA_DEFINES_H_ */