drivers/raw/ifpga_rawdev/base/ifpga_defines.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2018 Intel Corporation
   3  */
   4
   5 #ifndef _IFPGA_DEFINES_H_
   6 #define _IFPGA_DEFINES_H_
   7
   8 #include "ifpga_compat.h"
   9
  10 #define MAX_FPGA_PORT_NUM  4
  11
  12 #define FME_FEATURE_HEADER          "fme_hdr"
  13 #define FME_FEATURE_THERMAL_MGMT    "fme_thermal"
  14 #define FME_FEATURE_POWER_MGMT      "fme_power"
  15 #define FME_FEATURE_GLOBAL_IPERF    "fme_iperf"
  16 #define FME_FEATURE_GLOBAL_ERR      "fme_error"
  17 #define FME_FEATURE_PR_MGMT         "fme_pr"
  18 #define FME_FEATURE_EMIF_MGMT       "fme_emif"
  19 #define FME_FEATURE_HSSI_ETH        "fme_hssi"
  20 #define FME_FEATURE_GLOBAL_DPERF    "fme_dperf"
  21 #define FME_FEATURE_QSPI_FLASH      "fme_qspi_flash"
  22 #define FME_FEATURE_MAX10_SPI       "fme_max10_spi"
  23 #define FME_FEATURE_NIOS_SPI        "fme_nios_spi"
  24
  25 #define PORT_FEATURE_HEADER         "port_hdr"
  26 #define PORT_FEATURE_UAFU           "port_uafu"
  27 #define PORT_FEATURE_ERR            "port_err"
  28 #define PORT_FEATURE_UMSG           "port_umsg"
  29 #define PORT_FEATURE_PR             "port_pr"
  30 #define PORT_FEATURE_UINT           "port_uint"
  31 #define PORT_FEATURE_STP            "port_stp"
  32
  33 /*
  34  * do not check the revision id as id may be dynamic under
  35  * some cases, e.g, UAFU.
  36  */
  37 #define SKIP_REVISION_CHECK             0xff
  38
  39 #define FME_HEADER_REVISION             1
  40 #define FME_THERMAL_MGMT_REVISION       0
  41 #define FME_POWER_MGMT_REVISION         1
  42 #define FME_GLOBAL_IPERF_REVISION       1
  43 #define FME_GLOBAL_ERR_REVISION         1
  44 #define FME_PR_MGMT_REVISION            2
  45 #define FME_HSSI_ETH_REVISION           0
  46 #define FME_GLOBAL_DPERF_REVISION       0
  47 #define FME_QSPI_REVISION               0
  48 #define FME_MAX10_SPI                   0
  49
  50 #define PORT_HEADER_REVISION            0
  51 /* UAFU's header info depends on the downloaded GBS */
  52 #define PORT_UAFU_REVISION              SKIP_REVISION_CHECK
  53 #define PORT_ERR_REVISION               1
  54 #define PORT_UMSG_REVISION              0
  55 #define PORT_UINT_REVISION              0
  56 #define PORT_STP_REVISION               1
  57
  58 #define FEATURE_TYPE_AFU        0x1
  59 #define FEATURE_TYPE_BBB        0x2
  60 #define FEATURE_TYPE_PRIVATE    0x3
  61 #define FEATURE_TYPE_FIU        0x4
  62
  63 #define FEATURE_FIU_ID_FME      0x0
  64 #define FEATURE_FIU_ID_PORT     0x1
  65
  66 /* Reserved 0xfe for Header, 0xff for AFU*/
  67 #define FEATURE_ID_FIU_HEADER   0xfe
  68 #define FEATURE_ID_AFU          0xff
  69
  70 enum fpga_id_type {
  71         FME_ID,
  72         PORT_ID,
  73         FPGA_ID_MAX,
  74 };
  75
  76 #define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
  77 #define FME_FEATURE_ID_THERMAL_MGMT 0x1
  78 #define FME_FEATURE_ID_POWER_MGMT 0x2
  79 #define FME_FEATURE_ID_GLOBAL_IPERF 0x3
  80 #define FME_FEATURE_ID_GLOBAL_ERR 0x4
  81 #define FME_FEATURE_ID_PR_MGMT 0x5
  82 #define FME_FEATURE_ID_HSSI_ETH 0x6
  83 #define FME_FEATURE_ID_GLOBAL_DPERF 0x7
  84 #define FME_FEATURE_ID_QSPI_FLASH 0x8
  85 #define FME_FEATURE_ID_EMIF_MGMT  0x9
  86 #define FME_FEATURE_ID_MAX10_SPI  0xe
  87 #define FME_FEATURE_ID_NIOS_SPI 0xd
  88
  89 #define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
  90 #define PORT_FEATURE_ID_ERROR 0x10
  91 #define PORT_FEATURE_ID_UMSG 0x12
  92 #define PORT_FEATURE_ID_UINT 0x13
  93 #define PORT_FEATURE_ID_STP 0x14
  94 #define PORT_FEATURE_ID_UAFU FEATURE_ID_AFU
  95
  96 /*
  97  * All headers and structures must be byte-packed to match the spec.
  98  */
  99 #pragma pack(push, 1)
 100
 101 struct feature_header {
 102         union {
 103                 u64 csr;
 104                 struct {
 105                         u16 id:12;
 106                         u8  revision:4;
 107                         u32 next_header_offset:24;
 108                         u8  end_of_list:1;
 109                         u32 reserved:19;
 110                         u8  type:4;
 111                 };
 112         };
 113 };
 114
 115 struct feature_bbb_header {
 116         struct uuid guid;
 117 };
 118
 119 struct feature_afu_header {
 120         struct uuid guid;
 121         union {
 122                 u64 csr;
 123                 struct {
 124                         u64 next_afu:24;
 125                         u64 reserved:40;
 126                 };
 127         };
 128 };
 129
 130 struct feature_fiu_header {
 131         struct uuid guid;
 132         union {
 133                 u64 csr;
 134                 struct {
 135                         u64 next_afu:24;
 136                         u64 reserved:40;
 137                 };
 138         };
 139 };
 140
 141 struct feature_fme_capability {
 142         union {
 143                 u64 csr;
 144                 struct {
 145                         u8  fabric_verid;       /* Fabric version ID */
 146                         u8  socket_id:1;        /* Socket id */
 147                         u8  rsvd1:3;            /* Reserved */
 148                         /* pci0 link available yes /no */
 149                         u8  pci0_link_avile:1;
 150                         /* pci1 link available yes /no */
 151                         u8  pci1_link_avile:1;
 152                         /* Coherent (QPI/UPI) link available yes /no */
 153                         u8  qpi_link_avile:1;
 154                         u8  rsvd2:1;            /* Reserved */
 155                         /* IOMMU or VT-d supported  yes/no */
 156                         u8  iommu_support:1;
 157                         u8  num_ports:3;        /* Number of ports */
 158                         u8  sf_fab_ctl:1;       /* Internal validation bit */
 159                         u8  rsvd3:3;            /* Reserved */
 160                         /*
 161                          * Address width supported in bits
 162                          * BXT -0x26 , SKX -0x30
 163                          */
 164                         u8  address_width_bits:6;
 165                         u8  rsvd4:2;            /* Reserved */
 166                         /* Size of cache supported in kb */
 167                         u16 cache_size:12;
 168                         u8  cache_assoc:4;      /* Cache Associativity */
 169                         u16 rsvd5:15;           /* Reserved */
 170                         u8  lock_bit:1;         /* Lock bit */
 171                 };
 172         };
 173 };
 174
 175 #define FME_AFU_ACCESS_PF               0
 176 #define FME_AFU_ACCESS_VF               1
 177
 178 struct feature_fme_port {
 179         union {
 180                 u64 csr;
 181                 struct {
 182                         u32 port_offset:24;
 183                         u8  reserved1;
 184                         u8  port_bar:3;
 185                         u32 reserved2:20;
 186                         u8  afu_access_control:1;
 187                         u8  reserved3:4;
 188                         u8  port_implemented:1;
 189                         u8  reserved4:3;
 190                 };
 191         };
 192 };
 193
 194 struct feature_fme_fab_status {
 195         union {
 196                 u64 csr;
 197                 struct {
 198                         u8  upilink_status:4;   /* UPI Link Status */
 199                         u8  rsvd1:4;            /* Reserved */
 200                         u8  pci0link_status:1;  /* pci0 link status */
 201                         u8  rsvd2:3;            /* Reserved */
 202                         u8  pci1link_status:1;  /* pci1 link status */
 203                         u64 rsvd3:51;           /* Reserved */
 204                 };
 205         };
 206 };
 207
 208 struct feature_fme_genprotrange2_base {
 209         union {
 210                 u64 csr;
 211                 struct {
 212                         u16 rsvd1;           /* Reserved */
 213                         /* Base Address of memory range */
 214                         u8  protected_base_addrss:4;
 215                         u64 rsvd2:44;           /* Reserved */
 216                 };
 217         };
 218 };
 219
 220 struct feature_fme_genprotrange2_limit {
 221         union {
 222                 u64 csr;
 223                 struct {
 224                         u16 rsvd1;           /* Reserved */
 225                         /* Limit Address of memory range */
 226                         u8  protected_limit_addrss:4;
 227                         u16 rsvd2:11;           /* Reserved */
 228                         u8  enable:1;        /* Enable GENPROTRANGE check */
 229                         u32 rsvd3;           /* Reserved */
 230                 };
 231         };
 232 };
 233
 234 struct feature_fme_dxe_lock {
 235         union {
 236                 u64 csr;
 237                 struct {
 238                         /*
 239                          * Determines write access to the DXE region CSRs
 240                          * 1 - CSR region is locked;
 241                          * 0 - it is open for write access.
 242                          */
 243                         u8  dxe_early_lock:1;
 244                         /*
 245                          * Determines write access to the HSSI CSR
 246                          * 1 - CSR region is locked;
 247                          * 0 - it is open for write access.
 248                          */
 249                         u8  dxe_late_lock:1;
 250                         u64 rsvd:62;
 251                 };
 252         };
 253 };
 254
 255 #define HSSI_ID_NO_HASSI        0
 256 #define HSSI_ID_PCIE_RP         1
 257 #define HSSI_ID_ETHERNET        2
 258
 259 struct feature_fme_bitstream_id {
 260         union {
 261                 u64 csr;
 262                 struct {
 263                         u32 gitrepo_hash:32;    /* GIT repository hash */
 264                         /*
 265                          * HSSI configuration identifier:
 266                          * 0 - No HSSI
 267                          * 1 - PCIe-RP
 268                          * 2 - Ethernet
 269                          */
 270                         u8  hssi_id:4;
 271                         u16 rsvd1:12;           /* Reserved */
 272                         /* Bitstream version patch number */
 273                         u8  bs_verpatch:4;
 274                         /* Bitstream version minor number */
 275                         u8  bs_verminor:4;
 276                         /* Bitstream version major number */
 277                         u8  bs_vermajor:4;
 278                         /* Bitstream version debug number */
 279                         u8  bs_verdebug:4;
 280                 };
 281         };
 282 };
 283
 284 struct feature_fme_bitstream_md {
 285         union {
 286                 u64 csr;
 287                 struct {
 288                         /* Seed number userd for synthesis flow */
 289                         u8  synth_seed:4;
 290                         /* Synthesis date(day number - 2 digits) */
 291                         u8  synth_day:8;
 292                         /* Synthesis date(month number - 2 digits) */
 293                         u8  synth_month:8;
 294                         /* Synthesis date(year number - 2 digits) */
 295                         u8  synth_year:8;
 296                         u64 rsvd:36;            /* Reserved */
 297                 };
 298         };
 299 };
 300
 301 struct feature_fme_iommu_ctrl {
 302         union {
 303                 u64 csr;
 304                 struct {
 305                         /* Disables IOMMU prefetcher for C0 channel */
 306                         u8 prefetch_disableC0:1;
 307                         /* Disables IOMMU prefetcher for C1 channel */
 308                         u8 prefetch_disableC1:1;
 309                         /* Disables IOMMU partial cache line writes */
 310                         u8 prefetch_wrdisable:1;
 311                         u8 rsvd1:1;             /* Reserved */
 312                         /*
 313                          * Select counter and read value from register
 314                          * iommu_stat.dbg_counters
 315                          * 0 - Number of 4K page translation response
 316                          * 1 - Number of 2M page translation response
 317                          * 2 - Number of 1G page translation response
 318                          */
 319                         u8 counter_sel:2;
 320                         u32 rsvd2:26;           /* Reserved */
 321                         /* Connected to IOMMU SIP Capabilities */
 322                         u32 capecap_defeature;
 323                 };
 324         };
 325 };
 326
 327 struct feature_fme_iommu_stat {
 328         union {
 329                 u64 csr;
 330                 struct {
 331                         /* Translation Enable bit from IOMMU SIP */
 332                         u8 translation_enable:1;
 333                         /* Drain request in progress */
 334                         u8 drain_req_inprog:1;
 335                         /* Invalidation current state */
 336                         u8 inv_state:3;
 337                         /* C0 Response Buffer current state */
 338                         u8 respbuffer_stateC0:3;
 339                         /* C1 Response Buffer current state */
 340                         u8 respbuffer_stateC1:3;
 341                         /* Last request ID to IOMMU SIP */
 342                         u8 last_reqID:4;
 343                         /* Last IOMMU SIP response ID value */
 344                         u8 last_respID:4;
 345                         /* Last IOMMU SIP response status value */
 346                         u8 last_respstatus:3;
 347                         /* C0 Transaction Buffer is not empty */
 348                         u8 transbuf_notEmptyC0:1;
 349                         /* C1 Transaction Buffer is not empty */
 350                         u8 transbuf_notEmptyC1:1;
 351                         /* C0 Request FIFO is not empty */
 352                         u8 reqFIFO_notemptyC0:1;
 353                         /* C1 Request FIFO is not empty */
 354                         u8 reqFIFO_notemptyC1:1;
 355                         /* C0 Response FIFO is not empty */
 356                         u8 respFIFO_notemptyC0:1;
 357                         /* C1 Response FIFO is not empty */
 358                         u8 respFIFO_notemptyC1:1;
 359                         /* C0 Response FIFO overflow detected */
 360                         u8 respFIFO_overflowC0:1;
 361                         /* C1 Response FIFO overflow detected */
 362                         u8 respFIFO_overflowC1:1;
 363                         /* C0 Transaction Buffer overflow detected */
 364                         u8 tranbuf_overflowC0:1;
 365                         /* C1 Transaction Buffer overflow detected */
 366                         u8 tranbuf_overflowC1:1;
 367                         /* Request FIFO overflow detected */
 368                         u8 reqFIFO_overflow:1;
 369                         /* IOMMU memory read in progress */
 370                         u8 memrd_inprog:1;
 371                         /* IOMMU memory write in progress */
 372                         u8 memwr_inprog:1;
 373                         u8 rsvd1:1;     /* Reserved */
 374                         /* Value of counter selected by iommu_ctl.counter_sel */
 375                         u16 dbg_counters:16;
 376                         u16 rsvd2:12;   /* Reserved */
 377                 };
 378         };
 379 };
 380
 381 struct feature_fme_pcie0_ctrl {
 382         union {
 383                 u64 csr;
 384                 struct {
 385                         u64 vtd_bar_lock:1;     /* Lock VT-D BAR register */
 386                         u64 rsvd1:3;
 387                         u64 rciep:1;            /* Configure PCIE0 as RCiEP */
 388                         u64 rsvd2:59;
 389                 };
 390         };
 391 };
 392
 393 struct feature_fme_llpr_smrr_base {
 394         union {
 395                 u64 csr;
 396                 struct {
 397                         u64 rsvd1:12;
 398                         u64 base:20;    /* SMRR2 memory range base address */
 399                         u64 rsvd2:32;
 400                 };
 401         };
 402 };
 403
 404 struct feature_fme_llpr_smrr_mask {
 405         union {
 406                 u64 csr;
 407                 struct {
 408                         u64 rsvd1:11;
 409                         u64 valid:1;    /* LLPR_SMRR rule is valid or not */
 410                         /*
 411                          * SMRR memory range mask which determines the range
 412                          * of region being mapped
 413                          */
 414                         u64 phys_mask:20;
 415                         u64 rsvd2:32;
 416                 };
 417         };
 418 };
 419
 420 struct feature_fme_llpr_smrr2_base {
 421         union {
 422                 u64 csr;
 423                 struct {
 424                         u64 rsvd1:12;
 425                         u64 base:20;    /* SMRR2 memory range base address */
 426                         u64 rsvd2:32;
 427                 };
 428         };
 429 };
 430
 431 struct feature_fme_llpr_smrr2_mask {
 432         union {
 433                 u64 csr;
 434                 struct {
 435                         u64 rsvd1:11;
 436                         u64 valid:1;    /* LLPR_SMRR2 rule is valid or not */
 437                         /*
 438                          * SMRR2 memory range mask which determines the range
 439                          * of region being mapped
 440                          */
 441                         u64 phys_mask:20;
 442                         u64 rsvd2:32;
 443                 };
 444         };
 445 };
 446
 447 struct feature_fme_llpr_meseg_base {
 448         union {
 449                 u64 csr;
 450                 struct {
 451                         /* A[45:19] of base address memory range */
 452                         u64 me_base:27;
 453                         u64 rsvd:37;
 454                 };
 455         };
 456 };
 457
 458 struct feature_fme_llpr_meseg_limit {
 459         union {
 460                 u64 csr;
 461                 struct {
 462                         /* A[45:19] of limit address memory range */
 463                         u64 me_limit:27;
 464                         u64 rsvd1:4;
 465                         u64 enable:1;   /* Enable LLPR MESEG rule */
 466                         u64 rsvd2:32;
 467                 };
 468         };
 469 };
 470
 471 struct feature_fme_header {
 472         struct feature_header header;
 473         struct feature_afu_header afu_header;
 474         u64 reserved;
 475         u64 scratchpad;
 476         struct feature_fme_capability capability;
 477         struct feature_fme_port port[MAX_FPGA_PORT_NUM];
 478         struct feature_fme_fab_status fab_status;
 479         struct feature_fme_bitstream_id bitstream_id;
 480         struct feature_fme_bitstream_md bitstream_md;
 481         struct feature_fme_genprotrange2_base genprotrange2_base;
 482         struct feature_fme_genprotrange2_limit genprotrange2_limit;
 483         struct feature_fme_dxe_lock dxe_lock;
 484         struct feature_fme_iommu_ctrl iommu_ctrl;
 485         struct feature_fme_iommu_stat iommu_stat;
 486         struct feature_fme_pcie0_ctrl pcie0_control;
 487         struct feature_fme_llpr_smrr_base smrr_base;
 488         struct feature_fme_llpr_smrr_mask smrr_mask;
 489         struct feature_fme_llpr_smrr2_base smrr2_base;
 490         struct feature_fme_llpr_smrr2_mask smrr2_mask;
 491         struct feature_fme_llpr_meseg_base meseg_base;
 492         struct feature_fme_llpr_meseg_limit meseg_limit;
 493 };
 494
 495 struct feature_port_capability {
 496         union {
 497                 u64 csr;
 498                 struct {
 499                         u8 port_number:2;       /* Port Number 0-3 */
 500                         u8 rsvd1:6;             /* Reserved */
 501                         u16 mmio_size;          /* User MMIO size in KB */
 502                         u8 rsvd2;               /* Reserved */
 503                         u8 sp_intr_num:4;       /* Supported interrupts num */
 504                         u32 rsvd3:28;           /* Reserved */
 505                 };
 506         };
 507 };
 508
 509 struct feature_port_control {
 510         union {
 511                 u64 csr;
 512                 struct {
 513                         u8 port_sftrst:1;       /* Port Soft Reset */
 514                         u8 rsvd1:1;             /* Reserved */
 515                         u8 latency_tolerance:1;/* '1' >= 40us, '0' < 40us */
 516                         u8 rsvd2:1;             /* Reserved */
 517                         u8 port_sftrst_ack:1;   /* HW ACK for Soft Reset */
 518                         u64 rsvd3:59;           /* Reserved */
 519                 };
 520         };
 521 };
 522
 523 #define PORT_POWER_STATE_NORMAL         0
 524 #define PORT_POWER_STATE_AP1            1
 525 #define PORT_POWER_STATE_AP2            2
 526 #define PORT_POWER_STATE_AP6            6
 527
 528 struct feature_port_status {
 529         union {
 530                 u64 csr;
 531                 struct {
 532                         u8 port_freeze:1;       /* '1' - freezed '0' - normal */
 533                         u8 rsvd1:7;             /* Reserved */
 534                         u8 power_state:4;       /* Power State */
 535                         u8 ap1_event:1;         /* AP1 event was detected  */
 536                         u8 ap2_event:1;         /* AP2 event was detected  */
 537                         u64 rsvd2:50;           /* Reserved */
 538                 };
 539         };
 540 };
 541
 542 /* Port Header Register Set */
 543 struct feature_port_header {
 544         struct feature_header header;
 545         struct feature_afu_header afu_header;
 546         u64 port_mailbox;
 547         u64 scratchpad;
 548         struct feature_port_capability capability;
 549         struct feature_port_control control;
 550         struct feature_port_status status;
 551         u64 rsvd2;
 552         u64 user_clk_freq_cmd0;
 553         u64 user_clk_freq_cmd1;
 554         u64 user_clk_freq_sts0;
 555         u64 user_clk_freq_sts1;
 556 };
 557
 558 struct feature_fme_tmp_threshold {
 559         union {
 560                 u64 csr;
 561                 struct {
 562                         u8  tmp_thshold1:7;       /* temperature Threshold 1 */
 563                         /* temperature Threshold 1 enable/disable */
 564                         u8  tmp_thshold1_enable:1;
 565                         u8  tmp_thshold2:7;       /* temperature Threshold 2 */
 566                         /* temperature Threshold 2 enable /disable */
 567                         u8  tmp_thshold2_enable:1;
 568                         u8  pro_hot_setpoint:7;   /* Proc Hot set point */
 569                         u8  rsvd4:1;              /* Reserved */
 570                         u8  therm_trip_thshold:7; /* Thermeal Trip Threshold */
 571                         u8  rsvd3:1;              /* Reserved */
 572                         u8  thshold1_status:1;    /* Threshold 1 Status */
 573                         u8  thshold2_status:1;    /* Threshold 2 Status */
 574                         u8  rsvd5:1;              /* Reserved */
 575                         /* Thermeal Trip Threshold status */
 576                         u8  therm_trip_thshold_status:1;
 577                         u8  rsvd6:4;              /* Reserved */
 578                         /* Validation mode- Force Proc Hot */
 579                         u8  valmodeforce:1;
 580                         /* Validation mode - Therm trip Hot */
 581                         u8  valmodetherm:1;
 582                         u8  rsvd2:2;              /* Reserved */
 583                         u8  thshold_policy:1;     /* threshold policy */
 584                         u32 rsvd:19;              /* Reserved */
 585                 };
 586         };
 587 };
 588
 589 /* Temperature Sensor Read values format 1 */
 590 struct feature_fme_temp_rdsensor_fmt1 {
 591         union {
 592                 u64 csr;
 593                 struct {
 594                         /* Reads out FPGA temperature in celsius */
 595                         u8  fpga_temp:7;
 596                         u8  rsvd0:1;                    /* Reserved */
 597                         /* Temperature reading sequence number */
 598                         u16 tmp_reading_seq_num;
 599                         /* Temperature reading is valid */
 600                         u8  tmp_reading_valid:1;
 601                         u8  rsvd1:7;                    /* Reserved */
 602                         u16 dbg_mode:10;                /* Debug mode */
 603                         u32 rsvd2:22;                   /* Reserved */
 604                 };
 605         };
 606 };
 607
 608 /* Temperature sensor read values format 2 */
 609 struct feature_fme_temp_rdsensor_fmt2 {
 610         u64 rsvd;       /* Reserved */
 611 };
 612
 613 /* Temperature Threshold Capability Register */
 614 struct feature_fme_tmp_threshold_cap {
 615         union {
 616                 u64 csr;
 617                 struct {
 618                         /* Temperature Threshold Unsupported */
 619                         u8  tmp_thshold_disabled:1;
 620                         u64 rsvd:63;                    /* Reserved */
 621                 };
 622         };
 623 };
 624
 625 /* FME THERNAL FEATURE */
 626 struct feature_fme_thermal {
 627         struct feature_header header;
 628         struct feature_fme_tmp_threshold threshold;
 629         struct feature_fme_temp_rdsensor_fmt1 rdsensor_fm1;
 630         struct feature_fme_temp_rdsensor_fmt2 rdsensor_fm2;
 631         struct feature_fme_tmp_threshold_cap threshold_cap;
 632 };
 633
 634 /* Power Status register */
 635 struct feature_fme_pm_status {
 636         union {
 637                 u64 csr;
 638                 struct {
 639                         /* FPGA Power consumed, The format is to be defined */
 640                         u32 pwr_consumed:18;
 641                         /* FPGA Latency Tolerance Reporting */
 642                         u8  fpga_latency_report:1;
 643                         u64 rsvd:45;                    /* Reserved */
 644                 };
 645         };
 646 };
 647
 648 /* AP Thresholds */
 649 struct feature_fme_pm_ap_threshold {
 650         union {
 651                 u64 csr;
 652                 struct {
 653                         /*
 654                          * Number of clocks (5ns period) for assertion
 655                          * of FME_data
 656                          */
 657                         u8  threshold1:7;
 658                         u8  rsvd1:1;
 659                         u8  threshold2:7;
 660                         u8  rsvd2:1;
 661                         u8  threshold1_status:1;
 662                         u8  threshold2_status:1;
 663                         u64 rsvd3:46;           /* Reserved */
 664                 };
 665         };
 666 };
 667
 668 /* Xeon Power Limit */
 669 struct feature_fme_pm_xeon_limit {
 670         union {
 671                 u64 csr;
 672                 struct {
 673                         /* Power limit in Watts in 12.3 format */
 674                         u16 pwr_limit:15;
 675                         /* Indicates that power limit has been written */
 676                         u8  enable:1;
 677                         /* 0 - Turbe range, 1 - Entire range */
 678                         u8  clamping:1;
 679                         /* Time constant in XXYYY format */
 680                         u8  time:7;
 681                         u64 rsvd:40;            /* Reserved */
 682                 };
 683         };
 684 };
 685
 686 /* FPGA Power Limit */
 687 struct feature_fme_pm_fpga_limit {
 688         union {
 689                 u64 csr;
 690                 struct {
 691                         /* Power limit in Watts in 12.3 format */
 692                         u16 pwr_limit:15;
 693                         /* Indicates that power limit has been written */
 694                         u8  enable:1;
 695                         /* 0 - Turbe range, 1 - Entire range */
 696                         u8  clamping:1;
 697                         /* Time constant in XXYYY format */
 698                         u8  time:7;
 699                         u64 rsvd:40;            /* Reserved */
 700                 };
 701         };
 702 };
 703
 704 /* FME POWER FEATURE */
 705 struct feature_fme_power {
 706         struct feature_header header;
 707         struct feature_fme_pm_status status;
 708         struct feature_fme_pm_ap_threshold threshold;
 709         struct feature_fme_pm_xeon_limit xeon_limit;
 710         struct feature_fme_pm_fpga_limit fpga_limit;
 711 };
 712
 713 #define CACHE_CHANNEL_RD        0
 714 #define CACHE_CHANNEL_WR        1
 715
 716 enum iperf_cache_events {
 717         IPERF_CACHE_RD_HIT,
 718         IPERF_CACHE_WR_HIT,
 719         IPERF_CACHE_RD_MISS,
 720         IPERF_CACHE_WR_MISS,
 721         IPERF_CACHE_RSVD, /* reserved */
 722         IPERF_CACHE_HOLD_REQ,
 723         IPERF_CACHE_DATA_WR_PORT_CONTEN,
 724         IPERF_CACHE_TAG_WR_PORT_CONTEN,
 725         IPERF_CACHE_TX_REQ_STALL,
 726         IPERF_CACHE_RX_REQ_STALL,
 727         IPERF_CACHE_EVICTIONS,
 728 };
 729
 730 /* FPMON Cache Control */
 731 struct feature_fme_ifpmon_ch_ctl {
 732         union {
 733                 u64 csr;
 734                 struct {
 735                         u8  reset_counters:1;   /* Reset Counters */
 736                         u8  rsvd1:7;            /* Reserved */
 737                         u8  freeze:1;           /* Freeze if set to 1 */
 738                         u8  rsvd2:7;            /* Reserved */
 739                         u8  cache_event:4;      /* Select the cache event */
 740                         u8  cci_chsel:1;        /* Select the channel */
 741                         u64 rsvd3:43;           /* Reserved */
 742                 };
 743         };
 744 };
 745
 746 /* FPMON Cache Counter */
 747 struct feature_fme_ifpmon_ch_ctr {
 748         union {
 749                 u64 csr;
 750                 struct {
 751                         /* Cache Counter for even addresse */
 752                         u64 cache_counter:48;
 753                         u16 rsvd:12;            /* Reserved */
 754                         /* Cache Event being reported */
 755                         u8  event_code:4;
 756                 };
 757         };
 758 };
 759
 760 enum iperf_fab_events {
 761         IPERF_FAB_PCIE0_RD,
 762         IPERF_FAB_PCIE0_WR,
 763         IPERF_FAB_PCIE1_RD,
 764         IPERF_FAB_PCIE1_WR,
 765         IPERF_FAB_UPI_RD,
 766         IPERF_FAB_UPI_WR,
 767         IPERF_FAB_MMIO_RD,
 768         IPERF_FAB_MMIO_WR,
 769 };
 770
 771 #define FAB_DISABLE_FILTER     0
 772 #define FAB_ENABLE_FILTER      1
 773
 774 /* FPMON FAB Control */
 775 struct feature_fme_ifpmon_fab_ctl {
 776         union {
 777                 u64 csr;
 778                 struct {
 779                         u8  reset_counters:1;   /* Reset Counters */
 780                         u8  rsvd:7;             /* Reserved */
 781                         u8  freeze:1;           /* Set to 1 frozen counter */
 782                         u8  rsvd1:7;            /* Reserved */
 783                         u8  fab_evtcode:4;      /* Fabric Event Code */
 784                         u8  port_id:2;          /* Port ID */
 785                         u8  rsvd2:1;            /* Reserved */
 786                         u8  port_filter:1;      /* Port Filter */
 787                         u64 rsvd3:40;           /* Reserved */
 788                 };
 789         };
 790 };
 791
 792 /* FPMON Event Counter */
 793 struct feature_fme_ifpmon_fab_ctr {
 794         union {
 795                 u64 csr;
 796                 struct {
 797                         u64 fab_cnt:60; /* Fabric event counter */
 798                         /* Fabric event code being reported */
 799                         u8  event_code:4;
 800                 };
 801         };
 802 };
 803
 804 /* FPMON Clock Counter */
 805 struct feature_fme_ifpmon_clk_ctr {
 806         u64 afu_interf_clock;           /* Clk_16UI (AFU clock) counter. */
 807 };
 808
 809 enum iperf_vtd_events {
 810         IPERF_VTD_AFU_MEM_RD_TRANS,
 811         IPERF_VTD_AFU_MEM_WR_TRANS,
 812         IPERF_VTD_AFU_DEVTLB_RD_HIT,
 813         IPERF_VTD_AFU_DEVTLB_WR_HIT,
 814         IPERF_VTD_DEVTLB_4K_FILL,
 815         IPERF_VTD_DEVTLB_2M_FILL,
 816         IPERF_VTD_DEVTLB_1G_FILL,
 817 };
 818
 819 /* VT-d control register */
 820 struct feature_fme_ifpmon_vtd_ctl {
 821         union {
 822                 u64 csr;
 823                 struct {
 824                         u8  reset_counters:1;   /* Reset Counters */
 825                         u8  rsvd:7;             /* Reserved */
 826                         u8  freeze:1;           /* Set to 1 frozen counter */
 827                         u8  rsvd1:7;            /* Reserved */
 828                         u8  vtd_evtcode:4;      /* VTd and TLB event code */
 829                         u64 rsvd2:44;           /* Reserved */
 830                 };
 831         };
 832 };
 833
 834 /* VT-d event counter */
 835 struct feature_fme_ifpmon_vtd_ctr {
 836         union {
 837                 u64 csr;
 838                 struct {
 839                         u64 vtd_counter:48;     /* VTd event counter */
 840                         u16 rsvd:12;            /* Reserved */
 841                         u8  event_code:4;       /* VTd event code */
 842                 };
 843         };
 844 };
 845
 846 enum iperf_vtd_sip_events {
 847         IPERF_VTD_SIP_IOTLB_4K_HIT,
 848         IPERF_VTD_SIP_IOTLB_2M_HIT,
 849         IPERF_VTD_SIP_IOTLB_1G_HIT,
 850         IPERF_VTD_SIP_SLPWC_L3_HIT,
 851         IPERF_VTD_SIP_SLPWC_L4_HIT,
 852         IPERF_VTD_SIP_RCC_HIT,
 853         IPERF_VTD_SIP_IOTLB_4K_MISS,
 854         IPERF_VTD_SIP_IOTLB_2M_MISS,
 855         IPERF_VTD_SIP_IOTLB_1G_MISS,
 856         IPERF_VTD_SIP_SLPWC_L3_MISS,
 857         IPERF_VTD_SIP_SLPWC_L4_MISS,
 858         IPERF_VTD_SIP_RCC_MISS,
 859 };
 860
 861 /* VT-d SIP control register */
 862 struct feature_fme_ifpmon_vtd_sip_ctl {
 863         union {
 864                 u64 csr;
 865                 struct {
 866                         u8  reset_counters:1;   /* Reset Counters */
 867                         u8  rsvd:7;             /* Reserved */
 868                         u8  freeze:1;           /* Set to 1 frozen counter */
 869                         u8  rsvd1:7;            /* Reserved */
 870                         u8  vtd_evtcode:4;      /* VTd and TLB event code */
 871                         u64 rsvd2:44;           /* Reserved */
 872                 };
 873         };
 874 };
 875
 876 /* VT-d SIP event counter */
 877 struct feature_fme_ifpmon_vtd_sip_ctr {
 878         union {
 879                 u64 csr;
 880                 struct {
 881                         u64 vtd_counter:48;     /* VTd event counter */
 882                         u16 rsvd:12;            /* Reserved */
 883                         u8 event_code:4;        /* VTd event code */
 884                 };
 885         };
 886 };
 887
 888 /* FME IPERF FEATURE */
 889 struct feature_fme_iperf {
 890         struct feature_header header;
 891         struct feature_fme_ifpmon_ch_ctl ch_ctl;
 892         struct feature_fme_ifpmon_ch_ctr ch_ctr0;
 893         struct feature_fme_ifpmon_ch_ctr ch_ctr1;
 894         struct feature_fme_ifpmon_fab_ctl fab_ctl;
 895         struct feature_fme_ifpmon_fab_ctr fab_ctr;
 896         struct feature_fme_ifpmon_clk_ctr clk;
 897         struct feature_fme_ifpmon_vtd_ctl vtd_ctl;
 898         struct feature_fme_ifpmon_vtd_ctr vtd_ctr;
 899         struct feature_fme_ifpmon_vtd_sip_ctl vtd_sip_ctl;
 900         struct feature_fme_ifpmon_vtd_sip_ctr vtd_sip_ctr;
 901 };
 902
 903 enum dperf_fab_events {
 904         DPERF_FAB_PCIE0_RD,
 905         DPERF_FAB_PCIE0_WR,
 906         DPERF_FAB_MMIO_RD = 6,
 907         DPERF_FAB_MMIO_WR,
 908 };
 909
 910 /* FPMON FAB Control */
 911 struct feature_fme_dfpmon_fab_ctl {
 912         union {
 913                 u64 csr;
 914                 struct {
 915                         u8  reset_counters:1;   /* Reset Counters */
 916                         u8  rsvd:7;             /* Reserved */
 917                         u8  freeze:1;           /* Set to 1 frozen counter */
 918                         u8  rsvd1:7;            /* Reserved */
 919                         u8  fab_evtcode:4;      /* Fabric Event Code */
 920                         u8  port_id:2;          /* Port ID */
 921                         u8  rsvd2:1;            /* Reserved */
 922                         u8  port_filter:1;      /* Port Filter */
 923                         u64 rsvd3:40;           /* Reserved */
 924                 };
 925         };
 926 };
 927
 928 /* FPMON Event Counter */
 929 struct feature_fme_dfpmon_fab_ctr {
 930         union {
 931                 u64 csr;
 932                 struct {
 933                         u64 fab_cnt:60; /* Fabric event counter */
 934                         /* Fabric event code being reported */
 935                         u8  event_code:4;
 936                 };
 937         };
 938 };
 939
 940 /* FPMON Clock Counter */
 941 struct feature_fme_dfpmon_clk_ctr {
 942         u64 afu_interf_clock;           /* Clk_16UI (AFU clock) counter. */
 943 };
 944
 945 /* FME DPERF FEATURE */
 946 struct feature_fme_dperf {
 947         struct feature_header header;
 948         u64 rsvd[3];
 949         struct feature_fme_dfpmon_fab_ctl fab_ctl;
 950         struct feature_fme_dfpmon_fab_ctr fab_ctr;
 951         struct feature_fme_dfpmon_clk_ctr clk;
 952 };
 953
 954 struct feature_fme_error0 {
 955 #define FME_ERROR0_MASK        0xFFUL
 956 #define FME_ERROR0_MASK_DEFAULT 0x40UL  /* pcode workaround */
 957         union {
 958                 u64 csr;
 959                 struct {
 960                         u8  fabric_err:1;       /* Fabric error */
 961                         u8  fabfifo_overflow:1; /* Fabric fifo overflow */
 962                         u8  kticdc_parity_err:2;/* KTI CDC Parity Error */
 963                         u8  iommu_parity_err:1; /* IOMMU Parity error */
 964                         /* AFU PF/VF access mismatch detected */
 965                         u8  afu_acc_mode_err:1;
 966                         u8  mbp_err:1;          /* Indicates an MBP event */
 967                         /* PCIE0 CDC Parity Error */
 968                         u8  pcie0cdc_parity_err:5;
 969                         /* PCIE1 CDC Parity Error */
 970                         u8  pcie1cdc_parity_err:5;
 971                         /* CVL CDC Parity Error */
 972                         u8  cvlcdc_parity_err:3;
 973                         u64 rsvd:44;            /* Reserved */
 974                 };
 975         };
 976 };
 977
 978 /* PCIe0 Error Status register */
 979 struct feature_fme_pcie0_error {
 980 #define FME_PCIE0_ERROR_MASK   0xFFUL
 981         union {
 982                 u64 csr;
 983                 struct {
 984                         u8  formattype_err:1;   /* TLP format/type error */
 985                         u8  MWAddr_err:1;       /* TLP MW address error */
 986                         u8  MWAddrLength_err:1; /* TLP MW length error */
 987                         u8  MRAddr_err:1;       /* TLP MR address error */
 988                         u8  MRAddrLength_err:1; /* TLP MR length error */
 989                         u8  cpl_tag_err:1;      /* TLP CPL tag error */
 990                         u8  cpl_status_err:1;   /* TLP CPL status error */
 991                         u8  cpl_timeout_err:1;  /* TLP CPL timeout */
 992                         u8  cci_parity_err:1;   /* CCI bridge parity error */
 993                         u8  rxpoison_tlp_err:1; /* Received a TLP with EP set */
 994                         u64 rsvd:52;            /* Reserved */
 995                         u8  vfnumb_err:1;       /* Number of error VF */
 996                         u8  funct_type_err:1;   /* Virtual (1) or Physical */
 997                 };
 998         };
 999 };
1000
1001 /* PCIe1 Error Status register */
1002 struct feature_fme_pcie1_error {
1003 #define FME_PCIE1_ERROR_MASK   0xFFUL
1004         union {
1005                 u64 csr;
1006                 struct {
1007                         u8  formattype_err:1;   /* TLP format/type error */
1008                         u8  MWAddr_err:1;       /* TLP MW address error */
1009                         u8  MWAddrLength_err:1; /* TLP MW length error */
1010                         u8  MRAddr_err:1;       /* TLP MR address error */
1011                         u8  MRAddrLength_err:1; /* TLP MR length error */
1012                         u8  cpl_tag_err:1;      /* TLP CPL tag error */
1013                         u8  cpl_status_err:1;   /* TLP CPL status error */
1014                         u8  cpl_timeout_err:1;  /* TLP CPL timeout */
1015                         u8  cci_parity_err:1;   /* CCI bridge parity error */
1016                         u8  rxpoison_tlp_err:1; /* Received a TLP with EP set */
1017                         u64 rsvd:54;            /* Reserved */
1018                 };
1019         };
1020 };
1021
1022 /* FME First Error register */
1023 struct feature_fme_first_error {
1024 #define FME_FIRST_ERROR_MASK   ((1ULL << 60) - 1)
1025         union {
1026                 u64 csr;
1027                 struct {
1028                         /*
1029                          * Indicates the Error Register that was
1030                          * triggered first
1031                          */
1032                         u64 err_reg_status:60;
1033                         /*
1034                          * Holds 60 LSBs from the Error register that was
1035                          * triggered first
1036                          */
1037                         u8 errReg_id:4;
1038                 };
1039         };
1040 };
1041
1042 /* FME Next Error register */
1043 struct feature_fme_next_error {
1044 #define FME_NEXT_ERROR_MASK    ((1ULL << 60) - 1)
1045         union {
1046                 u64 csr;
1047                 struct {
1048                         /*
1049                          * Indicates the Error Register that was
1050                          * triggered second
1051                          */
1052                         u64 err_reg_status:60;
1053                         /*
1054                          * Holds 60 LSBs from the Error register that was
1055                          * triggered second
1056                          */
1057                         u8  errReg_id:4;
1058                 };
1059         };
1060 };
1061
1062 /* RAS Non Fatal Error Status register */
1063 struct feature_fme_ras_nonfaterror {
1064         union {
1065                 u64 csr;
1066                 struct {
1067                         /* thremal threshold AP1 */
1068                         u8  temp_thresh_ap1:1;
1069                         /* thremal threshold AP2 */
1070                         u8  temp_thresh_ap2:1;
1071                         u8  pcie_error:1;       /* pcie Error */
1072                         u8  portfatal_error:1;  /* port fatal error */
1073                         u8  proc_hot:1;         /* Indicates a ProcHot event */
1074                         /* Indicates an AFU PF/VF access mismatch */
1075                         u8  afu_acc_mode_err:1;
1076                         /* Injected nonfata Error */
1077                         u8  injected_nonfata_err:1;
1078                         u8  rsvd1:2;
1079                         /* Temperature threshold triggered AP6*/
1080                         u8  temp_thresh_AP6:1;
1081                         /* Power threshold triggered AP1 */
1082                         u8  power_thresh_AP1:1;
1083                         /* Power threshold triggered AP2 */
1084                         u8  power_thresh_AP2:1;
1085                         /* Indicates a MBP event */
1086                         u8  mbp_err:1;
1087                         u64 rsvd2:51;           /* Reserved */
1088                 };
1089         };
1090 };
1091
1092 /* RAS Catastrophic Fatal Error Status register */
1093 struct feature_fme_ras_catfaterror {
1094         union {
1095                 u64 csr;
1096                 struct {
1097                         /* KTI Link layer error detected */
1098                         u8  ktilink_fatal_err:1;
1099                         /* tag-n-cache error detected */
1100                         u8  tagcch_fatal_err:1;
1101                         /* CCI error detected */
1102                         u8  cci_fatal_err:1;
1103                         /* KTI Protocol error detected */
1104                         u8  ktiprpto_fatal_err:1;
1105                         /* Fatal DRAM error detected */
1106                         u8  dram_fatal_err:1;
1107                         /* IOMMU detected */
1108                         u8  iommu_fatal_err:1;
1109                         /* Fabric Fatal Error */
1110                         u8  fabric_fatal_err:1;
1111                         /* PCIe possion Error */
1112                         u8  pcie_poison_err:1;
1113                         /* Injected fatal Error */
1114                         u8  inject_fata_err:1;
1115                         /* Catastrophic CRC Error */
1116                         u8  crc_catast_err:1;
1117                         /* Catastrophic Thermal Error */
1118                         u8  therm_catast_err:1;
1119                         /* Injected Catastrophic Error */
1120                         u8  injected_catast_err:1;
1121                         u64 rsvd:52;
1122                 };
1123         };
1124 };
1125
1126 /* RAS Error injection register */
1127 struct feature_fme_ras_error_inj {
1128 #define FME_RAS_ERROR_INJ_MASK      0x7UL
1129         union {
1130                 u64 csr;
1131                 struct {
1132                         u8  catast_error:1;     /* Catastrophic error flag */
1133                         u8  fatal_error:1;      /* Fatal error flag */
1134                         u8  nonfatal_error:1;   /* NonFatal error flag */
1135                         u64 rsvd:61;            /* Reserved */
1136                 };
1137         };
1138 };
1139
1140 /* FME error capabilities */
1141 struct feature_fme_error_capability {
1142         union {
1143         u64 csr;
1144                 struct {
1145                         u8 support_intr:1;
1146                         /* MSI-X vector table entry number */
1147                         u16 intr_vector_num:12;
1148                         u64 rsvd:51;    /* Reserved */
1149                 };
1150         };
1151 };
1152
1153 /* FME ERR FEATURE */
1154 struct feature_fme_err {
1155         struct feature_header header;
1156         struct feature_fme_error0 fme_err_mask;
1157         struct feature_fme_error0 fme_err;
1158         struct feature_fme_pcie0_error pcie0_err_mask;
1159         struct feature_fme_pcie0_error pcie0_err;
1160         struct feature_fme_pcie1_error pcie1_err_mask;
1161         struct feature_fme_pcie1_error pcie1_err;
1162         struct feature_fme_first_error fme_first_err;
1163         struct feature_fme_next_error fme_next_err;
1164         struct feature_fme_ras_nonfaterror ras_nonfat_mask;
1165         struct feature_fme_ras_nonfaterror ras_nonfaterr;
1166         struct feature_fme_ras_catfaterror ras_catfat_mask;
1167         struct feature_fme_ras_catfaterror ras_catfaterr;
1168         struct feature_fme_ras_error_inj ras_error_inj;
1169         struct feature_fme_error_capability fme_err_capability;
1170 };
1171
1172 /* FME Partial Reconfiguration Control */
1173 struct feature_fme_pr_ctl {
1174         union {
1175                 u64 csr;
1176                 struct {
1177                         u8  pr_reset:1;         /* Reset PR Engine */
1178                         u8  rsvd3:3;            /* Reserved */
1179                         u8  pr_reset_ack:1;     /* Reset PR Engine Ack */
1180                         u8  rsvd4:3;            /* Reserved */
1181                         u8  pr_regionid:2;      /* PR Region ID */
1182                         u8  rsvd1:2;            /* Reserved */
1183                         u8  pr_start_req:1;     /* PR Start Request */
1184                         u8  pr_push_complete:1; /* PR Data push complete */
1185                         u8  pr_kind:1;          /* PR Data push complete */
1186                         u32 rsvd:17;            /* Reserved */
1187                         u32 config_data;        /* Config data TBD */
1188                 };
1189         };
1190 };
1191
1192 /* FME Partial Reconfiguration Status */
1193 struct feature_fme_pr_status {
1194         union {
1195                 u64 csr;
1196                 struct {
1197                         u16 pr_credit:9;        /* PR Credits */
1198                         u8  rsvd2:7;            /* Reserved */
1199                         u8  pr_status:1;        /* PR status */
1200                         u8  rsvd:3;             /* Reserved */
1201                         /* Altra PR Controller Block status */
1202                         u8  pr_controller_status:3;
1203                         u8  rsvd1:1;            /* Reserved */
1204                         u8  pr_host_status:4;   /* PR Host status */
1205                         u8  rsvd3:4;            /* Reserved */
1206                         /* Security Block Status fields (TBD) */
1207                         u32 security_bstatus;
1208                 };
1209         };
1210 };
1211
1212 /* FME Partial Reconfiguration Data */
1213 struct feature_fme_pr_data {
1214         union {
1215                 u64 csr;        /* PR data from the raw-binary file */
1216                 struct {
1217                         /* PR data from the raw-binary file */
1218                         u32 pr_data_raw;
1219                         u32 rsvd;
1220                 };
1221         };
1222 };
1223
1224 /* FME PR Public Key */
1225 struct feature_fme_pr_key {
1226         u64 key;                /* FME PR Public Hash */
1227 };
1228
1229 /* FME PR FEATURE */
1230 struct feature_fme_pr {
1231         struct feature_header header;
1232         /*Partial Reconfiguration control */
1233         struct feature_fme_pr_ctl       ccip_fme_pr_control;
1234
1235         /* Partial Reconfiguration Status */
1236         struct feature_fme_pr_status    ccip_fme_pr_status;
1237
1238         /* Partial Reconfiguration data */
1239         struct feature_fme_pr_data      ccip_fme_pr_data;
1240
1241         /* Partial Reconfiguration data */
1242         u64                             ccip_fme_pr_err;
1243
1244         u64 rsvd1[3];
1245
1246         /* Partial Reconfiguration data registers */
1247         u64 fme_pr_data1;
1248         u64 fme_pr_data2;
1249         u64 fme_pr_data3;
1250         u64 fme_pr_data4;
1251         u64 fme_pr_data5;
1252         u64 fme_pr_data6;
1253         u64 fme_pr_data7;
1254         u64 fme_pr_data8;
1255
1256         u64 rsvd2[5];
1257
1258         /* PR Interface ID */
1259         u64 fme_pr_intfc_id_l;
1260         u64 fme_pr_intfc_id_h;
1261
1262         /* MSIX filed to be Added */
1263 };
1264
1265 /* FME HSSI Control */
1266 struct feature_fme_hssi_eth_ctrl {
1267         union {
1268                 u64 csr;
1269                 struct {
1270                         u32 data:32;            /* HSSI data */
1271                         u16 address:16;         /* HSSI address */
1272                         /*
1273                          * HSSI comamnd
1274                          * 0x0 - No request
1275                          * 0x08 - SW register RD request
1276                          * 0x10 - SW register WR request
1277                          * 0x40 - Auxiliar bus RD request
1278                          * 0x80 - Auxiliar bus WR request
1279                          */
1280                         u16 cmd:16;
1281                 };
1282         };
1283 };
1284
1285 /* FME HSSI Status */
1286 struct feature_fme_hssi_eth_stat {
1287         union {
1288                 u64 csr;
1289                 struct {
1290                         u32 data:32;            /* HSSI data */
1291                         u8  acknowledge:1;      /* HSSI acknowledge */
1292                         u8  spare:1;            /* HSSI spare */
1293                         u32 rsvd:30;            /* Reserved */
1294                 };
1295         };
1296 };
1297
1298 /* FME HSSI FEATURE */
1299 struct feature_fme_hssi {
1300         struct feature_header header;
1301         struct feature_fme_hssi_eth_ctrl        hssi_control;
1302         struct feature_fme_hssi_eth_stat        hssi_status;
1303 };
1304
1305 #define PORT_ERR_MASK           0xfff0703ff001f
1306 struct feature_port_err_key {
1307         union {
1308                 u64 csr;
1309                 struct {
1310                         /* Tx Channel0: Overflow */
1311                         u8 tx_ch0_overflow:1;
1312                         /* Tx Channel0: Invalid request encoding */
1313                         u8 tx_ch0_invaldreq :1;
1314                         /* Tx Channel0: Request with cl_len=3 not supported */
1315                         u8 tx_ch0_cl_len3:1;
1316                         /* Tx Channel0: Request with cl_len=2 not aligned 2CL */
1317                         u8 tx_ch0_cl_len2:1;
1318                         /* Tx Channel0: Request with cl_len=4 not aligned 4CL */
1319                         u8 tx_ch0_cl_len4:1;
1320
1321                         u16 rsvd1:4;                    /* Reserved */
1322
1323                         /* AFU MMIO RD received while PORT is in reset */
1324                         u8 mmio_rd_whilerst:1;
1325                         /* AFU MMIO WR received while PORT is in reset */
1326                         u8 mmio_wr_whilerst:1;
1327
1328                         u16 rsvd2:5;                    /* Reserved */
1329
1330                         /* Tx Channel1: Overflow */
1331                         u8 tx_ch1_overflow:1;
1332                         /* Tx Channel1: Invalid request encoding */
1333                         u8 tx_ch1_invaldreq:1;
1334                         /* Tx Channel1: Request with cl_len=3 not supported */
1335                         u8 tx_ch1_cl_len3:1;
1336                         /* Tx Channel1: Request with cl_len=2 not aligned 2CL */
1337                         u8 tx_ch1_cl_len2:1;
1338                         /* Tx Channel1: Request with cl_len=4 not aligned 4CL */
1339                         u8 tx_ch1_cl_len4:1;
1340
1341                         /* Tx Channel1: Insufficient data payload */
1342                         u8 tx_ch1_insuff_data:1;
1343                         /* Tx Channel1: Data payload overrun */
1344                         u8 tx_ch1_data_overrun:1;
1345                         /* Tx Channel1 : Incorrect address */
1346                         u8 tx_ch1_incorr_addr:1;
1347                         /* Tx Channel1 : NON-Zero SOP Detected */
1348                         u8 tx_ch1_nzsop:1;
1349                         /* Tx Channel1 : Illegal VC_SEL, atomic request VLO */
1350                         u8 tx_ch1_illegal_vcsel:1;
1351
1352                         u8 rsvd3:6;                     /* Reserved */
1353
1354                         /* MMIO Read Timeout in AFU */
1355                         u8 mmioread_timeout:1;
1356
1357                         /* Tx Channel2: FIFO Overflow */
1358                         u8 tx_ch2_fifo_overflow:1;
1359
1360                         /* MMIO read is not matching pending request */
1361                         u8 unexp_mmio_resp:1;
1362
1363                         u8 rsvd4:5;                     /* Reserved */
1364
1365                         /* Number of pending Requests: counter overflow */
1366                         u8 tx_req_counter_overflow:1;
1367                         /* Req with Address violating SMM Range */
1368                         u8 llpr_smrr_err:1;
1369                         /* Req with Address violating second SMM Range */
1370                         u8 llpr_smrr2_err:1;
1371                         /* Req with Address violating ME Stolen message */
1372                         u8 llpr_mesg_err:1;
1373                         /* Req with Address violating Generic Protected Range */
1374                         u8 genprot_range_err:1;
1375                         /* Req with Address violating Legacy Range low */
1376                         u8 legrange_low_err:1;
1377                         /* Req with Address violating Legacy Range High */
1378                         u8 legrange_high_err:1;
1379                         /* Req with Address violating VGA memory range */
1380                         u8 vgmem_range_err:1;
1381                         u8 page_fault_err:1;            /* Page fault */
1382                         u8 pmr_err:1;                   /* PMR Error */
1383                         u8 ap6_event:1;                 /* AP6 event */
1384                         /* VF FLR detected on Port with PF access control */
1385                         u8 vfflr_access_err:1;
1386                         u16 rsvd5:12;                   /* Reserved */
1387                 };
1388         };
1389 };
1390
1391 /* Port first error register, not contain all error bits in error register. */
1392 struct feature_port_first_err_key {
1393         union {
1394                 u64 csr;
1395                 struct {
1396                         u8 tx_ch0_overflow:1;
1397                         u8 tx_ch0_invaldreq :1;
1398                         u8 tx_ch0_cl_len3:1;
1399                         u8 tx_ch0_cl_len2:1;
1400                         u8 tx_ch0_cl_len4:1;
1401                         u8 rsvd1:4;                     /* Reserved */
1402                         u8 mmio_rd_whilerst:1;
1403                         u8 mmio_wr_whilerst:1;
1404                         u8 rsvd2:5;                     /* Reserved */
1405                         u8 tx_ch1_overflow:1;
1406                         u8 tx_ch1_invaldreq:1;
1407                         u8 tx_ch1_cl_len3:1;
1408                         u8 tx_ch1_cl_len2:1;
1409                         u8 tx_ch1_cl_len4:1;
1410                         u8 tx_ch1_insuff_data:1;
1411                         u8 tx_ch1_data_overrun:1;
1412                         u8 tx_ch1_incorr_addr:1;
1413                         u8 tx_ch1_nzsop:1;
1414                         u8 tx_ch1_illegal_vcsel:1;
1415                         u8 rsvd3:6;                     /* Reserved */
1416                         u8 mmioread_timeout:1;
1417                         u8 tx_ch2_fifo_overflow:1;
1418                         u8 rsvd4:6;                     /* Reserved */
1419                         u8 tx_req_counter_overflow:1;
1420                         u32 rsvd5:23;                   /* Reserved */
1421                 };
1422         };
1423 };
1424
1425 /* Port malformed Req0 */
1426 struct feature_port_malformed_req0 {
1427         u64 header_lsb;
1428 };
1429
1430 /* Port malformed Req1 */
1431 struct feature_port_malformed_req1 {
1432         u64 header_msb;
1433 };
1434
1435 /* Port debug register */
1436 struct feature_port_debug {
1437         u64 port_debug;
1438 };
1439
1440 /* Port error capabilities */
1441 struct feature_port_err_capability {
1442         union {
1443                 u64 csr;
1444                 struct {
1445                         u8  support_intr:1;
1446                         /* MSI-X vector table entry number */
1447                         u16 intr_vector_num:12;
1448                         u64 rsvd:51;            /* Reserved */
1449                 };
1450         };
1451 };
1452
1453 /* PORT FEATURE ERROR */
1454 struct feature_port_error {
1455         struct feature_header header;
1456         struct feature_port_err_key error_mask;
1457         struct feature_port_err_key port_error;
1458         struct feature_port_first_err_key port_first_error;
1459         struct feature_port_malformed_req0 malreq0;
1460         struct feature_port_malformed_req1 malreq1;
1461         struct feature_port_debug port_debug;
1462         struct feature_port_err_capability error_capability;
1463 };
1464
1465 /* Port UMSG Capability */
1466 struct feature_port_umsg_cap {
1467         union {
1468                 u64 csr;
1469                 struct {
1470                         /* Number of umsg allocated to this port */
1471                         u8 umsg_allocated;
1472                         /* Enable / Disable UMsg engine for this port */
1473                         u8 umsg_enable:1;
1474                         /* Usmg initialization status */
1475                         u8 umsg_init_complete:1;
1476                         /* IOMMU can not translate the umsg base address */
1477                         u8 umsg_trans_error:1;
1478                         u64 rsvd:53;            /* Reserved */
1479                 };
1480         };
1481 };
1482
1483 /* Port UMSG base address */
1484 struct feature_port_umsg_baseaddr {
1485         union {
1486                 u64 csr;
1487                 struct {
1488                         u64 base_addr:48;       /* 48 bit physical address */
1489                         u16 rsvd;               /* Reserved */
1490                 };
1491         };
1492 };
1493
1494 struct feature_port_umsg_mode {
1495         union {
1496                 u64 csr;
1497                 struct {
1498                         u32 umsg_hint_enable;   /* UMSG hint enable/disable */
1499                         u32 rsvd;               /* Reserved */
1500                 };
1501         };
1502 };
1503
1504 /* PORT FEATURE UMSG */
1505 struct feature_port_umsg {
1506         struct feature_header header;
1507         struct feature_port_umsg_cap capability;
1508         struct feature_port_umsg_baseaddr baseaddr;
1509         struct feature_port_umsg_mode mode;
1510 };
1511
1512 #define UMSG_EN_POLL_INVL 10 /* us */
1513 #define UMSG_EN_POLL_TIMEOUT 1000 /* us */
1514
1515 /* Port UINT Capability */
1516 struct feature_port_uint_cap {
1517         union {
1518                 u64 csr;
1519                 struct {
1520                         u16 intr_num:12;        /* Supported interrupts num */
1521                         /* First MSI-X vector table entry number */
1522                         u16 first_vec_num:12;
1523                         u64 rsvd:40;
1524                 };
1525         };
1526 };
1527
1528 /* PORT FEATURE UINT */
1529 struct feature_port_uint {
1530         struct feature_header header;
1531         struct feature_port_uint_cap capability;
1532 };
1533
1534 /* STP region supports mmap operation, so use page aligned size. */
1535 #define PORT_FEATURE_STP_REGION_SIZE \
1536         IFPGA_PAGE_ALIGN(sizeof(struct feature_port_stp))
1537
1538 /* Port STP status register (for debug only)*/
1539 struct feature_port_stp_status {
1540         union {
1541                 u64 csr;
1542                 struct {
1543                         /* SLD Hub end-point read/write timeout */
1544                         u8 sld_ep_timeout:1;
1545                         /* Remote STP in reset/disable */
1546                         u8 rstp_disabled:1;
1547                         u8 unsupported_read:1;
1548                         /* MMIO timeout detected and faked with a response */
1549                         u8 mmio_timeout:1;
1550                         u8 txfifo_count:4;
1551                         u8 rxfifo_count:4;
1552                         u8 txfifo_overflow:1;
1553                         u8 txfifo_underflow:1;
1554                         u8 rxfifo_overflow:1;
1555                         u8 rxfifo_underflow:1;
1556                         /* Number of MMIO write requests */
1557                         u16 write_requests;
1558                         /* Number of MMIO read requests */
1559                         u16 read_requests;
1560                         /* Number of MMIO read responses */
1561                         u16 read_responses;
1562                 };
1563         };
1564 };
1565
1566 /*
1567  * PORT FEATURE STP
1568  * Most registers in STP region are not touched by driver, but mmapped to user
1569  * space. So they are not defined in below data structure, as its actual size
1570  * is 0x18c per spec.
1571  */
1572 struct feature_port_stp {
1573         struct feature_header header;
1574         struct feature_port_stp_status stp_status;
1575 };
1576
1577 /**
1578  * enum fpga_pr_states - fpga PR states
1579  * @FPGA_PR_STATE_UNKNOWN: can't determine state
1580  * @FPGA_PR_STATE_WRITE_INIT: preparing FPGA for programming
1581  * @FPGA_PR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage
1582  * @FPGA_PR_STATE_WRITE: writing image to FPGA
1583  * @FPGA_PR_STATE_WRITE_ERR: Error while writing FPGA
1584  * @FPGA_PR_STATE_WRITE_COMPLETE: Doing post programming steps
1585  * @FPGA_PR_STATE_WRITE_COMPLETE_ERR: Error during WRITE_COMPLETE
1586  * @FPGA_PR_STATE_OPERATING: FPGA PR done
1587  */
1588 enum fpga_pr_states {
1589         /* canot determine state states */
1590         FPGA_PR_STATE_UNKNOWN,
1591
1592         /* write sequence: init, write, complete */
1593         FPGA_PR_STATE_WRITE_INIT,
1594         FPGA_PR_STATE_WRITE_INIT_ERR,
1595         FPGA_PR_STATE_WRITE,
1596         FPGA_PR_STATE_WRITE_ERR,
1597         FPGA_PR_STATE_WRITE_COMPLETE,
1598         FPGA_PR_STATE_WRITE_COMPLETE_ERR,
1599
1600         /* FPGA PR done */
1601         FPGA_PR_STATE_DONE,
1602 };
1603
1604 /*
1605  * FPGA Manager flags
1606  * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported
1607  */
1608 #define FPGA_MGR_PARTIAL_RECONFIG       BIT(0)
1609
1610 /**
1611  * struct fpga_pr_info - specific information to a FPGA PR
1612  * @flags: boolean flags as defined above
1613  * @pr_err: PR error code
1614  * @state: fpga manager state
1615  * @port_id: port id
1616  */
1617 struct fpga_pr_info {
1618         u32 flags;
1619         u64 pr_err;
1620         enum fpga_pr_states state;
1621         int port_id;
1622 };
1623
1624 #define DEFINE_FPGA_PR_ERR_MSG(_name_)                  \
1625 static const char * const _name_[] = {                  \
1626         "PR operation error detected",                  \
1627         "PR CRC error detected",                        \
1628         "PR incompatiable bitstream error detected",    \
1629         "PR IP protocol error detected",                \
1630         "PR FIFO overflow error detected",              \
1631         "PR timeout error detected",                    \
1632         "PR secure load error detected",                \
1633 }
1634
1635 #define RST_POLL_INVL 10 /* us */
1636 #define RST_POLL_TIMEOUT 1000 /* us */
1637
1638 #define PR_WAIT_TIMEOUT   15000000
1639
1640 #define PR_HOST_STATUS_IDLE     0
1641 #define PR_MAX_ERR_NUM  7
1642
1643 DEFINE_FPGA_PR_ERR_MSG(pr_err_msg);
1644
1645 /*
1646  * green bitstream header must be byte-packed to match the
1647  * real file format.
1648  */
1649 struct bts_header {
1650         u64 guid_h;
1651         u64 guid_l;
1652         u32 metadata_len;
1653 };
1654
1655 #define GBS_GUID_H              0x414750466e6f6558
1656 #define GBS_GUID_L              0x31303076534247b7
1657 #define is_valid_bts(bts_hdr)                           \
1658         (((bts_hdr)->guid_h == GBS_GUID_H) &&           \
1659         ((bts_hdr)->guid_l == GBS_GUID_L))
1660
1661 #pragma pack(pop)
1662 #endif /* _BASE_IFPGA_DEFINES_H_ */