1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
5 #include "opae_hw_api.h"
9 #include "ifpga_enumerate.h"
10 #include "ifpga_feature_dev.h"
12 struct build_feature_devs_info {
13 struct opae_adapter_data_pci *pci_data;
15 struct ifpga_afu_info *acc_info;
18 enum fpga_id_type current_type;
36 unsigned int vec_start;
39 struct feature_ops *ops;
42 /* indexed by fme feature IDs which are defined in 'enum fme_feature_id'. */
43 static struct feature_info fme_features[] = {
45 .name = FME_FEATURE_HEADER,
46 .resource_size = sizeof(struct feature_fme_header),
47 .feature_index = FME_FEATURE_ID_HEADER,
48 .revision_id = FME_HEADER_REVISION,
52 .name = FME_FEATURE_THERMAL_MGMT,
53 .resource_size = sizeof(struct feature_fme_thermal),
54 .feature_index = FME_FEATURE_ID_THERMAL_MGMT,
55 .revision_id = FME_THERMAL_MGMT_REVISION,
56 .ops = &fme_thermal_mgmt_ops,
59 .name = FME_FEATURE_POWER_MGMT,
60 .resource_size = sizeof(struct feature_fme_power),
61 .feature_index = FME_FEATURE_ID_POWER_MGMT,
62 .revision_id = FME_POWER_MGMT_REVISION,
63 .ops = &fme_power_mgmt_ops,
66 .name = FME_FEATURE_GLOBAL_IPERF,
67 .resource_size = sizeof(struct feature_fme_iperf),
68 .feature_index = FME_FEATURE_ID_GLOBAL_IPERF,
69 .revision_id = FME_GLOBAL_IPERF_REVISION,
70 .ops = &fme_global_iperf_ops,
73 .name = FME_FEATURE_GLOBAL_ERR,
74 .resource_size = sizeof(struct feature_fme_err),
75 .feature_index = FME_FEATURE_ID_GLOBAL_ERR,
76 .revision_id = FME_GLOBAL_ERR_REVISION,
77 .ops = &fme_global_err_ops,
80 .name = FME_FEATURE_PR_MGMT,
81 .resource_size = sizeof(struct feature_fme_pr),
82 .feature_index = FME_FEATURE_ID_PR_MGMT,
83 .revision_id = FME_PR_MGMT_REVISION,
84 .ops = &fme_pr_mgmt_ops,
87 .name = FME_FEATURE_HSSI_ETH,
88 .resource_size = sizeof(struct feature_fme_hssi),
89 .feature_index = FME_FEATURE_ID_HSSI_ETH,
90 .revision_id = FME_HSSI_ETH_REVISION
93 .name = FME_FEATURE_GLOBAL_DPERF,
94 .resource_size = sizeof(struct feature_fme_dperf),
95 .feature_index = FME_FEATURE_ID_GLOBAL_DPERF,
96 .revision_id = FME_GLOBAL_DPERF_REVISION,
97 .ops = &fme_global_dperf_ops,
101 static struct feature_info port_features[] = {
103 .name = PORT_FEATURE_HEADER,
104 .resource_size = sizeof(struct feature_port_header),
105 .feature_index = PORT_FEATURE_ID_HEADER,
106 .revision_id = PORT_HEADER_REVISION,
107 .ops = &ifpga_rawdev_port_hdr_ops,
110 .name = PORT_FEATURE_ERR,
111 .resource_size = sizeof(struct feature_port_error),
112 .feature_index = PORT_FEATURE_ID_ERROR,
113 .revision_id = PORT_ERR_REVISION,
114 .ops = &ifpga_rawdev_port_error_ops,
117 .name = PORT_FEATURE_UMSG,
118 .resource_size = sizeof(struct feature_port_umsg),
119 .feature_index = PORT_FEATURE_ID_UMSG,
120 .revision_id = PORT_UMSG_REVISION,
123 .name = PORT_FEATURE_UINT,
124 .resource_size = sizeof(struct feature_port_uint),
125 .feature_index = PORT_FEATURE_ID_UINT,
126 .revision_id = PORT_UINT_REVISION,
127 .ops = &ifpga_rawdev_port_uint_ops,
130 .name = PORT_FEATURE_STP,
131 .resource_size = PORT_FEATURE_STP_REGION_SIZE,
132 .feature_index = PORT_FEATURE_ID_STP,
133 .revision_id = PORT_STP_REVISION,
134 .ops = &ifpga_rawdev_port_stp_ops,
137 .name = PORT_FEATURE_UAFU,
138 /* UAFU feature size should be read from PORT_CAP.MMIOSIZE.
139 * Will set uafu feature size while parse port device.
142 .feature_index = PORT_FEATURE_ID_UAFU,
143 .revision_id = PORT_UAFU_REVISION
147 static u64 feature_id(void __iomem *start)
149 struct feature_header header;
151 header.csr = readq(start);
153 switch (header.type) {
154 case FEATURE_TYPE_FIU:
155 return FEATURE_ID_HEADER;
156 case FEATURE_TYPE_PRIVATE:
158 case FEATURE_TYPE_AFU:
159 return FEATURE_ID_AFU;
167 build_info_add_sub_feature(struct build_feature_devs_info *binfo,
168 struct feature_info *finfo, void __iomem *start)
170 struct ifpga_hw *hw = binfo->hw;
171 struct feature *feature = NULL;
172 int feature_idx = finfo->feature_index;
173 unsigned int vec_start = finfo->vec_start;
174 unsigned int vec_cnt = finfo->vec_cnt;
175 struct feature_irq_ctx *ctx = NULL;
176 int port_id, ret = 0;
179 if (binfo->current_type == FME_ID) {
180 feature = &hw->fme.sub_feature[feature_idx];
181 feature->parent = &hw->fme;
182 } else if (binfo->current_type == PORT_ID) {
183 port_id = binfo->current_port_id;
184 feature = &hw->port[port_id].sub_feature[feature_idx];
185 feature->parent = &hw->port[port_id];
190 feature->state = IFPGA_FEATURE_ATTACHED;
191 feature->addr = start;
192 feature->id = feature_id(start);
193 feature->size = finfo->resource_size;
194 feature->name = finfo->name;
195 feature->revision = finfo->revision_id;
196 feature->ops = finfo->ops;
197 feature->phys_addr = binfo->phys_addr +
198 ((u8 *)start - (u8 *)binfo->ioaddr);
201 if (vec_start + vec_cnt <= vec_start)
204 ctx = zmalloc(sizeof(*ctx) * vec_cnt);
208 for (i = 0; i < vec_cnt; i++) {
210 ctx[i].idx = vec_start + i;
215 feature->ctx_num = vec_cnt;
216 feature->vfio_dev_fd = binfo->pci_data->vfio_dev_fd;
222 create_feature_instance(struct build_feature_devs_info *binfo,
223 void __iomem *start, struct feature_info *finfo)
225 struct feature_header *hdr = start;
227 if (finfo->revision_id != SKIP_REVISION_CHECK &&
228 hdr->revision > finfo->revision_id) {
229 dev_err(binfo, "feature %s revision :default:%x, now at:%x, mis-match.\n",
230 finfo->name, finfo->revision_id, hdr->revision);
233 return build_info_add_sub_feature(binfo, finfo, start);
237 * UAFU GUID is dynamic as it can be changed after FME downloads different
238 * Green Bitstream to the port, so we treat the unknown GUIDs which are
239 * attached on port's feature list as UAFU.
241 static bool feature_is_UAFU(struct build_feature_devs_info *binfo)
243 if (binfo->current_type != PORT_ID)
249 static int parse_feature_port_uafu(struct build_feature_devs_info *binfo,
250 struct feature_header *hdr)
252 enum port_feature_id id = PORT_FEATURE_ID_UAFU;
253 struct ifpga_afu_info *info;
254 void *start = (void *)hdr;
257 if (port_features[id].resource_size) {
258 ret = create_feature_instance(binfo, hdr, &port_features[id]);
260 dev_err(binfo, "the uafu feature header is mis-configured.\n");
267 /* FIXME: need to figure out a better name */
268 info = malloc(sizeof(*info));
272 info->region[0].addr = start;
273 info->region[0].phys_addr = binfo->phys_addr +
274 (uint8_t *)start - (uint8_t *)binfo->ioaddr;
275 info->region[0].len = port_features[id].resource_size;
276 port_features[id].resource_size = 0;
277 info->num_regions = 1;
279 binfo->acc_info = info;
284 static int parse_feature_afus(struct build_feature_devs_info *binfo,
285 struct feature_header *hdr)
288 struct feature_afu_header *afu_hdr, header;
290 u8 __iomem *end = binfo->ioend;
292 start = (u8 __iomem *)hdr;
293 for (; start < end; start += header.next_afu) {
294 if ((unsigned int)(end - start) <
295 (unsigned int)(sizeof(*afu_hdr) + sizeof(*hdr)))
298 hdr = (struct feature_header *)start;
299 afu_hdr = (struct feature_afu_header *)(hdr + 1);
300 header.csr = readq(&afu_hdr->csr);
302 if (feature_is_UAFU(binfo)) {
303 ret = parse_feature_port_uafu(binfo, hdr);
308 if (!header.next_afu)
315 /* create and register proper private data */
316 static int build_info_commit_dev(struct build_feature_devs_info *binfo)
318 struct ifpga_afu_info *info = binfo->acc_info;
319 struct ifpga_hw *hw = binfo->hw;
320 struct opae_manager *mgr;
321 struct opae_bridge *br;
322 struct opae_accelerator *acc;
327 if (binfo->current_type == PORT_ID) {
328 /* return error if no valid acc info data structure */
332 br = opae_bridge_alloc(hw->adapter->name, &ifpga_br_ops,
337 br->id = binfo->current_port_id;
339 /* update irq info */
340 info->num_irqs = port_features[PORT_FEATURE_ID_UINT].vec_cnt;
342 acc = opae_accelerator_alloc(hw->adapter->name,
343 &ifpga_acc_ops, info);
345 opae_bridge_free(br);
352 opae_adapter_add_acc(hw->adapter, acc);
354 } else if (binfo->current_type == FME_ID) {
355 mgr = opae_manager_alloc(hw->adapter->name, &ifpga_mgr_ops,
360 mgr->adapter = hw->adapter;
361 hw->adapter->mgr = mgr;
370 build_info_create_dev(struct build_feature_devs_info *binfo,
371 enum fpga_id_type type, unsigned int index)
375 ret = build_info_commit_dev(binfo);
379 binfo->current_type = type;
381 if (type == FME_ID) {
382 binfo->fiu = &binfo->hw->fme;
383 } else if (type == PORT_ID) {
384 binfo->fiu = &binfo->hw->port[index];
385 binfo->current_port_id = index;
391 static int parse_feature_fme(struct build_feature_devs_info *binfo,
392 struct feature_header *start)
394 struct ifpga_hw *hw = binfo->hw;
395 struct ifpga_fme_hw *fme = &hw->fme;
398 ret = build_info_create_dev(binfo, FME_ID, 0);
402 /* Update FME states */
403 fme->state = IFPGA_FME_IMPLEMENTED;
405 spinlock_init(&fme->lock);
407 return create_feature_instance(binfo, start,
408 &fme_features[FME_FEATURE_ID_HEADER]);
411 static int parse_feature_port(struct build_feature_devs_info *binfo,
414 struct feature_port_header *port_hdr;
415 struct feature_port_capability capability;
416 struct ifpga_hw *hw = binfo->hw;
417 struct ifpga_port_hw *port;
418 unsigned int port_id;
421 /* Get current port's id */
422 port_hdr = (struct feature_port_header *)start;
423 capability.csr = readq(&port_hdr->capability);
424 port_id = capability.port_number;
426 ret = build_info_create_dev(binfo, PORT_ID, port_id);
430 /*found a Port device*/
431 port = &hw->port[port_id];
432 port->port_id = binfo->current_port_id;
434 port->state = IFPGA_PORT_ATTACHED;
435 spinlock_init(&port->lock);
437 return create_feature_instance(binfo, start,
438 &port_features[PORT_FEATURE_ID_HEADER]);
441 static void enable_port_uafu(struct build_feature_devs_info *binfo,
444 enum port_feature_id id = PORT_FEATURE_ID_UAFU;
445 struct feature_port_header *port_hdr;
446 struct feature_port_capability capability;
447 struct ifpga_port_hw *port = &binfo->hw->port[binfo->current_port_id];
449 port_hdr = (struct feature_port_header *)start;
450 capability.csr = readq(&port_hdr->capability);
451 port_features[id].resource_size = (capability.mmio_size << 10);
454 * From spec, to Enable UAFU, we should reset related port,
455 * or the whole mmio space in this UAFU will be invalid
457 if (port_features[id].resource_size)
458 fpga_port_reset(port);
461 static int parse_feature_fiu(struct build_feature_devs_info *binfo,
462 struct feature_header *hdr)
464 struct feature_header header;
465 struct feature_fiu_header *fiu_hdr, fiu_header;
466 u8 __iomem *start = (u8 __iomem *)hdr;
469 header.csr = readq(hdr);
472 case FEATURE_FIU_ID_FME:
473 ret = parse_feature_fme(binfo, hdr);
474 binfo->pfme_hdr = hdr;
478 case FEATURE_FIU_ID_PORT:
479 ret = parse_feature_port(binfo, hdr);
480 enable_port_uafu(binfo, hdr);
484 /* Check Port FIU's next_afu pointer to User AFU DFH */
485 fiu_hdr = (struct feature_fiu_header *)(hdr + 1);
486 fiu_header.csr = readq(&fiu_hdr->csr);
488 if (fiu_header.next_afu) {
489 start += fiu_header.next_afu;
490 ret = parse_feature_afus(binfo,
491 (struct feature_header *)start);
495 dev_info(binfo, "No AFUs detected on Port\n");
500 dev_info(binfo, "FIU TYPE %d is not supported yet.\n",
507 static void parse_feature_irqs(struct build_feature_devs_info *binfo,
508 void __iomem *start, struct feature_info *finfo)
510 finfo->vec_start = 0;
515 if (!strcmp(finfo->name, PORT_FEATURE_UINT)) {
516 struct feature_port_uint *port_uint = start;
517 struct feature_port_uint_cap uint_cap;
519 uint_cap.csr = readq(&port_uint->capability);
520 if (uint_cap.intr_num) {
521 finfo->vec_start = uint_cap.first_vec_num;
522 finfo->vec_cnt = uint_cap.intr_num;
524 dev_debug(binfo, "UAFU doesn't support interrupt\n");
526 } else if (!strcmp(finfo->name, PORT_FEATURE_ERR)) {
527 struct feature_port_error *port_err = start;
528 struct feature_port_err_capability port_err_cap;
530 port_err_cap.csr = readq(&port_err->error_capability);
531 if (port_err_cap.support_intr) {
532 finfo->vec_start = port_err_cap.intr_vector_num;
535 dev_debug(&binfo, "Port error doesn't support interrupt\n");
538 } else if (!strcmp(finfo->name, FME_FEATURE_GLOBAL_ERR)) {
539 struct feature_fme_err *fme_err = start;
540 struct feature_fme_error_capability fme_err_cap;
542 fme_err_cap.csr = readq(&fme_err->fme_err_capability);
543 if (fme_err_cap.support_intr) {
544 finfo->vec_start = fme_err_cap.intr_vector_num;
547 dev_debug(&binfo, "FME error doesn't support interrupt\n");
552 static int parse_feature_fme_private(struct build_feature_devs_info *binfo,
553 struct feature_header *hdr)
555 struct feature_header header;
557 header.csr = readq(hdr);
559 if (header.id >= ARRAY_SIZE(fme_features)) {
560 dev_err(binfo, "FME feature id %x is not supported yet.\n",
565 parse_feature_irqs(binfo, hdr, &fme_features[header.id]);
567 return create_feature_instance(binfo, hdr, &fme_features[header.id]);
570 static int parse_feature_port_private(struct build_feature_devs_info *binfo,
571 struct feature_header *hdr)
573 struct feature_header header;
574 enum port_feature_id id;
576 header.csr = readq(hdr);
578 * the region of port feature id is [0x10, 0x13], + 1 to reserve 0
579 * which is dedicated for port-hdr.
581 id = (header.id & 0x000f) + 1;
583 if (id >= ARRAY_SIZE(port_features)) {
584 dev_err(binfo, "Port feature id %x is not supported yet.\n",
589 parse_feature_irqs(binfo, hdr, &port_features[id]);
591 return create_feature_instance(binfo, hdr, &port_features[id]);
594 static int parse_feature_private(struct build_feature_devs_info *binfo,
595 struct feature_header *hdr)
597 struct feature_header header;
599 header.csr = readq(hdr);
601 switch (binfo->current_type) {
603 return parse_feature_fme_private(binfo, hdr);
605 return parse_feature_port_private(binfo, hdr);
607 dev_err(binfo, "private feature %x belonging to AFU %d (unknown_type) is not supported yet.\n",
608 header.id, binfo->current_type);
613 static int parse_feature(struct build_feature_devs_info *binfo,
614 struct feature_header *hdr)
616 struct feature_header header;
619 header.csr = readq(hdr);
621 switch (header.type) {
622 case FEATURE_TYPE_AFU:
623 ret = parse_feature_afus(binfo, hdr);
625 case FEATURE_TYPE_PRIVATE:
626 ret = parse_feature_private(binfo, hdr);
628 case FEATURE_TYPE_FIU:
629 ret = parse_feature_fiu(binfo, hdr);
632 dev_err(binfo, "Feature Type %x is not supported.\n",
640 parse_feature_list(struct build_feature_devs_info *binfo, u8 __iomem *start)
642 struct feature_header *hdr, header;
643 u8 __iomem *end = (u8 __iomem *)binfo->ioend;
646 for (; start < end; start += header.next_header_offset) {
647 if ((unsigned int)(end - start) < (unsigned int)sizeof(*hdr)) {
648 dev_err(binfo, "The region is too small to contain a feature.\n");
653 hdr = (struct feature_header *)start;
654 ret = parse_feature(binfo, hdr);
658 header.csr = readq(hdr);
659 if (!header.next_header_offset)
663 return build_info_commit_dev(binfo);
666 /* switch the memory mapping to BAR# @bar */
667 static int parse_switch_to(struct build_feature_devs_info *binfo, int bar)
669 struct opae_adapter_data_pci *pci_data = binfo->pci_data;
671 if (!pci_data->region[bar].addr)
674 binfo->ioaddr = pci_data->region[bar].addr;
675 binfo->ioend = (u8 __iomem *)binfo->ioaddr + pci_data->region[bar].len;
676 binfo->phys_addr = pci_data->region[bar].phys_addr;
677 binfo->current_bar = bar;
682 static int parse_ports_from_fme(struct build_feature_devs_info *binfo)
684 struct feature_fme_header *fme_hdr;
685 struct feature_fme_port port;
688 if (!binfo->pfme_hdr) {
689 dev_info(binfo, "VF is detected.\n");
693 fme_hdr = binfo->pfme_hdr;
696 port.csr = readq(&fme_hdr->port[i]);
697 if (!port.port_implemented)
700 /* skip port which only could be accessed via VF */
701 if (port.afu_access_control == FME_AFU_ACCESS_VF)
704 ret = parse_switch_to(binfo, port.port_bar);
708 ret = parse_feature_list(binfo,
709 (u8 __iomem *)binfo->ioaddr +
713 } while (++i < MAX_FPGA_PORT_NUM);
718 static struct build_feature_devs_info *
719 build_info_alloc_and_init(struct ifpga_hw *hw)
721 struct build_feature_devs_info *binfo;
723 binfo = zmalloc(sizeof(*binfo));
728 binfo->pci_data = hw->pci_data;
730 /* fpga feature list starts from BAR 0 */
731 if (parse_switch_to(binfo, 0)) {
739 static void build_info_free(struct build_feature_devs_info *binfo)
744 static void ifpga_print_device_feature_list(struct ifpga_hw *hw)
746 struct ifpga_fme_hw *fme = &hw->fme;
747 struct ifpga_port_hw *port;
748 struct feature *feature;
751 dev_info(hw, "found fme_device, is in PF: %s\n",
752 is_ifpga_hw_pf(hw) ? "yes" : "no");
754 for (i = 0; i < FME_FEATURE_ID_MAX; i++) {
755 feature = &fme->sub_feature[i];
756 if (feature->state != IFPGA_FEATURE_ATTACHED)
759 dev_info(hw, "%12s: 0x%p - 0x%p - paddr: 0x%lx\n",
760 feature->name, feature->addr,
761 feature->addr + feature->size - 1,
762 (unsigned long)feature->phys_addr);
765 for (i = 0; i < MAX_FPGA_PORT_NUM; i++) {
768 if (port->state != IFPGA_PORT_ATTACHED)
771 dev_info(hw, "port device: %d\n", port->port_id);
773 for (j = 0; j < PORT_FEATURE_ID_MAX; j++) {
774 feature = &port->sub_feature[j];
775 if (feature->state != IFPGA_FEATURE_ATTACHED)
778 dev_info(hw, "%12s: 0x%p - 0x%p - paddr:0x%lx\n",
783 (unsigned long)feature->phys_addr);
788 int ifpga_bus_enumerate(struct ifpga_hw *hw)
790 struct build_feature_devs_info *binfo;
793 binfo = build_info_alloc_and_init(hw);
797 ret = parse_feature_list(binfo, binfo->ioaddr);
801 ret = parse_ports_from_fme(binfo);
805 ifpga_print_device_feature_list(hw);
808 build_info_free(binfo);
812 int ifpga_bus_init(struct ifpga_hw *hw)
816 fme_hw_init(&hw->fme);
817 for (i = 0; i < MAX_FPGA_PORT_NUM; i++)
818 port_hw_init(&hw->port[i]);