1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
5 #include "opae_hw_api.h"
9 #include "ifpga_enumerate.h"
10 #include "ifpga_feature_dev.h"
12 struct build_feature_devs_info {
13 struct opae_adapter_data_pci *pci_data;
15 struct ifpga_afu_info *acc_info;
18 enum fpga_id_type current_type;
31 static int feature_revision(void __iomem *start)
33 struct feature_header header;
35 header.csr = readq(start);
37 return header.revision;
40 static u32 feature_size(void __iomem *start)
42 struct feature_header header;
44 header.csr = readq(start);
46 /*the size of private feature is 4KB aligned*/
47 return header.next_header_offset ? header.next_header_offset:4096;
50 static u64 feature_id(void __iomem *start)
52 struct feature_header header;
54 header.csr = readq(start);
56 switch (header.type) {
57 case FEATURE_TYPE_FIU:
58 return FEATURE_ID_FIU_HEADER;
59 case FEATURE_TYPE_PRIVATE:
61 case FEATURE_TYPE_AFU:
62 return FEATURE_ID_AFU;
70 build_info_add_sub_feature(struct build_feature_devs_info *binfo,
71 void __iomem *start, u64 fid, unsigned int size,
72 unsigned int vec_start,
75 struct ifpga_hw *hw = binfo->hw;
76 struct feature *feature = NULL;
77 struct feature_irq_ctx *ctx = NULL;
81 fid = fid?fid:feature_id(start);
82 size = size?size:feature_size(start);
84 feature = opae_malloc(sizeof(struct feature));
88 feature->state = IFPGA_FEATURE_ATTACHED;
89 feature->addr = start;
92 feature->revision = feature_revision(start);
93 feature->phys_addr = binfo->phys_addr +
94 ((u8 *)start - (u8 *)binfo->ioaddr);
95 feature->vec_start = vec_start;
96 feature->vec_cnt = vec_cnt;
98 dev_debug(binfo, "%s: id=0x%llx, phys_addr=0x%llx, size=%u\n",
99 __func__, (unsigned long long)feature->id,
100 (unsigned long long)feature->phys_addr, size);
103 if (vec_start + vec_cnt <= vec_start)
106 ctx = zmalloc(sizeof(*ctx) * vec_cnt);
110 for (i = 0; i < vec_cnt; i++) {
112 ctx[i].idx = vec_start + i;
117 feature->ctx_num = vec_cnt;
118 feature->vfio_dev_fd = binfo->pci_data->vfio_dev_fd;
120 if (binfo->current_type == FME_ID) {
121 feature->parent = &hw->fme;
122 feature->type = FEATURE_FME_TYPE;
123 feature->name = get_fme_feature_name(fid);
124 TAILQ_INSERT_TAIL(&hw->fme.feature_list, feature, next);
125 } else if (binfo->current_type == PORT_ID) {
126 port_id = binfo->current_port_id;
127 feature->parent = &hw->port[port_id];
128 feature->type = FEATURE_PORT_TYPE;
129 feature->name = get_port_feature_name(fid);
130 TAILQ_INSERT_TAIL(&hw->port[port_id].feature_list,
139 create_feature_instance(struct build_feature_devs_info *binfo,
140 void __iomem *start, u64 fid,
141 unsigned int size, unsigned int vec_start,
142 unsigned int vec_cnt)
144 return build_info_add_sub_feature(binfo, start, fid, size, vec_start,
149 * UAFU GUID is dynamic as it can be changed after FME downloads different
150 * Green Bitstream to the port, so we treat the unknown GUIDs which are
151 * attached on port's feature list as UAFU.
153 static bool feature_is_UAFU(struct build_feature_devs_info *binfo)
155 if (binfo->current_type != PORT_ID)
161 static int parse_feature_port_uafu(struct build_feature_devs_info *binfo,
162 struct feature_header *hdr)
164 u64 id = PORT_FEATURE_ID_UAFU;
165 struct ifpga_afu_info *info;
166 void *start = (void *)hdr;
167 struct feature_port_header *port_hdr = binfo->ioaddr;
168 struct feature_port_capability capability;
172 capability.csr = readq(&port_hdr->capability);
174 size = capability.mmio_size << 10;
176 ret = create_feature_instance(binfo, hdr, id, size, 0, 0);
180 info = opae_malloc(sizeof(*info));
184 info->region[0].addr = start;
185 info->region[0].phys_addr = binfo->phys_addr +
186 (uint8_t *)start - (uint8_t *)binfo->ioaddr;
187 info->region[0].len = size;
188 info->num_regions = 1;
190 binfo->acc_info = info;
195 static int parse_feature_afus(struct build_feature_devs_info *binfo,
196 struct feature_header *hdr)
199 struct feature_afu_header *afu_hdr, header;
201 u8 __iomem *end = binfo->ioend;
203 start = (u8 __iomem *)hdr;
204 for (; start < end; start += header.next_afu) {
205 if ((unsigned int)(end - start) <
206 (unsigned int)(sizeof(*afu_hdr) + sizeof(*hdr)))
209 hdr = (struct feature_header *)start;
210 afu_hdr = (struct feature_afu_header *)(hdr + 1);
211 header.csr = readq(&afu_hdr->csr);
213 if (feature_is_UAFU(binfo)) {
214 ret = parse_feature_port_uafu(binfo, hdr);
219 if (!header.next_afu)
226 /* create and register proper private data */
227 static int build_info_commit_dev(struct build_feature_devs_info *binfo)
229 struct ifpga_afu_info *info = binfo->acc_info;
230 struct ifpga_hw *hw = binfo->hw;
231 struct opae_manager *mgr;
232 struct opae_bridge *br;
233 struct opae_accelerator *acc;
234 struct ifpga_port_hw *port;
235 struct feature *feature;
240 if (binfo->current_type == PORT_ID) {
241 /* return error if no valid acc info data structure */
245 br = opae_bridge_alloc(hw->adapter->name, &ifpga_br_ops,
250 br->id = binfo->current_port_id;
252 /* update irq info */
253 port = &hw->port[binfo->current_port_id];
254 feature = get_feature_by_id(&port->feature_list,
255 PORT_FEATURE_ID_UINT);
257 info->num_irqs = feature->vec_cnt;
259 acc = opae_accelerator_alloc(hw->adapter->name,
260 &ifpga_acc_ops, info);
262 opae_bridge_free(br);
269 opae_adapter_add_acc(hw->adapter, acc);
271 } else if (binfo->current_type == FME_ID) {
272 mgr = opae_manager_alloc(hw->adapter->name, &ifpga_mgr_ops,
273 &ifpga_mgr_network_ops, binfo->fiu);
277 mgr->adapter = hw->adapter;
278 hw->adapter->mgr = mgr;
287 build_info_create_dev(struct build_feature_devs_info *binfo,
288 enum fpga_id_type type, unsigned int index)
292 ret = build_info_commit_dev(binfo);
296 binfo->current_type = type;
298 if (type == FME_ID) {
299 binfo->fiu = &binfo->hw->fme;
300 } else if (type == PORT_ID) {
301 binfo->fiu = &binfo->hw->port[index];
302 binfo->current_port_id = index;
308 static int parse_feature_fme(struct build_feature_devs_info *binfo,
309 struct feature_header *start)
311 struct ifpga_hw *hw = binfo->hw;
312 struct ifpga_fme_hw *fme = &hw->fme;
315 ret = build_info_create_dev(binfo, FME_ID, 0);
319 /* Update FME states */
320 fme->state = IFPGA_FME_IMPLEMENTED;
322 TAILQ_INIT(&fme->feature_list);
323 spinlock_init(&fme->lock);
325 return create_feature_instance(binfo, start, 0, 0, 0, 0);
328 static int parse_feature_port(struct build_feature_devs_info *binfo,
331 struct feature_port_header *port_hdr;
332 struct feature_port_capability capability;
333 struct ifpga_hw *hw = binfo->hw;
334 struct ifpga_port_hw *port;
335 unsigned int port_id;
338 /* Get current port's id */
339 port_hdr = (struct feature_port_header *)start;
340 capability.csr = readq(&port_hdr->capability);
341 port_id = capability.port_number;
343 ret = build_info_create_dev(binfo, PORT_ID, port_id);
347 /*found a Port device*/
348 port = &hw->port[port_id];
349 port->port_id = binfo->current_port_id;
351 port->state = IFPGA_PORT_ATTACHED;
352 spinlock_init(&port->lock);
353 TAILQ_INIT(&port->feature_list);
355 return create_feature_instance(binfo, start, 0, 0, 0, 0);
358 static void enable_port_uafu(struct build_feature_devs_info *binfo,
361 struct ifpga_port_hw *port = &binfo->hw->port[binfo->current_port_id];
365 fpga_port_reset(port);
368 static int parse_feature_fiu(struct build_feature_devs_info *binfo,
369 struct feature_header *hdr)
371 struct feature_header header;
372 struct feature_fiu_header *fiu_hdr, fiu_header;
373 u8 __iomem *start = (u8 __iomem *)hdr;
376 header.csr = readq(hdr);
379 case FEATURE_FIU_ID_FME:
380 ret = parse_feature_fme(binfo, hdr);
381 binfo->pfme_hdr = hdr;
385 case FEATURE_FIU_ID_PORT:
386 ret = parse_feature_port(binfo, hdr);
387 enable_port_uafu(binfo, hdr);
391 /* Check Port FIU's next_afu pointer to User AFU DFH */
392 fiu_hdr = (struct feature_fiu_header *)(hdr + 1);
393 fiu_header.csr = readq(&fiu_hdr->csr);
395 if (fiu_header.next_afu) {
396 start += fiu_header.next_afu;
397 ret = parse_feature_afus(binfo,
398 (struct feature_header *)start);
402 dev_info(binfo, "No AFUs detected on Port\n");
407 dev_info(binfo, "FIU TYPE %d is not supported yet.\n",
414 static void parse_feature_irqs(struct build_feature_devs_info *binfo,
415 void __iomem *start, unsigned int *vec_start,
416 unsigned int *vec_cnt)
421 id = feature_id(start);
423 if (id == PORT_FEATURE_ID_UINT) {
424 struct feature_port_uint *port_uint = start;
425 struct feature_port_uint_cap uint_cap;
427 uint_cap.csr = readq(&port_uint->capability);
428 if (uint_cap.intr_num) {
429 *vec_start = uint_cap.first_vec_num;
430 *vec_cnt = uint_cap.intr_num;
432 dev_debug(binfo, "UAFU doesn't support interrupt\n");
434 } else if (id == PORT_FEATURE_ID_ERROR) {
435 struct feature_port_error *port_err = start;
436 struct feature_port_err_capability port_err_cap;
438 port_err_cap.csr = readq(&port_err->error_capability);
439 if (port_err_cap.support_intr) {
440 *vec_start = port_err_cap.intr_vector_num;
443 dev_debug(&binfo, "Port error doesn't support interrupt\n");
446 } else if (id == FME_FEATURE_ID_GLOBAL_ERR) {
447 struct feature_fme_err *fme_err = start;
448 struct feature_fme_error_capability fme_err_cap;
450 fme_err_cap.csr = readq(&fme_err->fme_err_capability);
451 if (fme_err_cap.support_intr) {
452 *vec_start = fme_err_cap.intr_vector_num;
455 dev_debug(&binfo, "FME error doesn't support interrupt\n");
460 static int parse_feature_fme_private(struct build_feature_devs_info *binfo,
461 struct feature_header *hdr)
463 unsigned int vec_start = 0;
464 unsigned int vec_cnt = 0;
466 parse_feature_irqs(binfo, hdr, &vec_start, &vec_cnt);
468 return create_feature_instance(binfo, hdr, 0, 0, vec_start, vec_cnt);
471 static int parse_feature_port_private(struct build_feature_devs_info *binfo,
472 struct feature_header *hdr)
474 unsigned int vec_start = 0;
475 unsigned int vec_cnt = 0;
477 parse_feature_irqs(binfo, hdr, &vec_start, &vec_cnt);
479 return create_feature_instance(binfo, hdr, 0, 0, vec_start, vec_cnt);
482 static int parse_feature_private(struct build_feature_devs_info *binfo,
483 struct feature_header *hdr)
485 struct feature_header header;
487 header.csr = readq(hdr);
489 switch (binfo->current_type) {
491 return parse_feature_fme_private(binfo, hdr);
493 return parse_feature_port_private(binfo, hdr);
495 dev_err(binfo, "private feature %x belonging to AFU %d (unknown_type) is not supported yet.\n",
496 header.id, binfo->current_type);
501 static int parse_feature(struct build_feature_devs_info *binfo,
502 struct feature_header *hdr)
504 struct feature_header header;
507 header.csr = readq(hdr);
509 switch (header.type) {
510 case FEATURE_TYPE_AFU:
511 ret = parse_feature_afus(binfo, hdr);
513 case FEATURE_TYPE_PRIVATE:
514 ret = parse_feature_private(binfo, hdr);
516 case FEATURE_TYPE_FIU:
517 ret = parse_feature_fiu(binfo, hdr);
520 dev_err(binfo, "Feature Type %x is not supported.\n",
528 parse_feature_list(struct build_feature_devs_info *binfo, u8 __iomem *start)
530 struct feature_header *hdr, header;
531 u8 __iomem *end = (u8 __iomem *)binfo->ioend;
534 for (; start < end; start += header.next_header_offset) {
535 if ((unsigned int)(end - start) < (unsigned int)sizeof(*hdr)) {
536 dev_err(binfo, "The region is too small to contain a feature.\n");
541 hdr = (struct feature_header *)start;
542 header.csr = readq(hdr);
544 dev_debug(binfo, "%s: address=0x%p, val=0x%llx, header.id=0x%x, header.next_offset=0x%x, header.eol=0x%x, header.type=0x%x\n",
545 __func__, hdr, (unsigned long long)header.csr,
546 header.id, header.next_header_offset,
547 header.end_of_list, header.type);
549 ret = parse_feature(binfo, hdr);
553 if (header.end_of_list || !header.next_header_offset)
557 return build_info_commit_dev(binfo);
560 /* switch the memory mapping to BAR# @bar */
561 static int parse_switch_to(struct build_feature_devs_info *binfo, int bar)
563 struct opae_adapter_data_pci *pci_data = binfo->pci_data;
565 if (!pci_data->region[bar].addr)
568 binfo->ioaddr = pci_data->region[bar].addr;
569 binfo->ioend = (u8 __iomem *)binfo->ioaddr + pci_data->region[bar].len;
570 binfo->phys_addr = pci_data->region[bar].phys_addr;
571 binfo->current_bar = bar;
576 static int parse_ports_from_fme(struct build_feature_devs_info *binfo)
578 struct feature_fme_header *fme_hdr;
579 struct feature_fme_port port;
582 if (!binfo->pfme_hdr) {
583 dev_info(binfo, "VF is detected.\n");
587 fme_hdr = binfo->pfme_hdr;
590 port.csr = readq(&fme_hdr->port[i]);
591 if (!port.port_implemented)
594 /* skip port which only could be accessed via VF */
595 if (port.afu_access_control == FME_AFU_ACCESS_VF)
598 ret = parse_switch_to(binfo, port.port_bar);
602 ret = parse_feature_list(binfo,
603 (u8 __iomem *)binfo->ioaddr +
607 } while (++i < MAX_FPGA_PORT_NUM);
612 static struct build_feature_devs_info *
613 build_info_alloc_and_init(struct ifpga_hw *hw)
615 struct build_feature_devs_info *binfo;
617 binfo = zmalloc(sizeof(*binfo));
622 binfo->pci_data = hw->pci_data;
624 /* fpga feature list starts from BAR 0 */
625 if (parse_switch_to(binfo, 0)) {
633 static void build_info_free(struct build_feature_devs_info *binfo)
638 static void ifpga_print_device_feature_list(struct ifpga_hw *hw)
640 struct ifpga_fme_hw *fme = &hw->fme;
641 struct ifpga_port_hw *port;
642 struct feature *feature;
645 dev_info(hw, "found fme_device, is in PF: %s\n",
646 is_ifpga_hw_pf(hw) ? "yes" : "no");
648 ifpga_for_each_fme_feature(fme, feature) {
649 if (feature->state != IFPGA_FEATURE_ATTACHED)
652 dev_info(hw, "%12s: %p - %p - paddr: 0x%lx\n",
653 feature->name, feature->addr,
654 feature->addr + feature->size - 1,
655 (unsigned long)feature->phys_addr);
659 for (i = 0; i < MAX_FPGA_PORT_NUM; i++) {
662 if (port->state != IFPGA_PORT_ATTACHED)
665 dev_info(hw, "port device: %d\n", port->port_id);
667 ifpga_for_each_port_feature(port, feature) {
668 if (feature->state != IFPGA_FEATURE_ATTACHED)
671 dev_info(hw, "%12s: %p - %p - paddr:0x%lx\n",
676 (unsigned long)feature->phys_addr);
682 int ifpga_bus_enumerate(struct ifpga_hw *hw)
684 struct build_feature_devs_info *binfo;
687 binfo = build_info_alloc_and_init(hw);
691 ret = parse_feature_list(binfo, binfo->ioaddr);
695 ret = parse_ports_from_fme(binfo);
699 ifpga_print_device_feature_list(hw);
702 build_info_free(binfo);
706 int ifpga_bus_init(struct ifpga_hw *hw)
709 struct ifpga_port_hw *port;
711 fme_hw_init(&hw->fme);
712 for (i = 0; i < MAX_FPGA_PORT_NUM; i++) {