1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2019 Intel Corporation
5 #include "opae_osdep.h"
8 static int nios_spi_indirect_read(struct altera_spi_device *dev, u32 reg,
13 int loops = SPI_MAX_RETRY;
15 ctrl = NIOS_SPI_RD | ((u64)reg << 32);
16 opae_writeq(ctrl, dev->regs + NIOS_SPI_CTRL);
18 stat = opae_readq(dev->regs + NIOS_SPI_STAT);
19 while (!(stat & NIOS_SPI_VALID) && --loops)
20 stat = opae_readq(dev->regs + NIOS_SPI_STAT);
22 *val = stat & NIOS_SPI_READ_DATA;
24 return loops ? 0 : -ETIMEDOUT;
27 static int nios_spi_indirect_write(struct altera_spi_device *dev, u32 reg,
33 int loops = SPI_MAX_RETRY;
35 ctrl |= NIOS_SPI_WR | (u64)reg << 32;
36 ctrl |= value & NIOS_SPI_WRITE_DATA;
38 opae_writeq(ctrl, dev->regs + NIOS_SPI_CTRL);
40 stat = opae_readq(dev->regs + NIOS_SPI_STAT);
41 while (!(stat & NIOS_SPI_VALID) && --loops)
42 stat = opae_readq(dev->regs + NIOS_SPI_STAT);
44 return loops ? 0 : -ETIMEDOUT;
47 static int spi_indirect_write(struct altera_spi_device *dev, u32 reg,
52 opae_writeq(value & WRITE_DATA_MASK, dev->regs + SPI_WRITE);
54 ctrl = CTRL_W | (reg >> 2);
55 opae_writeq(ctrl, dev->regs + SPI_CTRL);
60 static int spi_indirect_read(struct altera_spi_device *dev, u32 reg,
66 ctrl = CTRL_R | (reg >> 2);
67 opae_writeq(ctrl, dev->regs + SPI_CTRL);
70 * FIXME: Read one more time to avoid HW timing issue. This is
71 * a short term workaround solution, and must be removed once
72 * hardware fixing is done.
74 tmp = opae_readq(dev->regs + SPI_READ);
81 int spi_reg_write(struct altera_spi_device *dev, u32 reg,
84 return dev->reg_write(dev, reg, value);
87 int spi_reg_read(struct altera_spi_device *dev, u32 reg,
90 return dev->reg_read(dev, reg, val);
93 void spi_cs_activate(struct altera_spi_device *dev, unsigned int chip_select)
95 spi_reg_write(dev, ALTERA_SPI_SLAVE_SEL, 1 << chip_select);
96 spi_reg_write(dev, ALTERA_SPI_CONTROL, ALTERA_SPI_CONTROL_SSO_MSK);
99 void spi_cs_deactivate(struct altera_spi_device *dev)
101 spi_reg_write(dev, ALTERA_SPI_CONTROL, 0);
104 static int spi_flush_rx(struct altera_spi_device *dev)
109 ret = spi_reg_read(dev, ALTERA_SPI_STATUS, &val);
113 if (val & ALTERA_SPI_STATUS_RRDY_MSK) {
114 ret = spi_reg_read(dev, ALTERA_SPI_RXDATA, &val);
122 static unsigned int spi_write_bytes(struct altera_spi_device *dev, int count)
124 unsigned int val = 0;
129 switch (dev->data_width) {
131 val = dev->txbuf[count];
134 p16 = (u16 *)(dev->txbuf + 2*count);
136 if (dev->endian == SPI_BIG_ENDIAN)
137 val = cpu_to_be16(val);
140 p32 = (u32 *)(dev->txbuf + 4*count);
149 static void spi_fill_readbuffer(struct altera_spi_device *dev,
150 unsigned int value, int count)
156 switch (dev->data_width) {
158 dev->rxbuf[count] = value;
161 p16 = (u16 *)(dev->rxbuf + 2*count);
162 if (dev->endian == SPI_BIG_ENDIAN)
163 *p16 = cpu_to_be16((u16)value);
168 p32 = (u32 *)(dev->rxbuf + 4*count);
169 if (dev->endian == SPI_BIG_ENDIAN)
170 *p32 = cpu_to_be32(value);
178 static int spi_txrx(struct altera_spi_device *dev)
180 unsigned int count = 0;
182 unsigned int tx_data;
187 while (count < dev->len) {
188 tx_data = spi_write_bytes(dev, count);
189 spi_reg_write(dev, ALTERA_SPI_TXDATA, tx_data);
192 ret = spi_reg_read(dev, ALTERA_SPI_STATUS, &status);
195 if (status & ALTERA_SPI_STATUS_RRDY_MSK)
197 if (retry++ > SPI_MAX_RETRY) {
198 dev_err(dev, "%s, read timeout\n", __func__);
203 ret = spi_reg_read(dev, ALTERA_SPI_RXDATA, &rxd);
207 spi_fill_readbuffer(dev, rxd, count);
215 int spi_command(struct altera_spi_device *dev, unsigned int chip_select,
216 unsigned int wlen, void *wdata,
217 unsigned int rlen, void *rdata)
219 if (((wlen > 0) && !wdata) || ((rlen > 0) && !rdata)) {
220 dev_err(dev, "error on spi command checking\n");
224 wlen = wlen / dev->data_width;
225 rlen = rlen / dev->data_width;
227 /* flush rx buffer */
230 spi_cs_activate(dev, chip_select);
243 spi_cs_deactivate(dev);
247 struct altera_spi_device *altera_spi_alloc(void *base, int type)
249 struct altera_spi_device *spi_dev =
250 opae_malloc(sizeof(struct altera_spi_device));
255 spi_dev->regs = base;
259 spi_dev->reg_read = spi_indirect_read;
260 spi_dev->reg_write = spi_indirect_write;
263 spi_dev->reg_read = nios_spi_indirect_read;
264 spi_dev->reg_write = nios_spi_indirect_write;
267 dev_err(dev, "%s: invalid SPI type\n", __func__);
274 altera_spi_release(spi_dev);
278 void altera_spi_init(struct altera_spi_device *spi_dev)
280 spi_dev->spi_param.info = opae_readq(spi_dev->regs + SPI_CORE_PARAM);
282 spi_dev->data_width = spi_dev->spi_param.data_width / 8;
283 spi_dev->endian = spi_dev->spi_param.endian;
284 spi_dev->num_chipselect = spi_dev->spi_param.num_chipselect;
285 dev_info(spi_dev, "spi param: type=%d, data width:%d, endian:%d, clock_polarity=%d, clock=%dMHz, chips=%d, cpha=%d\n",
286 spi_dev->spi_param.type,
287 spi_dev->data_width, spi_dev->endian,
288 spi_dev->spi_param.clock_polarity,
289 spi_dev->spi_param.clock,
290 spi_dev->num_chipselect,
291 spi_dev->spi_param.clock_phase);
294 spi_reg_write(spi_dev, ALTERA_SPI_CONTROL, 0);
295 spi_reg_write(spi_dev, ALTERA_SPI_STATUS, 0);
297 spi_flush_rx(spi_dev);
300 void altera_spi_release(struct altera_spi_device *dev)