1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
13 #include <rte_eal_memconfig.h>
14 #include <rte_malloc.h>
15 #include <rte_devargs.h>
16 #include <rte_memcpy.h>
18 #include <rte_bus_pci.h>
19 #include <rte_kvargs.h>
20 #include <rte_alarm.h>
22 #include <rte_errno.h>
23 #include <rte_per_lcore.h>
24 #include <rte_memory.h>
25 #include <rte_memzone.h>
27 #include <rte_common.h>
28 #include <rte_bus_vdev.h>
30 #include "base/opae_hw_api.h"
31 #include "rte_rawdev.h"
32 #include "rte_rawdev_pmd.h"
33 #include "rte_bus_ifpga.h"
34 #include "ifpga_common.h"
35 #include "ifpga_logs.h"
36 #include "ifpga_rawdev.h"
37 #include "ipn3ke_rawdev_api.h"
39 int ifpga_rawdev_logtype;
41 #define PCI_VENDOR_ID_INTEL 0x8086
43 #define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
44 #define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
45 #define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
46 #define PCIE_DEVICE_ID_PAC_N3000 0x0B30
48 #define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
49 #define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
50 #define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
51 #define PCIE_DEVICE_ID_VF_PAC_N3000 0x0B31
52 #define RTE_MAX_RAW_DEVICE 10
54 static const struct rte_pci_id pci_ifpga_map[] = {
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
63 { .vendor_id = 0, /* sentinel */ },
67 ifpga_fill_afu_dev(struct opae_accelerator *acc,
68 struct rte_afu_device *afu_dev)
70 struct rte_mem_resource *res = afu_dev->mem_resource;
71 struct opae_acc_region_info region_info;
72 struct opae_acc_info info;
76 ret = opae_acc_get_info(acc, &info);
80 if (info.num_regions > PCI_MAX_RESOURCE)
83 afu_dev->num_region = info.num_regions;
85 for (i = 0; i < info.num_regions; i++) {
86 region_info.index = i;
87 ret = opae_acc_get_region_info(acc, ®ion_info);
91 if ((region_info.flags & ACC_REGION_MMIO) &&
92 (region_info.flags & ACC_REGION_READ) &&
93 (region_info.flags & ACC_REGION_WRITE)) {
94 res[i].phys_addr = region_info.phys_addr;
95 res[i].len = region_info.len;
96 res[i].addr = region_info.addr;
105 ifpga_rawdev_info_get(struct rte_rawdev *dev,
106 rte_rawdev_obj_t dev_info)
108 struct opae_adapter *adapter;
109 struct opae_accelerator *acc;
110 struct rte_afu_device *afu_dev;
111 struct opae_manager *mgr = NULL;
112 struct opae_eth_group_region_info opae_lside_eth_info;
113 struct opae_eth_group_region_info opae_nside_eth_info;
114 int lside_bar_idx, nside_bar_idx;
116 IFPGA_RAWDEV_PMD_FUNC_TRACE();
119 IFPGA_RAWDEV_PMD_ERR("Invalid request");
123 adapter = ifpga_rawdev_get_priv(dev);
128 afu_dev->rawdev = dev;
130 /* find opae_accelerator and fill info into afu_device */
131 opae_adapter_for_each_acc(adapter, acc) {
132 if (acc->index != afu_dev->id.port)
135 if (ifpga_fill_afu_dev(acc, afu_dev)) {
136 IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
141 /* get opae_manager to rawdev */
142 mgr = opae_adapter_get_mgr(adapter);
144 /* get LineSide BAR Index */
145 if (opae_manager_get_eth_group_region_info(mgr, 0,
146 &opae_lside_eth_info)) {
149 lside_bar_idx = opae_lside_eth_info.mem_idx;
151 /* get NICSide BAR Index */
152 if (opae_manager_get_eth_group_region_info(mgr, 1,
153 &opae_nside_eth_info)) {
156 nside_bar_idx = opae_nside_eth_info.mem_idx;
158 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
159 nside_bar_idx >= PCI_MAX_RESOURCE ||
160 lside_bar_idx == nside_bar_idx)
163 /* fill LineSide BAR Index */
164 afu_dev->mem_resource[lside_bar_idx].phys_addr =
165 opae_lside_eth_info.phys_addr;
166 afu_dev->mem_resource[lside_bar_idx].len =
167 opae_lside_eth_info.len;
168 afu_dev->mem_resource[lside_bar_idx].addr =
169 opae_lside_eth_info.addr;
171 /* fill NICSide BAR Index */
172 afu_dev->mem_resource[nside_bar_idx].phys_addr =
173 opae_nside_eth_info.phys_addr;
174 afu_dev->mem_resource[nside_bar_idx].len =
175 opae_nside_eth_info.len;
176 afu_dev->mem_resource[nside_bar_idx].addr =
177 opae_nside_eth_info.addr;
182 ifpga_rawdev_configure(const struct rte_rawdev *dev,
183 rte_rawdev_obj_t config)
185 IFPGA_RAWDEV_PMD_FUNC_TRACE();
187 RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
189 return config ? 0 : 1;
193 ifpga_rawdev_start(struct rte_rawdev *dev)
196 struct opae_adapter *adapter;
198 IFPGA_RAWDEV_PMD_FUNC_TRACE();
200 RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
202 adapter = ifpga_rawdev_get_priv(dev);
210 ifpga_rawdev_stop(struct rte_rawdev *dev)
216 ifpga_rawdev_close(struct rte_rawdev *dev)
222 ifpga_rawdev_reset(struct rte_rawdev *dev)
228 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, u64 *buffer, u32 size,
232 struct opae_adapter *adapter;
233 struct opae_manager *mgr;
234 struct opae_accelerator *acc;
235 struct opae_bridge *br;
238 adapter = ifpga_rawdev_get_priv(raw_dev);
242 mgr = opae_adapter_get_mgr(adapter);
246 acc = opae_adapter_get_acc(adapter, port_id);
250 br = opae_acc_get_br(acc);
254 ret = opae_manager_flash(mgr, port_id, buffer, size, status);
256 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
260 ret = opae_bridge_reset(br);
262 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
263 __func__, port_id, ret);
271 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
272 const char *file_name)
274 struct stat file_stat;
284 file_fd = open(file_name, O_RDONLY);
286 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
287 __func__, file_name);
288 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
291 ret = stat(file_name, &file_stat);
293 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
298 buffer_size = file_stat.st_size;
299 IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
300 buffer = rte_malloc(NULL, buffer_size, 0);
306 /*read the raw data*/
307 if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
313 ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
314 IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
315 ret ? "failed" : "success");
331 ifpga_rawdev_pr(struct rte_rawdev *dev,
332 rte_rawdev_obj_t pr_conf)
334 struct opae_adapter *adapter;
335 struct rte_afu_pr_conf *afu_pr_conf;
338 struct opae_accelerator *acc;
340 IFPGA_RAWDEV_PMD_FUNC_TRACE();
342 adapter = ifpga_rawdev_get_priv(dev);
349 afu_pr_conf = pr_conf;
351 if (afu_pr_conf->pr_enable) {
352 ret = rte_fpga_do_pr(dev,
353 afu_pr_conf->afu_id.port,
354 afu_pr_conf->bs_path);
356 IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
361 acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
365 ret = opae_acc_get_uuid(acc, &uuid);
369 memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b, sizeof(u64));
370 memcpy(&afu_pr_conf->afu_id.uuid.uuid_high, uuid.b + 8, sizeof(u64));
372 IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n", __func__,
373 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
374 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
380 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
381 const char *attr_name, uint64_t *attr_value)
383 struct opae_adapter *adapter;
384 struct opae_manager *mgr;
385 struct opae_retimer_info opae_rtm_info;
386 struct opae_retimer_status opae_rtm_status;
387 struct opae_eth_group_info opae_eth_grp_info;
388 struct opae_eth_group_region_info opae_eth_grp_reg_info;
389 int eth_group_num = 0;
390 uint64_t port_link_bitmap = 0, port_link_bit;
393 #define MAX_PORT_PER_RETIMER 4
395 IFPGA_RAWDEV_PMD_FUNC_TRACE();
397 if (!dev || !attr_name || !attr_value) {
398 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
402 adapter = ifpga_rawdev_get_priv(dev);
404 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
408 mgr = opae_adapter_get_mgr(adapter);
410 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
414 /* currently, eth_group_num is always 2 */
415 eth_group_num = opae_manager_get_eth_group_nums(mgr);
416 if (eth_group_num < 0)
419 if (!strcmp(attr_name, "LineSideBaseMAC")) {
420 /* Currently FPGA not implement, so just set all zeros*/
421 *attr_value = (uint64_t)0;
424 if (!strcmp(attr_name, "LineSideMACType")) {
425 /* eth_group 0 on FPGA connect to LineSide */
426 if (opae_manager_get_eth_group_info(mgr, 0,
429 switch (opae_eth_grp_info.speed) {
432 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
436 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
440 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
445 if (!strcmp(attr_name, "LineSideLinkSpeed")) {
446 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
448 switch (opae_rtm_status.speed) {
451 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
455 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
459 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
463 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
467 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
471 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
475 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
477 case MXD_SPEED_UNKNOWN:
479 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
483 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
488 if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
489 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
491 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
494 if (!strcmp(attr_name, "LineSideLinkPortNum")) {
495 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
497 uint64_t tmp = opae_rtm_info.ports_per_retimer *
498 opae_rtm_info.nums_retimer;
502 if (!strcmp(attr_name, "LineSideLinkStatus")) {
503 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
505 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
509 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
510 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
511 p = i * MAX_PORT_PER_RETIMER;
512 for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
514 IFPGA_BIT_SET(port_link_bit, (p+j));
515 port_link_bit &= port_link_bitmap;
517 IFPGA_BIT_SET((*attr_value), q);
523 if (!strcmp(attr_name, "LineSideBARIndex")) {
524 /* eth_group 0 on FPGA connect to LineSide */
525 if (opae_manager_get_eth_group_region_info(mgr, 0,
526 &opae_eth_grp_reg_info))
528 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
531 if (!strcmp(attr_name, "NICSideMACType")) {
532 /* eth_group 1 on FPGA connect to NicSide */
533 if (opae_manager_get_eth_group_info(mgr, 1,
536 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
539 if (!strcmp(attr_name, "NICSideLinkSpeed")) {
540 /* eth_group 1 on FPGA connect to NicSide */
541 if (opae_manager_get_eth_group_info(mgr, 1,
544 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
547 if (!strcmp(attr_name, "NICSideLinkPortNum")) {
548 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
550 uint64_t tmp = opae_rtm_info.nums_fvl *
551 opae_rtm_info.ports_per_fvl;
555 if (!strcmp(attr_name, "NICSideLinkStatus"))
557 if (!strcmp(attr_name, "NICSideBARIndex")) {
558 /* eth_group 1 on FPGA connect to NicSide */
559 if (opae_manager_get_eth_group_region_info(mgr, 1,
560 &opae_eth_grp_reg_info))
562 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
566 IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
570 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
571 .dev_info_get = ifpga_rawdev_info_get,
572 .dev_configure = ifpga_rawdev_configure,
573 .dev_start = ifpga_rawdev_start,
574 .dev_stop = ifpga_rawdev_stop,
575 .dev_close = ifpga_rawdev_close,
576 .dev_reset = ifpga_rawdev_reset,
578 .queue_def_conf = NULL,
580 .queue_release = NULL,
582 .attr_get = ifpga_rawdev_get_attr,
585 .enqueue_bufs = NULL,
586 .dequeue_bufs = NULL,
591 .xstats_get_names = NULL,
592 .xstats_get_by_name = NULL,
593 .xstats_reset = NULL,
595 .firmware_status_get = NULL,
596 .firmware_version_get = NULL,
597 .firmware_load = ifpga_rawdev_pr,
598 .firmware_unload = NULL,
600 .dev_selftest = NULL,
604 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
608 struct rte_rawdev *rawdev = NULL;
609 struct opae_adapter *adapter = NULL;
610 struct opae_manager *mgr = NULL;
611 struct opae_adapter_data_pci *data = NULL;
612 char name[RTE_RAWDEV_NAME_MAX_LEN];
616 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
621 memset(name, 0, sizeof(name));
622 snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%x:%02x.%x",
623 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
625 IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
627 /* Allocate device structure */
628 rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
630 if (rawdev == NULL) {
631 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
636 /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
637 data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
643 /* init opae_adapter_data_pci for device specific information */
644 for (i = 0; i < PCI_MAX_RESOURCE; i++) {
645 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
646 data->region[i].len = pci_dev->mem_resource[i].len;
647 data->region[i].addr = pci_dev->mem_resource[i].addr;
649 data->device_id = pci_dev->id.device_id;
650 data->vendor_id = pci_dev->id.vendor_id;
652 adapter = rawdev->dev_private;
653 /* create a opae_adapter based on above device data */
654 ret = opae_adapter_init(adapter, pci_dev->device.name, data);
657 goto free_adapter_data;
660 rawdev->dev_ops = &ifpga_rawdev_ops;
661 rawdev->device = &pci_dev->device;
662 rawdev->driver_name = pci_dev->driver->driver.name;
664 /* must enumerate the adapter before use it */
665 ret = opae_adapter_enumerate(adapter);
667 goto free_adapter_data;
669 /* get opae_manager to rawdev */
670 mgr = opae_adapter_get_mgr(adapter);
673 IFPGA_RAWDEV_PMD_INFO("this is a PF function");
680 opae_adapter_data_free(data);
683 rte_rawdev_pmd_release(rawdev);
689 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
692 struct rte_rawdev *rawdev;
693 char name[RTE_RAWDEV_NAME_MAX_LEN];
694 struct opae_adapter *adapter;
697 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
702 memset(name, 0, sizeof(name));
703 snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%x:%02x.%x",
704 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
706 IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
707 name, rte_socket_id());
709 rawdev = rte_rawdev_pmd_get_named_dev(name);
711 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
715 adapter = ifpga_rawdev_get_priv(rawdev);
719 opae_adapter_data_free(adapter->data);
720 opae_adapter_free(adapter);
722 /* rte_rawdev_close is called by pmd_release */
723 ret = rte_rawdev_pmd_release(rawdev);
725 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
731 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
732 struct rte_pci_device *pci_dev)
734 IFPGA_RAWDEV_PMD_FUNC_TRACE();
735 return ifpga_rawdev_create(pci_dev, rte_socket_id());
739 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
741 return ifpga_rawdev_destroy(pci_dev);
744 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
745 .id_table = pci_ifpga_map,
746 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
747 .probe = ifpga_rawdev_pci_probe,
748 .remove = ifpga_rawdev_pci_remove,
751 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
752 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
753 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
755 RTE_INIT(ifpga_rawdev_init_log)
757 ifpga_rawdev_logtype = rte_log_register("driver.raw.init");
758 if (ifpga_rawdev_logtype >= 0)
759 rte_log_set_level(ifpga_rawdev_logtype, RTE_LOG_NOTICE);
762 static const char * const valid_args[] = {
763 #define IFPGA_ARG_NAME "ifpga"
765 #define IFPGA_ARG_PORT "port"
767 #define IFPGA_AFU_BTS "afu_bts"
773 ifpga_cfg_probe(struct rte_vdev_device *dev)
775 struct rte_devargs *devargs;
776 struct rte_kvargs *kvlist = NULL;
779 char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
782 devargs = dev->device.devargs;
784 kvlist = rte_kvargs_parse(devargs->args, valid_args);
786 IFPGA_RAWDEV_PMD_LOG(ERR, "error when parsing param");
790 if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
791 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
792 &rte_ifpga_get_string_arg, &name) < 0) {
793 IFPGA_RAWDEV_PMD_ERR("error to parse %s",
798 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
803 if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
804 if (rte_kvargs_process(kvlist,
806 &rte_ifpga_get_integer32_arg,
808 IFPGA_RAWDEV_PMD_ERR("error to parse %s",
813 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
818 memset(dev_name, 0, sizeof(dev_name));
819 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
822 ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
823 dev_name, devargs->args);
826 rte_kvargs_free(kvlist);
834 ifpga_cfg_remove(struct rte_vdev_device *vdev)
836 IFPGA_RAWDEV_PMD_INFO("Remove ifpga_cfg %p",
842 static struct rte_vdev_driver ifpga_cfg_driver = {
843 .probe = ifpga_cfg_probe,
844 .remove = ifpga_cfg_remove,
847 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
848 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
849 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,