drivers/raw/ioat/idxd_pci.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2020 Intel Corporation
   3  */
   4
   5 #include <rte_bus_pci.h>
   6 #include <rte_memzone.h>
   7
   8 #include "ioat_private.h"
   9 #include "ioat_spec.h"
  10
  11 #define IDXD_VENDOR_ID          0x8086
  12 #define IDXD_DEVICE_ID_SPR      0x0B25
  13
  14 #define IDXD_PMD_RAWDEV_NAME_PCI rawdev_idxd_pci
  15
  16 const struct rte_pci_id pci_id_idxd_map[] = {
  17         { RTE_PCI_DEVICE(IDXD_VENDOR_ID, IDXD_DEVICE_ID_SPR) },
  18         { .vendor_id = 0, /* sentinel */ },
  19 };
  20
  21 static inline int
  22 idxd_pci_dev_command(struct idxd_rawdev *idxd, enum rte_idxd_cmds command)
  23 {
  24         uint8_t err_code;
  25         uint16_t qid = idxd->qid;
  26         int i = 0;
  27
  28         if (command >= idxd_disable_wq && command <= idxd_reset_wq)
  29                 qid = (1 << qid);
  30         rte_spinlock_lock(&idxd->u.pci->lk);
  31         idxd->u.pci->regs->cmd = (command << IDXD_CMD_SHIFT) | qid;
  32
  33         do {
  34                 rte_pause();
  35                 err_code = idxd->u.pci->regs->cmdstatus;
  36                 if (++i >= 1000) {
  37                         IOAT_PMD_ERR("Timeout waiting for command response from HW");
  38                         rte_spinlock_unlock(&idxd->u.pci->lk);
  39                         return err_code;
  40                 }
  41         } while (idxd->u.pci->regs->cmdstatus & CMDSTATUS_ACTIVE_MASK);
  42         rte_spinlock_unlock(&idxd->u.pci->lk);
  43
  44         return err_code & CMDSTATUS_ERR_MASK;
  45 }
  46
  47 static int
  48 idxd_is_wq_enabled(struct idxd_rawdev *idxd)
  49 {
  50         uint32_t state = idxd->u.pci->wq_regs[idxd->qid].wqcfg[WQ_STATE_IDX];
  51         return ((state >> WQ_STATE_SHIFT) & WQ_STATE_MASK) == 0x1;
  52 }
  53
  54 static void
  55 idxd_pci_dev_stop(struct rte_rawdev *dev)
  56 {
  57         struct idxd_rawdev *idxd = dev->dev_private;
  58         uint8_t err_code;
  59
  60         if (!idxd_is_wq_enabled(idxd)) {
  61                 IOAT_PMD_ERR("Work queue %d already disabled", idxd->qid);
  62                 return;
  63         }
  64
  65         err_code = idxd_pci_dev_command(idxd, idxd_disable_wq);
  66         if (err_code || idxd_is_wq_enabled(idxd)) {
  67                 IOAT_PMD_ERR("Failed disabling work queue %d, error code: %#x",
  68                                 idxd->qid, err_code);
  69                 return;
  70         }
  71         IOAT_PMD_DEBUG("Work queue %d disabled OK", idxd->qid);
  72 }
  73
  74 static int
  75 idxd_pci_dev_start(struct rte_rawdev *dev)
  76 {
  77         struct idxd_rawdev *idxd = dev->dev_private;
  78         uint8_t err_code;
  79
  80         if (idxd_is_wq_enabled(idxd)) {
  81                 IOAT_PMD_WARN("WQ %d already enabled", idxd->qid);
  82                 return 0;
  83         }
  84
  85         if (idxd->public.batch_ring == NULL) {
  86                 IOAT_PMD_ERR("WQ %d has not been fully configured", idxd->qid);
  87                 return -EINVAL;
  88         }
  89
  90         err_code = idxd_pci_dev_command(idxd, idxd_enable_wq);
  91         if (err_code || !idxd_is_wq_enabled(idxd)) {
  92                 IOAT_PMD_ERR("Failed enabling work queue %d, error code: %#x",
  93                                 idxd->qid, err_code);
  94                 return err_code == 0 ? -1 : err_code;
  95         }
  96
  97         IOAT_PMD_DEBUG("Work queue %d enabled OK", idxd->qid);
  98
  99         return 0;
 100 }
 101
 102 static const struct rte_rawdev_ops idxd_pci_ops = {
 103                 .dev_close = idxd_rawdev_close,
 104                 .dev_selftest = idxd_rawdev_test,
 105                 .dump = idxd_dev_dump,
 106                 .dev_configure = idxd_dev_configure,
 107                 .dev_start = idxd_pci_dev_start,
 108                 .dev_stop = idxd_pci_dev_stop,
 109                 .dev_info_get = idxd_dev_info_get,
 110 };
 111
 112 /* each portal uses 4 x 4k pages */
 113 #define IDXD_PORTAL_SIZE (4096 * 4)
 114
 115 static int
 116 init_pci_device(struct rte_pci_device *dev, struct idxd_rawdev *idxd)
 117 {
 118         struct idxd_pci_common *pci;
 119         uint8_t nb_groups, nb_engines, nb_wqs;
 120         uint16_t grp_offset, wq_offset; /* how far into bar0 the regs are */
 121         uint16_t wq_size, total_wq_size;
 122         uint8_t lg2_max_batch, lg2_max_copy_size;
 123         unsigned int i, err_code;
 124
 125         pci = malloc(sizeof(*pci));
 126         if (pci == NULL) {
 127                 IOAT_PMD_ERR("%s: Can't allocate memory", __func__);
 128                 goto err;
 129         }
 130         rte_spinlock_init(&pci->lk);
 131
 132         /* assign the bar registers, and then configure device */
 133         pci->regs = dev->mem_resource[0].addr;
 134         grp_offset = (uint16_t)pci->regs->offsets[0];
 135         pci->grp_regs = RTE_PTR_ADD(pci->regs, grp_offset * 0x100);
 136         wq_offset = (uint16_t)(pci->regs->offsets[0] >> 16);
 137         pci->wq_regs = RTE_PTR_ADD(pci->regs, wq_offset * 0x100);
 138         pci->portals = dev->mem_resource[2].addr;
 139
 140         /* sanity check device status */
 141         if (pci->regs->gensts & GENSTS_DEV_STATE_MASK) {
 142                 /* need function-level-reset (FLR) or is enabled */
 143                 IOAT_PMD_ERR("Device status is not disabled, cannot init");
 144                 goto err;
 145         }
 146         if (pci->regs->cmdstatus & CMDSTATUS_ACTIVE_MASK) {
 147                 /* command in progress */
 148                 IOAT_PMD_ERR("Device has a command in progress, cannot init");
 149                 goto err;
 150         }
 151
 152         /* read basic info about the hardware for use when configuring */
 153         nb_groups = (uint8_t)pci->regs->grpcap;
 154         nb_engines = (uint8_t)pci->regs->engcap;
 155         nb_wqs = (uint8_t)(pci->regs->wqcap >> 16);
 156         total_wq_size = (uint16_t)pci->regs->wqcap;
 157         lg2_max_copy_size = (uint8_t)(pci->regs->gencap >> 16) & 0x1F;
 158         lg2_max_batch = (uint8_t)(pci->regs->gencap >> 21) & 0x0F;
 159
 160         IOAT_PMD_DEBUG("nb_groups = %u, nb_engines = %u, nb_wqs = %u",
 161                         nb_groups, nb_engines, nb_wqs);
 162
 163         /* zero out any old config */
 164         for (i = 0; i < nb_groups; i++) {
 165                 pci->grp_regs[i].grpengcfg = 0;
 166                 pci->grp_regs[i].grpwqcfg[0] = 0;
 167         }
 168         for (i = 0; i < nb_wqs; i++)
 169                 pci->wq_regs[i].wqcfg[0] = 0;
 170
 171         /* put each engine into a separate group to avoid reordering */
 172         if (nb_groups > nb_engines)
 173                 nb_groups = nb_engines;
 174         if (nb_groups < nb_engines)
 175                 nb_engines = nb_groups;
 176
 177         /* assign engines to groups, round-robin style */
 178         for (i = 0; i < nb_engines; i++) {
 179                 IOAT_PMD_DEBUG("Assigning engine %u to group %u",
 180                                 i, i % nb_groups);
 181                 pci->grp_regs[i % nb_groups].grpengcfg |= (1ULL << i);
 182         }
 183
 184         /* now do the same for queues and give work slots to each queue */
 185         wq_size = total_wq_size / nb_wqs;
 186         IOAT_PMD_DEBUG("Work queue size = %u, max batch = 2^%u, max copy = 2^%u",
 187                         wq_size, lg2_max_batch, lg2_max_copy_size);
 188         for (i = 0; i < nb_wqs; i++) {
 189                 /* add engine "i" to a group */
 190                 IOAT_PMD_DEBUG("Assigning work queue %u to group %u",
 191                                 i, i % nb_groups);
 192                 pci->grp_regs[i % nb_groups].grpwqcfg[0] |= (1ULL << i);
 193                 /* now configure it, in terms of size, max batch, mode */
 194                 pci->wq_regs[i].wqcfg[WQ_SIZE_IDX] = wq_size;
 195                 pci->wq_regs[i].wqcfg[WQ_MODE_IDX] = (1 << WQ_PRIORITY_SHIFT) |
 196                                 WQ_MODE_DEDICATED;
 197                 pci->wq_regs[i].wqcfg[WQ_SIZES_IDX] = lg2_max_copy_size |
 198                                 (lg2_max_batch << WQ_BATCH_SZ_SHIFT);
 199         }
 200
 201         /* dump the group configuration to output */
 202         for (i = 0; i < nb_groups; i++) {
 203                 IOAT_PMD_DEBUG("## Group %d", i);
 204                 IOAT_PMD_DEBUG("    GRPWQCFG: %"PRIx64, pci->grp_regs[i].grpwqcfg[0]);
 205                 IOAT_PMD_DEBUG("    GRPENGCFG: %"PRIx64, pci->grp_regs[i].grpengcfg);
 206                 IOAT_PMD_DEBUG("    GRPFLAGS: %"PRIx32, pci->grp_regs[i].grpflags);
 207         }
 208
 209         idxd->u.pci = pci;
 210         idxd->max_batches = wq_size;
 211
 212         /* enable the device itself */
 213         err_code = idxd_pci_dev_command(idxd, idxd_enable_dev);
 214         if (err_code) {
 215                 IOAT_PMD_ERR("Error enabling device: code %#x", err_code);
 216                 return err_code;
 217         }
 218         IOAT_PMD_DEBUG("IDXD Device enabled OK");
 219
 220         return nb_wqs;
 221
 222 err:
 223         free(pci);
 224         return -1;
 225 }
 226
 227 static int
 228 idxd_rawdev_probe_pci(struct rte_pci_driver *drv, struct rte_pci_device *dev)
 229 {
 230         struct idxd_rawdev idxd = {{0}}; /* Double {} to avoid error on BSD12 */
 231         uint8_t nb_wqs;
 232         int qid, ret = 0;
 233         char name[PCI_PRI_STR_SIZE];
 234
 235         rte_pci_device_name(&dev->addr, name, sizeof(name));
 236         IOAT_PMD_INFO("Init %s on NUMA node %d", name, dev->device.numa_node);
 237         dev->device.driver = &drv->driver;
 238
 239         ret = init_pci_device(dev, &idxd);
 240         if (ret < 0) {
 241                 IOAT_PMD_ERR("Error initializing PCI hardware");
 242                 return ret;
 243         }
 244         nb_wqs = (uint8_t)ret;
 245
 246         /* set up one device for each queue */
 247         for (qid = 0; qid < nb_wqs; qid++) {
 248                 char qname[32];
 249
 250                 /* add the queue number to each device name */
 251                 snprintf(qname, sizeof(qname), "%s-q%d", name, qid);
 252                 idxd.qid = qid;
 253                 idxd.public.portal = RTE_PTR_ADD(idxd.u.pci->portals,
 254                                 qid * IDXD_PORTAL_SIZE);
 255                 if (idxd_is_wq_enabled(&idxd))
 256                         IOAT_PMD_ERR("Error, WQ %u seems enabled", qid);
 257                 ret = idxd_rawdev_create(qname, &dev->device,
 258                                 &idxd, &idxd_pci_ops);
 259                 if (ret != 0) {
 260                         IOAT_PMD_ERR("Failed to create rawdev %s", name);
 261                         if (qid == 0) /* if no devices using this, free pci */
 262                                 free(idxd.u.pci);
 263                         return ret;
 264                 }
 265         }
 266
 267         return 0;
 268 }
 269
 270 static int
 271 idxd_rawdev_destroy(const char *name)
 272 {
 273         int ret;
 274         uint8_t err_code;
 275         struct rte_rawdev *rdev;
 276         struct idxd_rawdev *idxd;
 277
 278         if (!name) {
 279                 IOAT_PMD_ERR("Invalid device name");
 280                 return -EINVAL;
 281         }
 282
 283         rdev = rte_rawdev_pmd_get_named_dev(name);
 284         if (!rdev) {
 285                 IOAT_PMD_ERR("Invalid device name (%s)", name);
 286                 return -EINVAL;
 287         }
 288
 289         idxd = rdev->dev_private;
 290
 291         /* disable the device */
 292         err_code = idxd_pci_dev_command(idxd, idxd_disable_dev);
 293         if (err_code) {
 294                 IOAT_PMD_ERR("Error disabling device: code %#x", err_code);
 295                 return err_code;
 296         }
 297         IOAT_PMD_DEBUG("IDXD Device disabled OK");
 298
 299         /* free device memory */
 300         if (rdev->dev_private != NULL) {
 301                 IOAT_PMD_DEBUG("Freeing device driver memory");
 302                 rdev->dev_private = NULL;
 303                 rte_free(idxd->public.batch_ring);
 304                 rte_free(idxd->public.hdl_ring);
 305                 rte_memzone_free(idxd->mz);
 306         }
 307
 308         /* rte_rawdev_close is called by pmd_release */
 309         ret = rte_rawdev_pmd_release(rdev);
 310         if (ret)
 311                 IOAT_PMD_DEBUG("Device cleanup failed");
 312
 313         return 0;
 314 }
 315
 316 static int
 317 idxd_rawdev_remove_pci(struct rte_pci_device *dev)
 318 {
 319         char name[PCI_PRI_STR_SIZE];
 320         int ret = 0;
 321
 322         rte_pci_device_name(&dev->addr, name, sizeof(name));
 323
 324         IOAT_PMD_INFO("Closing %s on NUMA node %d",
 325                         name, dev->device.numa_node);
 326
 327         ret = idxd_rawdev_destroy(name);
 328
 329         return ret;
 330 }
 331
 332 struct rte_pci_driver idxd_pmd_drv_pci = {
 333         .id_table = pci_id_idxd_map,
 334         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 335         .probe = idxd_rawdev_probe_pci,
 336         .remove = idxd_rawdev_remove_pci,
 337 };
 338
 339 RTE_PMD_REGISTER_PCI(IDXD_PMD_RAWDEV_NAME_PCI, idxd_pmd_drv_pci);
 340 RTE_PMD_REGISTER_PCI_TABLE(IDXD_PMD_RAWDEV_NAME_PCI, pci_id_idxd_map);
 341 RTE_PMD_REGISTER_KMOD_DEP(IDXD_PMD_RAWDEV_NAME_PCI,
 342                           "* igb_uio | uio_pci_generic | vfio-pci");