1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) Intel Corporation
7 * I/OAT specification definitions
9 * Taken from ioat_spec.h from SPDK project, with prefix renames and
10 * other minor changes.
13 #ifndef RTE_IOAT_SPEC_H
14 #define RTE_IOAT_SPEC_H
22 #define RTE_IOAT_PCI_CHANERR_INT_OFFSET 0x180
24 #define RTE_IOAT_INTRCTRL_MASTER_INT_EN 0x01
26 #define RTE_IOAT_VER_3_0 0x30
27 #define RTE_IOAT_VER_3_3 0x33
29 /* DMA Channel Registers */
30 #define RTE_IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000
31 #define RTE_IOAT_CHANCTRL_COMPL_DCA_EN 0x0200
32 #define RTE_IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100
33 #define RTE_IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020
34 #define RTE_IOAT_CHANCTRL_ERR_INT_EN 0x0010
35 #define RTE_IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008
36 #define RTE_IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004
37 #define RTE_IOAT_CHANCTRL_INT_REARM 0x0001
39 /* DMA Channel Capabilities */
40 #define RTE_IOAT_DMACAP_PB (1 << 0)
41 #define RTE_IOAT_DMACAP_DCA (1 << 4)
42 #define RTE_IOAT_DMACAP_BFILL (1 << 6)
43 #define RTE_IOAT_DMACAP_XOR (1 << 8)
44 #define RTE_IOAT_DMACAP_PQ (1 << 9)
45 #define RTE_IOAT_DMACAP_DMA_DIF (1 << 10)
47 struct rte_ioat_registers {
53 uint8_t cbver; /* 0x08 */
54 uint8_t reserved4[0x3]; /* 0x09 */
55 uint16_t intrdelay; /* 0x0C */
56 uint16_t cs_status; /* 0x0E */
57 uint32_t dmacapability; /* 0x10 */
58 uint8_t reserved5[0x6C]; /* 0x14 */
59 uint16_t chanctrl; /* 0x80 */
60 uint8_t reserved6[0x2]; /* 0x82 */
61 uint8_t chancmd; /* 0x84 */
62 uint8_t reserved3[1]; /* 0x85 */
63 uint16_t dmacount; /* 0x86 */
64 uint64_t chansts; /* 0x88 */
65 uint64_t chainaddr; /* 0x90 */
66 uint64_t chancmp; /* 0x98 */
67 uint8_t reserved2[0x8]; /* 0xA0 */
68 uint32_t chanerr; /* 0xA8 */
69 uint32_t chanerrmask; /* 0xAC */
72 #define RTE_IOAT_CHANCMD_RESET 0x20
73 #define RTE_IOAT_CHANCMD_SUSPEND 0x04
75 #define RTE_IOAT_CHANSTS_STATUS 0x7ULL
76 #define RTE_IOAT_CHANSTS_ACTIVE 0x0
77 #define RTE_IOAT_CHANSTS_IDLE 0x1
78 #define RTE_IOAT_CHANSTS_SUSPENDED 0x2
79 #define RTE_IOAT_CHANSTS_HALTED 0x3
80 #define RTE_IOAT_CHANSTS_ARMED 0x4
82 #define RTE_IOAT_CHANSTS_UNAFFILIATED_ERROR 0x8ULL
83 #define RTE_IOAT_CHANSTS_SOFT_ERROR 0x10ULL
85 #define RTE_IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK (~0x3FULL)
87 #define RTE_IOAT_CHANCMP_ALIGN 8 /* CHANCMP address must be 64-bit aligned */
89 struct rte_ioat_dma_hw_desc {
94 uint32_t int_enable: 1;
95 uint32_t src_snoop_disable: 1;
96 uint32_t dest_snoop_disable: 1;
97 uint32_t completion_update: 1;
100 uint32_t src_page_break: 1;
101 uint32_t dest_page_break: 1;
103 uint32_t dest_dca: 1;
105 uint32_t reserved: 13;
106 #define RTE_IOAT_OP_COPY 0x00
119 struct rte_ioat_fill_hw_desc {
122 uint32_t control_raw;
124 uint32_t int_enable: 1;
125 uint32_t reserved: 1;
126 uint32_t dest_snoop_disable: 1;
127 uint32_t completion_update: 1;
129 uint32_t reserved2: 2;
130 uint32_t dest_page_break: 1;
132 uint32_t reserved3: 15;
133 #define RTE_IOAT_OP_FILL 0x01
141 uint64_t next_dest_addr;
146 struct rte_ioat_xor_hw_desc {
149 uint32_t control_raw;
151 uint32_t int_enable: 1;
152 uint32_t src_snoop_disable: 1;
153 uint32_t dest_snoop_disable: 1;
154 uint32_t completion_update: 1;
156 uint32_t src_count: 3;
158 uint32_t dest_dca: 1;
160 uint32_t reserved: 13;
161 #define RTE_IOAT_OP_XOR 0x87
162 #define RTE_IOAT_OP_XOR_VAL 0x88
175 struct rte_ioat_xor_ext_hw_desc {
180 uint64_t reserved[4];
183 struct rte_ioat_pq_hw_desc {
186 uint32_t control_raw;
188 uint32_t int_enable: 1;
189 uint32_t src_snoop_disable: 1;
190 uint32_t dest_snoop_disable: 1;
191 uint32_t completion_update: 1;
193 uint32_t src_count: 3;
195 uint32_t dest_dca: 1;
197 uint32_t p_disable: 1;
198 uint32_t q_disable: 1;
199 uint32_t reserved: 11;
200 #define RTE_IOAT_OP_PQ 0x89
201 #define RTE_IOAT_OP_PQ_VAL 0x8a
214 struct rte_ioat_pq_ext_hw_desc {
221 uint64_t reserved[2];
224 struct rte_ioat_pq_update_hw_desc {
227 uint32_t control_raw;
229 uint32_t int_enable: 1;
230 uint32_t src_snoop_disable: 1;
231 uint32_t dest_snoop_disable: 1;
232 uint32_t completion_update: 1;
236 uint32_t dest_dca: 1;
238 uint32_t p_disable: 1;
239 uint32_t q_disable: 1;
240 uint32_t reserved: 3;
242 #define RTE_IOAT_OP_PQ_UP 0x8b
255 struct rte_ioat_raw_hw_desc {
259 union rte_ioat_hw_desc {
260 struct rte_ioat_raw_hw_desc raw;
261 struct rte_ioat_generic_hw_desc generic;
262 struct rte_ioat_dma_hw_desc dma;
263 struct rte_ioat_fill_hw_desc fill;
264 struct rte_ioat_xor_hw_desc xor_desc;
265 struct rte_ioat_xor_ext_hw_desc xor_ext;
266 struct rte_ioat_pq_hw_desc pq;
267 struct rte_ioat_pq_ext_hw_desc pq_ext;
268 struct rte_ioat_pq_update_hw_desc pq_update;
271 /*** Definitions for Intel(R) Data Streaming Accelerator Follow ***/
273 #define IDXD_CMD_SHIFT 20
287 /* General bar0 registers */
288 struct rte_idxd_bar0 {
289 uint32_t __rte_cache_aligned version; /* offset 0x00 */
290 uint64_t __rte_aligned(0x10) gencap; /* offset 0x10 */
291 uint64_t __rte_aligned(0x10) wqcap; /* offset 0x20 */
292 uint64_t __rte_aligned(0x10) grpcap; /* offset 0x30 */
293 uint64_t __rte_aligned(0x08) engcap; /* offset 0x38 */
294 uint64_t __rte_aligned(0x10) opcap; /* offset 0x40 */
295 uint64_t __rte_aligned(0x20) offsets[2]; /* offset 0x60 */
296 uint32_t __rte_aligned(0x20) gencfg; /* offset 0x80 */
297 uint32_t __rte_aligned(0x08) genctrl; /* offset 0x88 */
298 uint32_t __rte_aligned(0x10) gensts; /* offset 0x90 */
299 uint32_t __rte_aligned(0x08) intcause; /* offset 0x98 */
300 uint32_t __rte_aligned(0x10) cmd; /* offset 0xA0 */
301 uint32_t __rte_aligned(0x08) cmdstatus; /* offset 0xA8 */
302 uint64_t __rte_aligned(0x20) swerror[4]; /* offset 0xC0 */
305 /* workqueue config is provided by array of uint32_t. */
306 #define WQ_SIZE_IDX 0 /* size is in first 32-bit value */
307 #define WQ_THRESHOLD_IDX 1 /* WQ threshold second 32-bits */
308 #define WQ_MODE_IDX 2 /* WQ mode and other flags */
309 #define WQ_SIZES_IDX 3 /* WQ transfer and batch sizes */
310 #define WQ_OCC_INT_IDX 4 /* WQ occupancy interrupt handle */
311 #define WQ_OCC_LIMIT_IDX 5 /* WQ occupancy limit */
312 #define WQ_STATE_IDX 6 /* WQ state and occupancy state */
314 #define WQ_MODE_SHARED 0
315 #define WQ_MODE_DEDICATED 1
316 #define WQ_PRIORITY_SHIFT 4
317 #define WQ_BATCH_SZ_SHIFT 5
318 #define WQ_STATE_SHIFT 30
319 #define WQ_STATE_MASK 0x3
321 struct rte_idxd_grpcfg {
322 uint64_t grpwqcfg[4] __rte_cache_aligned; /* 64-byte register set */
323 uint64_t grpengcfg; /* offset 32 */
324 uint32_t grpflags; /* offset 40 */
327 #define GENSTS_DEV_STATE_MASK 0x03
328 #define CMDSTATUS_ACTIVE_SHIFT 31
329 #define CMDSTATUS_ACTIVE_MASK (1 << 31)
330 #define CMDSTATUS_ERR_MASK 0xFF
336 #endif /* RTE_IOAT_SPEC_H */