1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) Intel Corporation
7 * I/OAT specification definitions
9 * Taken from ioat_spec.h from SPDK project, with prefix renames and
10 * other minor changes.
13 #ifndef RTE_IOAT_SPEC_H
14 #define RTE_IOAT_SPEC_H
22 #define RTE_IOAT_PCI_CHANERR_INT_OFFSET 0x180
24 #define RTE_IOAT_INTRCTRL_MASTER_INT_EN 0x01
26 #define RTE_IOAT_VER_3_0 0x30
27 #define RTE_IOAT_VER_3_3 0x33
29 /* DMA Channel Registers */
30 #define RTE_IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000
31 #define RTE_IOAT_CHANCTRL_COMPL_DCA_EN 0x0200
32 #define RTE_IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100
33 #define RTE_IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020
34 #define RTE_IOAT_CHANCTRL_ERR_INT_EN 0x0010
35 #define RTE_IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008
36 #define RTE_IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004
37 #define RTE_IOAT_CHANCTRL_INT_REARM 0x0001
39 /* DMA Channel Capabilities */
40 #define RTE_IOAT_DMACAP_PB (1 << 0)
41 #define RTE_IOAT_DMACAP_DCA (1 << 4)
42 #define RTE_IOAT_DMACAP_BFILL (1 << 6)
43 #define RTE_IOAT_DMACAP_XOR (1 << 8)
44 #define RTE_IOAT_DMACAP_PQ (1 << 9)
45 #define RTE_IOAT_DMACAP_DMA_DIF (1 << 10)
47 struct rte_ioat_registers {
53 uint8_t cbver; /* 0x08 */
54 uint8_t reserved4[0x3]; /* 0x09 */
55 uint16_t intrdelay; /* 0x0C */
56 uint16_t cs_status; /* 0x0E */
57 uint32_t dmacapability; /* 0x10 */
58 uint8_t reserved5[0x6C]; /* 0x14 */
59 uint16_t chanctrl; /* 0x80 */
60 uint8_t reserved6[0x2]; /* 0x82 */
61 uint8_t chancmd; /* 0x84 */
62 uint8_t reserved3[1]; /* 0x85 */
63 uint16_t dmacount; /* 0x86 */
64 uint64_t chansts; /* 0x88 */
65 uint64_t chainaddr; /* 0x90 */
66 uint64_t chancmp; /* 0x98 */
67 uint8_t reserved2[0x8]; /* 0xA0 */
68 uint32_t chanerr; /* 0xA8 */
69 uint32_t chanerrmask; /* 0xAC */
72 #define RTE_IOAT_CHANCMD_RESET 0x20
73 #define RTE_IOAT_CHANCMD_SUSPEND 0x04
75 #define RTE_IOAT_CHANSTS_STATUS 0x7ULL
76 #define RTE_IOAT_CHANSTS_ACTIVE 0x0
77 #define RTE_IOAT_CHANSTS_IDLE 0x1
78 #define RTE_IOAT_CHANSTS_SUSPENDED 0x2
79 #define RTE_IOAT_CHANSTS_HALTED 0x3
80 #define RTE_IOAT_CHANSTS_ARMED 0x4
82 #define RTE_IOAT_CHANSTS_UNAFFILIATED_ERROR 0x8ULL
83 #define RTE_IOAT_CHANSTS_SOFT_ERROR 0x10ULL
85 #define RTE_IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK (~0x3FULL)
87 #define RTE_IOAT_CHANCMP_ALIGN 8 /* CHANCMP address must be 64-bit aligned */
89 struct rte_ioat_generic_hw_desc {
94 uint32_t int_enable: 1;
95 uint32_t src_snoop_disable: 1;
96 uint32_t dest_snoop_disable: 1;
97 uint32_t completion_update: 1;
99 uint32_t reserved2: 1;
100 uint32_t src_page_break: 1;
101 uint32_t dest_page_break: 1;
103 uint32_t dest_dca: 1;
105 uint32_t reserved: 13;
112 uint64_t op_specific[4];
115 struct rte_ioat_dma_hw_desc {
118 uint32_t control_raw;
120 uint32_t int_enable: 1;
121 uint32_t src_snoop_disable: 1;
122 uint32_t dest_snoop_disable: 1;
123 uint32_t completion_update: 1;
126 uint32_t src_page_break: 1;
127 uint32_t dest_page_break: 1;
129 uint32_t dest_dca: 1;
131 uint32_t reserved: 13;
132 #define RTE_IOAT_OP_COPY 0x00
145 struct rte_ioat_fill_hw_desc {
148 uint32_t control_raw;
150 uint32_t int_enable: 1;
151 uint32_t reserved: 1;
152 uint32_t dest_snoop_disable: 1;
153 uint32_t completion_update: 1;
155 uint32_t reserved2: 2;
156 uint32_t dest_page_break: 1;
158 uint32_t reserved3: 15;
159 #define RTE_IOAT_OP_FILL 0x01
167 uint64_t next_dest_addr;
172 struct rte_ioat_xor_hw_desc {
175 uint32_t control_raw;
177 uint32_t int_enable: 1;
178 uint32_t src_snoop_disable: 1;
179 uint32_t dest_snoop_disable: 1;
180 uint32_t completion_update: 1;
182 uint32_t src_count: 3;
184 uint32_t dest_dca: 1;
186 uint32_t reserved: 13;
187 #define RTE_IOAT_OP_XOR 0x87
188 #define RTE_IOAT_OP_XOR_VAL 0x88
201 struct rte_ioat_xor_ext_hw_desc {
206 uint64_t reserved[4];
209 struct rte_ioat_pq_hw_desc {
212 uint32_t control_raw;
214 uint32_t int_enable: 1;
215 uint32_t src_snoop_disable: 1;
216 uint32_t dest_snoop_disable: 1;
217 uint32_t completion_update: 1;
219 uint32_t src_count: 3;
221 uint32_t dest_dca: 1;
223 uint32_t p_disable: 1;
224 uint32_t q_disable: 1;
225 uint32_t reserved: 11;
226 #define RTE_IOAT_OP_PQ 0x89
227 #define RTE_IOAT_OP_PQ_VAL 0x8a
240 struct rte_ioat_pq_ext_hw_desc {
247 uint64_t reserved[2];
250 struct rte_ioat_pq_update_hw_desc {
253 uint32_t control_raw;
255 uint32_t int_enable: 1;
256 uint32_t src_snoop_disable: 1;
257 uint32_t dest_snoop_disable: 1;
258 uint32_t completion_update: 1;
262 uint32_t dest_dca: 1;
264 uint32_t p_disable: 1;
265 uint32_t q_disable: 1;
266 uint32_t reserved: 3;
268 #define RTE_IOAT_OP_PQ_UP 0x8b
281 struct rte_ioat_raw_hw_desc {
285 union rte_ioat_hw_desc {
286 struct rte_ioat_raw_hw_desc raw;
287 struct rte_ioat_generic_hw_desc generic;
288 struct rte_ioat_dma_hw_desc dma;
289 struct rte_ioat_fill_hw_desc fill;
290 struct rte_ioat_xor_hw_desc xor_desc;
291 struct rte_ioat_xor_ext_hw_desc xor_ext;
292 struct rte_ioat_pq_hw_desc pq;
293 struct rte_ioat_pq_ext_hw_desc pq_ext;
294 struct rte_ioat_pq_update_hw_desc pq_update;
301 #endif /* RTE_IOAT_SPEC_H */