1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
8 #define DPI_QUEUE_OPEN 0x1
9 #define DPI_QUEUE_CLOSE 0x2
11 /* DPI VF register offsets from VF_BAR0 */
12 #define DPI_VDMA_EN (0x0)
13 #define DPI_VDMA_REQQ_CTL (0x8)
14 #define DPI_VDMA_DBELL (0x10)
15 #define DPI_VDMA_SADDR (0x18)
16 #define DPI_VDMA_COUNTS (0x20)
17 #define DPI_VDMA_NADDR (0x28)
18 #define DPI_VDMA_IWBUSY (0x30)
19 #define DPI_VDMA_CNT (0x38)
20 #define DPI_VF_INT (0x100)
21 #define DPI_VF_INT_W1S (0x108)
22 #define DPI_VF_INT_ENA_W1C (0x110)
23 #define DPI_VF_INT_ENA_W1S (0x118)
26 #define DPI_DMA_CMD_SIZE 64
27 #define DPI_CHUNK_SIZE 1024
28 #define DPI_QUEUE_STOP 0x0
29 #define DPI_QUEUE_START 0x1
32 struct rte_pci_device *dev;
39 uint16_t pool_size_m1;
43 struct otx2_mbox *mbox;
46 struct dpi_rawdev_conf_s {
50 enum dpi_dma_queue_result_e {
51 DPI_DMA_QUEUE_SUCCESS = 0,
52 DPI_DMA_QUEUE_NO_MEMORY = -1,
53 DPI_DMA_QUEUE_INVALID_PARAM = -2,
56 #endif /* _DPI_RAWDEV_H_ */