drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2019 Marvell International Ltd.
   3  */
   4
   5 #include <string.h>
   6 #include <unistd.h>
   7 #include <dirent.h>
   8 #include <fcntl.h>
   9
  10 #include <rte_bus.h>
  11 #include <rte_bus_pci.h>
  12 #include <rte_eal.h>
  13 #include <rte_lcore.h>
  14 #include <rte_mempool.h>
  15 #include <rte_pci.h>
  16
  17 #include <rte_common.h>
  18 #include <rte_rawdev.h>
  19 #include <rte_rawdev_pmd.h>
  20
  21 #include "otx2_common.h"
  22 #include "otx2_ep_enqdeq.h"
  23
  24 static void
  25 sdp_dmazone_free(const struct rte_memzone *mz)
  26 {
  27         const struct rte_memzone *mz_tmp;
  28         int ret = 0;
  29
  30         if (mz == NULL) {
  31                 otx2_err("Memzone %s : NULL", mz->name);
  32                 return;
  33         }
  34
  35         mz_tmp = rte_memzone_lookup(mz->name);
  36         if (mz_tmp == NULL) {
  37                 otx2_err("Memzone %s Not Found", mz->name);
  38                 return;
  39         }
  40
  41         ret = rte_memzone_free(mz);
  42         if (ret)
  43                 otx2_err("Memzone free failed : ret = %d", ret);
  44
  45 }
  46
  47 /* Free IQ resources */
  48 int
  49 sdp_delete_iqs(struct sdp_device *sdpvf, uint32_t iq_no)
  50 {
  51         struct sdp_instr_queue *iq;
  52
  53         iq = sdpvf->instr_queue[iq_no];
  54         if (iq == NULL) {
  55                 otx2_err("Invalid IQ[%d]\n", iq_no);
  56                 return -ENOMEM;
  57         }
  58
  59         rte_free(iq->req_list);
  60         iq->req_list = NULL;
  61
  62         if (iq->iq_mz) {
  63                 sdp_dmazone_free(iq->iq_mz);
  64                 iq->iq_mz = NULL;
  65         }
  66
  67         rte_free(sdpvf->instr_queue[iq_no]);
  68         sdpvf->instr_queue[iq_no] = NULL;
  69
  70         sdpvf->num_iqs--;
  71
  72         otx2_info("IQ[%d] is deleted", iq_no);
  73
  74         return 0;
  75 }
  76
  77 /* IQ initialization */
  78 static int
  79 sdp_init_instr_queue(struct sdp_device *sdpvf, int iq_no)
  80 {
  81         const struct sdp_config *conf;
  82         struct sdp_instr_queue *iq;
  83         uint32_t q_size;
  84
  85         conf = sdpvf->conf;
  86         iq = sdpvf->instr_queue[iq_no];
  87         q_size = conf->iq.instr_type * conf->num_iqdef_descs;
  88
  89         /* IQ memory creation for Instruction submission to OCTEON TX2 */
  90         iq->iq_mz = rte_memzone_reserve_aligned("iqmz",
  91                                         q_size,
  92                                         rte_socket_id(),
  93                                         RTE_MEMZONE_IOVA_CONTIG,
  94                                         RTE_CACHE_LINE_SIZE);
  95         if (iq->iq_mz == NULL) {
  96                 otx2_err("IQ[%d] memzone alloc failed", iq_no);
  97                 goto iq_init_fail;
  98         }
  99
 100         iq->base_addr_dma = iq->iq_mz->iova;
 101         iq->base_addr = (uint8_t *)iq->iq_mz->addr;
 102
 103         if (conf->num_iqdef_descs & (conf->num_iqdef_descs - 1)) {
 104                 otx2_err("IQ[%d] descs not in power of 2", iq_no);
 105                 goto iq_init_fail;
 106         }
 107
 108         iq->nb_desc = conf->num_iqdef_descs;
 109
 110         /* Create a IQ request list to hold requests that have been
 111          * posted to OCTEON TX2. This list will be used for freeing the IQ
 112          * data buffer(s) later once the OCTEON TX2 fetched the requests.
 113          */
 114         iq->req_list = rte_zmalloc_socket("request_list",
 115                         (iq->nb_desc * SDP_IQREQ_LIST_SIZE),
 116                         RTE_CACHE_LINE_SIZE,
 117                         rte_socket_id());
 118         if (iq->req_list == NULL) {
 119                 otx2_err("IQ[%d] req_list alloc failed", iq_no);
 120                 goto iq_init_fail;
 121         }
 122
 123         otx2_info("IQ[%d]: base: %p basedma: %lx count: %d",
 124                      iq_no, iq->base_addr, (unsigned long)iq->base_addr_dma,
 125                      iq->nb_desc);
 126
 127         iq->sdp_dev = sdpvf;
 128         iq->q_no = iq_no;
 129         iq->fill_cnt = 0;
 130         iq->host_write_index = 0;
 131         iq->otx_read_index = 0;
 132         iq->flush_index = 0;
 133
 134         /* Initialize the spinlock for this instruction queue */
 135         rte_spinlock_init(&iq->lock);
 136         rte_spinlock_init(&iq->post_lock);
 137
 138         rte_atomic64_clear(&iq->iq_flush_running);
 139
 140         sdpvf->io_qmask.iq |= (1ull << iq_no);
 141
 142         /* Set 32B/64B mode for each input queue */
 143         if (conf->iq.instr_type == 64)
 144                 sdpvf->io_qmask.iq64B |= (1ull << iq_no);
 145
 146         iq->iqcmd_64B = (conf->iq.instr_type == 64);
 147
 148         /* Set up IQ registers */
 149         sdpvf->fn_list.setup_iq_regs(sdpvf, iq_no);
 150
 151         return 0;
 152
 153 iq_init_fail:
 154         return -ENOMEM;
 155
 156 }
 157
 158 int
 159 sdp_setup_iqs(struct sdp_device *sdpvf, uint32_t iq_no)
 160 {
 161         struct sdp_instr_queue *iq;
 162
 163         iq = (struct sdp_instr_queue *)rte_zmalloc("sdp_IQ", sizeof(*iq),
 164                                                 RTE_CACHE_LINE_SIZE);
 165         if (iq == NULL)
 166                 return -ENOMEM;
 167
 168         sdpvf->instr_queue[iq_no] = iq;
 169
 170         if (sdp_init_instr_queue(sdpvf, iq_no)) {
 171                 otx2_err("IQ init is failed");
 172                 goto delete_IQ;
 173         }
 174         otx2_info("IQ[%d] is created.", sdpvf->num_iqs);
 175
 176         sdpvf->num_iqs++;
 177
 178
 179         return 0;
 180
 181 delete_IQ:
 182         sdp_delete_iqs(sdpvf, iq_no);
 183         return -ENOMEM;
 184 }
 185
 186 static void
 187 sdp_droq_reset_indices(struct sdp_droq *droq)
 188 {
 189         droq->read_idx  = 0;
 190         droq->write_idx = 0;
 191         droq->refill_idx = 0;
 192         droq->refill_count = 0;
 193         rte_atomic64_set(&droq->pkts_pending, 0);
 194 }
 195
 196 static void
 197 sdp_droq_destroy_ring_buffers(struct sdp_device *sdpvf,
 198                                 struct sdp_droq *droq)
 199 {
 200         uint32_t idx;
 201
 202         for (idx = 0; idx < droq->nb_desc; idx++) {
 203                 if (droq->recv_buf_list[idx].buffer) {
 204                         rte_mempool_put(sdpvf->enqdeq_mpool,
 205                                 droq->recv_buf_list[idx].buffer);
 206
 207                         droq->recv_buf_list[idx].buffer = NULL;
 208                 }
 209         }
 210
 211         sdp_droq_reset_indices(droq);
 212 }
 213
 214 /* Free OQs resources */
 215 int
 216 sdp_delete_oqs(struct sdp_device *sdpvf, uint32_t oq_no)
 217 {
 218         struct sdp_droq *droq;
 219
 220         droq = sdpvf->droq[oq_no];
 221         if (droq == NULL) {
 222                 otx2_err("Invalid droq[%d]", oq_no);
 223                 return -ENOMEM;
 224         }
 225
 226         sdp_droq_destroy_ring_buffers(sdpvf, droq);
 227         rte_free(droq->recv_buf_list);
 228         droq->recv_buf_list = NULL;
 229
 230         if (droq->info_mz) {
 231                 sdp_dmazone_free(droq->info_mz);
 232                 droq->info_mz = NULL;
 233         }
 234
 235         if (droq->desc_ring_mz) {
 236                 sdp_dmazone_free(droq->desc_ring_mz);
 237                 droq->desc_ring_mz = NULL;
 238         }
 239
 240         memset(droq, 0, SDP_DROQ_SIZE);
 241
 242         rte_free(sdpvf->droq[oq_no]);
 243         sdpvf->droq[oq_no] = NULL;
 244
 245         sdpvf->num_oqs--;
 246
 247         otx2_info("OQ[%d] is deleted", oq_no);
 248         return 0;
 249 }
 250
 251 static int
 252 sdp_droq_setup_ring_buffers(struct sdp_device *sdpvf,
 253                 struct sdp_droq *droq)
 254 {
 255         struct sdp_droq_desc *desc_ring = droq->desc_ring;
 256         uint32_t idx;
 257         void *buf;
 258
 259         for (idx = 0; idx < droq->nb_desc; idx++) {
 260                 rte_mempool_get(sdpvf->enqdeq_mpool, &buf);
 261                 if (buf == NULL) {
 262                         otx2_err("OQ buffer alloc failed");
 263                         /* sdp_droq_destroy_ring_buffers(droq);*/
 264                         return -ENOMEM;
 265                 }
 266
 267                 droq->recv_buf_list[idx].buffer = buf;
 268                 droq->info_list[idx].length = 0;
 269
 270                 /* Map ring buffers into memory */
 271                 desc_ring[idx].info_ptr = (uint64_t)(droq->info_list_dma +
 272                         (idx * SDP_DROQ_INFO_SIZE));
 273
 274                 desc_ring[idx].buffer_ptr = rte_mem_virt2iova(buf);
 275         }
 276
 277         sdp_droq_reset_indices(droq);
 278
 279         return 0;
 280 }
 281
 282 static void *
 283 sdp_alloc_info_buffer(struct sdp_device *sdpvf __rte_unused,
 284         struct sdp_droq *droq)
 285 {
 286         droq->info_mz = rte_memzone_reserve_aligned("OQ_info_list",
 287                                 (droq->nb_desc * SDP_DROQ_INFO_SIZE),
 288                                 rte_socket_id(),
 289                                 RTE_MEMZONE_IOVA_CONTIG,
 290                                 RTE_CACHE_LINE_SIZE);
 291
 292         if (droq->info_mz == NULL)
 293                 return NULL;
 294
 295         droq->info_list_dma = droq->info_mz->iova;
 296         droq->info_alloc_size = droq->info_mz->len;
 297         droq->info_base_addr = (size_t)droq->info_mz->addr;
 298
 299         return droq->info_mz->addr;
 300 }
 301
 302 /* OQ initialization */
 303 static int
 304 sdp_init_droq(struct sdp_device *sdpvf, uint32_t q_no)
 305 {
 306         const struct sdp_config *conf = sdpvf->conf;
 307         uint32_t c_refill_threshold;
 308         uint32_t desc_ring_size;
 309         struct sdp_droq *droq;
 310
 311         otx2_info("OQ[%d] Init start", q_no);
 312
 313         droq = sdpvf->droq[q_no];
 314         droq->sdp_dev = sdpvf;
 315         droq->q_no = q_no;
 316
 317         c_refill_threshold = conf->oq.refill_threshold;
 318         droq->nb_desc      = conf->num_oqdef_descs;
 319         droq->buffer_size  = conf->oqdef_buf_size;
 320
 321         /* OQ desc_ring set up */
 322         desc_ring_size = droq->nb_desc * SDP_DROQ_DESC_SIZE;
 323         droq->desc_ring_mz = rte_memzone_reserve_aligned("sdp_oqmz",
 324                                                 desc_ring_size,
 325                                                 rte_socket_id(),
 326                                                 RTE_MEMZONE_IOVA_CONTIG,
 327                                                 RTE_CACHE_LINE_SIZE);
 328
 329         if (droq->desc_ring_mz == NULL) {
 330                 otx2_err("OQ:%d desc_ring allocation failed", q_no);
 331                 goto init_droq_fail;
 332         }
 333
 334         droq->desc_ring_dma = droq->desc_ring_mz->iova;
 335         droq->desc_ring = (struct sdp_droq_desc *)droq->desc_ring_mz->addr;
 336
 337         otx2_sdp_dbg("OQ[%d]: desc_ring: virt: 0x%p, dma: %lx",
 338                     q_no, droq->desc_ring, (unsigned long)droq->desc_ring_dma);
 339         otx2_sdp_dbg("OQ[%d]: num_desc: %d", q_no, droq->nb_desc);
 340
 341
 342         /* OQ info_list set up */
 343         droq->info_list = sdp_alloc_info_buffer(sdpvf, droq);
 344         if (droq->info_list == NULL) {
 345                 otx2_err("memory allocation failed for OQ[%d] info_list", q_no);
 346                 goto init_droq_fail;
 347         }
 348
 349         /* OQ buf_list set up */
 350         droq->recv_buf_list = rte_zmalloc_socket("recv_buf_list",
 351                                 (droq->nb_desc * SDP_DROQ_RECVBUF_SIZE),
 352                                  RTE_CACHE_LINE_SIZE, rte_socket_id());
 353         if (droq->recv_buf_list == NULL) {
 354                 otx2_err("OQ recv_buf_list alloc failed");
 355                 goto init_droq_fail;
 356         }
 357
 358         if (sdp_droq_setup_ring_buffers(sdpvf, droq))
 359                 goto init_droq_fail;
 360
 361         droq->refill_threshold = c_refill_threshold;
 362         rte_spinlock_init(&droq->lock);
 363
 364
 365         /* Set up OQ registers */
 366         sdpvf->fn_list.setup_oq_regs(sdpvf, q_no);
 367
 368         sdpvf->io_qmask.oq |= (1ull << q_no);
 369
 370         return 0;
 371
 372 init_droq_fail:
 373         return -ENOMEM;
 374 }
 375
 376 /* OQ configuration and setup */
 377 int
 378 sdp_setup_oqs(struct sdp_device *sdpvf, uint32_t oq_no)
 379 {
 380         struct sdp_droq *droq;
 381
 382         /* Allocate new droq. */
 383         droq = (struct sdp_droq *)rte_zmalloc("sdp_OQ",
 384                                 sizeof(*droq), RTE_CACHE_LINE_SIZE);
 385         if (droq == NULL) {
 386                 otx2_err("Droq[%d] Creation Failed", oq_no);
 387                 return -ENOMEM;
 388         }
 389         sdpvf->droq[oq_no] = droq;
 390
 391         if (sdp_init_droq(sdpvf, oq_no)) {
 392                 otx2_err("Droq[%d] Initialization failed", oq_no);
 393                 goto delete_OQ;
 394         }
 395         otx2_info("OQ[%d] is created.", oq_no);
 396
 397         sdpvf->num_oqs++;
 398
 399         return 0;
 400
 401 delete_OQ:
 402         sdp_delete_oqs(sdpvf, oq_no);
 403         return -ENOMEM;
 404 }
 405
 406 static inline void
 407 sdp_iqreq_delete(struct sdp_device *sdpvf,
 408                 struct sdp_instr_queue *iq, uint32_t idx)
 409 {
 410         uint32_t reqtype;
 411         void *buf;
 412
 413         buf     = iq->req_list[idx].buf;
 414         reqtype = iq->req_list[idx].reqtype;
 415
 416         switch (reqtype) {
 417         case SDP_REQTYPE_NORESP:
 418                 rte_mempool_put(sdpvf->enqdeq_mpool, buf);
 419                 otx2_sdp_dbg("IQ buffer freed at idx[%d]", idx);
 420                 break;
 421
 422         case SDP_REQTYPE_NORESP_GATHER:
 423         case SDP_REQTYPE_NONE:
 424         default:
 425                 otx2_info("This iqreq mode is not supported:%d", reqtype);
 426
 427         }
 428
 429         /* Reset the request list at this index */
 430         iq->req_list[idx].buf = NULL;
 431         iq->req_list[idx].reqtype = 0;
 432 }
 433
 434 static inline void
 435 sdp_iqreq_add(struct sdp_instr_queue *iq, void *buf,
 436                 uint32_t reqtype)
 437 {
 438         iq->req_list[iq->host_write_index].buf = buf;
 439         iq->req_list[iq->host_write_index].reqtype = reqtype;
 440
 441         otx2_sdp_dbg("IQ buffer added at idx[%d]", iq->host_write_index);
 442
 443 }
 444
 445 static void
 446 sdp_flush_iq(struct sdp_device *sdpvf,
 447                 struct sdp_instr_queue *iq,
 448                 uint32_t pending_thresh __rte_unused)
 449 {
 450         uint32_t instr_processed = 0;
 451
 452         rte_spinlock_lock(&iq->lock);
 453
 454         iq->otx_read_index = sdpvf->fn_list.update_iq_read_idx(iq);
 455         while (iq->flush_index != iq->otx_read_index) {
 456                 /* Free the IQ data buffer to the pool */
 457                 sdp_iqreq_delete(sdpvf, iq, iq->flush_index);
 458                 iq->flush_index =
 459                         sdp_incr_index(iq->flush_index, 1, iq->nb_desc);
 460
 461                 instr_processed++;
 462         }
 463
 464         iq->stats.instr_processed = instr_processed;
 465         rte_atomic64_sub(&iq->instr_pending, instr_processed);
 466
 467         rte_spinlock_unlock(&iq->lock);
 468 }
 469
 470 static inline void
 471 sdp_ring_doorbell(struct sdp_device *sdpvf __rte_unused,
 472                 struct sdp_instr_queue *iq)
 473 {
 474         otx2_write64(iq->fill_cnt, iq->doorbell_reg);
 475
 476         /* Make sure doorbell writes observed by HW */
 477         rte_cio_wmb();
 478         iq->fill_cnt = 0;
 479
 480 }
 481
 482 static inline int
 483 post_iqcmd(struct sdp_instr_queue *iq, uint8_t *iqcmd)
 484 {
 485         uint8_t *iqptr, cmdsize;
 486
 487         /* This ensures that the read index does not wrap around to
 488          * the same position if queue gets full before OCTEON TX2 could
 489          * fetch any instr.
 490          */
 491         if (rte_atomic64_read(&iq->instr_pending) >=
 492                               (int32_t)(iq->nb_desc - 1)) {
 493                 otx2_err("IQ is full, pending:%ld",
 494                          (long)rte_atomic64_read(&iq->instr_pending));
 495
 496                 return SDP_IQ_SEND_FAILED;
 497         }
 498
 499         /* Copy cmd into iq */
 500         cmdsize = ((iq->iqcmd_64B) ? 64 : 32);
 501         iqptr   = iq->base_addr + (cmdsize * iq->host_write_index);
 502
 503         rte_memcpy(iqptr, iqcmd, cmdsize);
 504
 505         otx2_sdp_dbg("IQ cmd posted @ index:%d", iq->host_write_index);
 506
 507         /* Increment the host write index */
 508         iq->host_write_index =
 509                 sdp_incr_index(iq->host_write_index, 1, iq->nb_desc);
 510
 511         iq->fill_cnt++;
 512
 513         /* Flush the command into memory. We need to be sure the data
 514          * is in memory before indicating that the instruction is
 515          * pending.
 516          */
 517         rte_smp_wmb();
 518         rte_atomic64_inc(&iq->instr_pending);
 519
 520         /* SDP_IQ_SEND_SUCCESS */
 521         return 0;
 522 }
 523
 524
 525 static int
 526 sdp_send_data(struct sdp_device *sdpvf,
 527               struct sdp_instr_queue *iq, void *cmd)
 528 {
 529         uint32_t ret;
 530
 531         /* Lock this IQ command queue before posting instruction */
 532         rte_spinlock_lock(&iq->post_lock);
 533
 534         /* Submit IQ command */
 535         ret = post_iqcmd(iq, cmd);
 536
 537         if (ret == SDP_IQ_SEND_SUCCESS) {
 538                 sdp_ring_doorbell(sdpvf, iq);
 539
 540                 iq->stats.instr_posted++;
 541                 otx2_sdp_dbg("Instr submit success posted: %ld\n",
 542                              (long)iq->stats.instr_posted);
 543
 544         } else {
 545                 iq->stats.instr_dropped++;
 546                 otx2_err("Instr submit failed, dropped: %ld\n",
 547                          (long)iq->stats.instr_dropped);
 548
 549         }
 550
 551         rte_spinlock_unlock(&iq->post_lock);
 552
 553         return ret;
 554 }
 555
 556
 557 /* Enqueue requests/packets to SDP IQ queue.
 558  * returns number of requests enqueued successfully
 559  */
 560 int
 561 sdp_rawdev_enqueue(struct rte_rawdev *rawdev,
 562                    struct rte_rawdev_buf **buffers __rte_unused,
 563                    unsigned int count, rte_rawdev_obj_t context)
 564 {
 565         struct sdp_instr_64B *iqcmd;
 566         struct sdp_instr_queue *iq;
 567         struct sdp_soft_instr *si;
 568         struct sdp_device *sdpvf;
 569
 570         struct sdp_instr_ih ihx;
 571
 572         sdpvf = (struct sdp_device *)rawdev->dev_private;
 573         si = (struct sdp_soft_instr *)context;
 574
 575         iq = sdpvf->instr_queue[si->q_no];
 576
 577         if ((count > 1) || (count < 1)) {
 578                 otx2_err("This mode not supported: req[%d]", count);
 579                 goto enq_fail;
 580         }
 581
 582         memset(&ihx, 0, sizeof(struct sdp_instr_ih));
 583
 584         iqcmd = &si->command;
 585         memset(iqcmd, 0, sizeof(struct sdp_instr_64B));
 586
 587         iqcmd->dptr = (uint64_t)si->dptr;
 588
 589         /* Populate SDP IH */
 590         ihx.pkind  = sdpvf->pkind;
 591         ihx.fsz    = si->ih.fsz + 8; /* 8B for NIX IH */
 592         ihx.gather = si->ih.gather;
 593
 594         /* Direct data instruction */
 595         ihx.tlen   = si->ih.tlen + ihx.fsz;
 596
 597         switch (ihx.gather) {
 598         case 0: /* Direct data instr */
 599                 ihx.tlen = si->ih.tlen + ihx.fsz;
 600                 break;
 601
 602         default: /* Gather */
 603                 switch (si->ih.gsz) {
 604                 case 0: /* Direct gather instr */
 605                         otx2_err("Direct Gather instr : not supported");
 606                         goto enq_fail;
 607
 608                 default: /* Indirect gather instr */
 609                         otx2_err("Indirect Gather instr : not supported");
 610                         goto enq_fail;
 611                 }
 612         }
 613
 614         rte_memcpy(&iqcmd->ih, &ihx, sizeof(uint64_t));
 615         iqcmd->rptr = (uint64_t)si->rptr;
 616         rte_memcpy(&iqcmd->irh, &si->irh, sizeof(uint64_t));
 617
 618         /* Swap FSZ(front data) here, to avoid swapping on OCTEON TX2 side */
 619         sdp_swap_8B_data(&iqcmd->rptr, 1);
 620         sdp_swap_8B_data(&iqcmd->irh, 1);
 621
 622         otx2_sdp_dbg("After swapping");
 623         otx2_sdp_dbg("Word0 [dptr]: 0x%016lx", (unsigned long)iqcmd->dptr);
 624         otx2_sdp_dbg("Word1 [ihtx]: 0x%016lx", (unsigned long)iqcmd->ih);
 625         otx2_sdp_dbg("Word2 [rptr]: 0x%016lx", (unsigned long)iqcmd->rptr);
 626         otx2_sdp_dbg("Word3 [irh]: 0x%016lx", (unsigned long)iqcmd->irh);
 627         otx2_sdp_dbg("Word4 [exhdr[0]]: 0x%016lx",
 628                         (unsigned long)iqcmd->exhdr[0]);
 629
 630         sdp_iqreq_add(iq, si->dptr, si->reqtype);
 631
 632         if (sdp_send_data(sdpvf, iq, iqcmd)) {
 633                 otx2_err("Data send failed :");
 634                 sdp_iqreq_delete(sdpvf, iq, iq->host_write_index);
 635                 goto enq_fail;
 636         }
 637
 638         if (rte_atomic64_read(&iq->instr_pending) >= 1)
 639                 sdp_flush_iq(sdpvf, iq, 1 /*(iq->nb_desc / 2)*/);
 640
 641         /* Return no# of instructions posted successfully. */
 642         return count;
 643
 644 enq_fail:
 645         return SDP_IQ_SEND_FAILED;
 646 }
 647