1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef _OTX2_EP_RAWDEV_H_
6 #define _OTX2_EP_RAWDEV_H_
8 #include <rte_byteorder.h>
9 #include <rte_spinlock.h>
12 /* Input Request Header format */
13 struct sdp_instr_irh {
17 /* PCIe port to use for response */
20 /* Scatter indicator 1=scatter */
23 /* Size of Expected result OR no. of entries in scatter list */
26 /* Desired destination port for result */
29 /* Opcode Specific parameters */
32 /* Opcode for the return packet */
36 /* SDP 32B instruction format */
37 struct sdp_instr_32B {
38 /* Pointer where the input data is available. */
41 /* SDP Instruction Header. */
44 /** Pointer where the response for a RAW mode packet
45 * will be written by OCTEON TX2.
49 /* Input Request Header. Additional info about the input. */
52 #define SDP_32B_INSTR_SIZE (sizeof(sdp_instr_32B))
54 /* SDP 64B instruction format */
55 struct sdp_instr_64B {
56 /* Pointer where the input data is available. */
59 /* SDP Instruction Header. */
62 /** Pointer where the response for a RAW mode packet
63 * will be written by OCTEON TX2.
67 /* Input Request Header. */
70 /* Additional headers available in a 64-byte instruction. */
73 #define SDP_64B_INSTR_SIZE (sizeof(sdp_instr_64B))
75 struct sdp_soft_instr {
76 /** Input data pointer. It is either pointing directly to input data
77 * or to a gather list.
81 /** Response from OCTEON TX2 comes at this address. It is either
82 * directlty pointing to output data buffer or to a scatter list.
86 /* The instruction header. All input commands have this field. */
87 struct sdp_instr_ih ih;
89 /* Input request header. */
90 struct sdp_instr_irh irh;
92 /** The PCI instruction to be sent to OCTEON TX2. This is stored in the
93 * instr to retrieve the physical address of buffers when instr is
96 struct sdp_instr_64B command;
98 /** If a gather list was allocated, this ptr points to the buffer used
99 * for the gather list. The gather list has to be 8B aligned, so this
100 * value may be different from dptr.
104 /* Total data bytes transferred in the gather mode request. */
105 uint64_t gather_bytes;
107 /** If a scatter list was allocated, this ptr points to the buffer used
108 * for the scatter list. The scatter list has to be 8B aligned, so
109 * this value may be different from rptr.
113 /* Total data bytes to be received in the scatter mode request. */
114 uint64_t scatter_bytes;
116 /* IQ number to which this instruction has to be submitted. */
119 /* IQ instruction request type. */
122 #define SDP_SOFT_INSTR_SIZE (sizeof(sdp_soft_instr))
124 /* SDP IQ request list */
125 struct sdp_instr_list {
129 #define SDP_IQREQ_LIST_SIZE (sizeof(struct sdp_instr_list))
131 /* Structure to define the configuration attributes for each Input queue. */
132 struct sdp_iq_config {
133 /* Max number of IQs available */
136 /* Command size - 32 or 64 bytes */
139 /* Pending list size, usually set to the sum of the size of all IQs */
140 uint32_t pending_list_size;
143 /** The instruction (input) queue.
144 * The input queue is used to post raw (instruction) mode data or packet data
145 * to OCTEON TX2 device from the host. Each IQ of a SDP EP VF device has one
146 * such structure to represent it.
148 struct sdp_instr_queue {
149 /* A spinlock to protect access to the input ring. */
151 rte_spinlock_t post_lock;
153 struct sdp_device *sdp_dev;
154 rte_atomic64_t iq_flush_running;
157 uint32_t pkt_in_done;
159 /* Flag for 64 byte commands. */
160 uint32_t iqcmd_64B:1;
164 /* Number of descriptors in this ring. */
167 /* Input ring index, where the driver should write the next packet */
168 uint32_t host_write_index;
170 /* Input ring index, where the OCTEON TX2 should read the next packet */
171 uint32_t otx_read_index;
173 /** This index aids in finding the window in the queue where OCTEON TX2
174 * has read the commands.
176 uint32_t flush_index;
178 /* This keeps track of the instructions pending in this queue. */
179 rte_atomic64_t instr_pending;
181 uint32_t reset_instr_cnt;
183 /* Pointer to the Virtual Base addr of the input ring. */
186 /* This IQ request list */
187 struct sdp_instr_list *req_list;
189 /* SDP doorbell register for the ring. */
192 /* SDP instruction count register for this ring. */
195 /* Number of instructions pending to be posted to OCTEON TX2. */
198 /* DMA mapped base address of the input descriptor ring. */
199 uint64_t base_addr_dma;
202 const struct rte_memzone *iq_mz;
205 /* DROQ packet format for application i/f. */
206 struct sdp_droq_pkt {
207 /* DROQ packet data buffer pointer. */
210 /* DROQ packet data length */
216 /** Descriptor format.
217 * The descriptor ring is made of descriptors which have 2 64-bit values:
218 * -# Physical (bus) address of the data buffer.
219 * -# Physical (bus) address of a sdp_droq_info structure.
220 * The device DMA's incoming packets and its information at the address
221 * given by these descriptor fields.
223 struct sdp_droq_desc {
224 /* The buffer pointer */
227 /* The Info pointer */
230 #define SDP_DROQ_DESC_SIZE (sizeof(struct sdp_droq_desc))
236 #define SDP_RH_SIZE (sizeof(union sdp_rh))
238 /** Information about packet DMA'ed by OCTEON TX2.
239 * The format of the information available at Info Pointer after OCTEON TX2
240 * has posted a packet. Not all descriptors have valid information. Only
241 * the Info field of the first descriptor for a packet has information
244 struct sdp_droq_info {
245 /* The Output Receive Header. */
248 /* The Length of the packet. */
251 #define SDP_DROQ_INFO_SIZE (sizeof(struct sdp_droq_info))
253 /** Pointer to data buffer.
254 * Driver keeps a pointer to the data buffer that it made available to
255 * the OCTEON TX2 device. Since the descriptor ring keeps physical (bus)
256 * addresses, this field is required for the driver to keep track of
257 * the virtual address pointers.
259 struct sdp_recv_buffer {
260 /* Packet buffer, including meta data. */
263 /* Data in the packet buffer. */
266 #define SDP_DROQ_RECVBUF_SIZE (sizeof(struct sdp_recv_buffer))
268 /* Structure to define the configuration attributes for each Output queue. */
269 struct sdp_oq_config {
270 /* Max number of OQs available */
273 /* If set, the Output queue uses info-pointer mode. (Default: 1 ) */
276 /** The number of buffers that were consumed during packet processing by
277 * the driver on this Output queue before the driver attempts to
278 * replenish the descriptor ring with new buffers.
280 uint32_t refill_threshold;
283 /* The Descriptor Ring Output Queue(DROQ) structure. */
285 /* A spinlock to protect access to this ring. */
288 struct sdp_device *sdp_dev;
289 /* The 8B aligned descriptor ring starts at this address. */
290 struct sdp_droq_desc *desc_ring;
293 uint32_t last_pkt_count;
295 /* Driver should read the next packet at this index */
298 /* OCTEON TX2 will write the next packet at this index */
301 /* At this index, the driver will refill the descriptor's buffer */
304 /* Packets pending to be processed */
305 rte_atomic64_t pkts_pending;
307 /* Number of descriptors in this ring. */
310 /* The number of descriptors pending to refill. */
311 uint32_t refill_count;
313 uint32_t refill_threshold;
315 /* The 8B aligned info ptrs begin from this address. */
316 struct sdp_droq_info *info_list;
318 /* receive buffer list contains virtual addresses of the buffers. */
319 struct sdp_recv_buffer *recv_buf_list;
321 /* The size of each buffer pointed by the buffer pointer. */
322 uint32_t buffer_size;
324 /** Pointer to the mapped packet credit register.
325 * Host writes number of info/buffer ptrs available to this register
327 void *pkts_credit_reg;
329 /** Pointer to the mapped packet sent register. OCTEON TX2 writes the
330 * number of packets DMA'ed to host memory in this register.
334 /* DMA mapped address of the DROQ descriptor ring. */
335 size_t desc_ring_dma;
337 /* Info_ptr list is allocated at this virtual address. */
338 size_t info_base_addr;
340 /* DMA mapped address of the info list */
341 size_t info_list_dma;
343 /* Allocated size of info list. */
344 uint32_t info_alloc_size;
347 const struct rte_memzone *desc_ring_mz;
348 const struct rte_memzone *info_mz;
350 #define SDP_DROQ_SIZE (sizeof(struct sdp_droq))
353 struct sdp_io_enable {
359 /* Structure to define the configuration. */
361 /* Input Queue attributes. */
362 struct sdp_iq_config iq;
364 /* Output Queue attributes. */
365 struct sdp_oq_config oq;
367 /* Num of desc for IQ rings */
368 uint32_t num_iqdef_descs;
370 /* Num of desc for OQ rings */
371 uint32_t num_oqdef_descs;
374 uint32_t oqdef_buf_size;
377 /* Required functions for each VF device */
379 void (*setup_iq_regs)(struct sdp_device *sdpvf, uint32_t q_no);
380 void (*setup_oq_regs)(struct sdp_device *sdpvf, uint32_t q_no);
381 int (*setup_device_regs)(struct sdp_device *sdpvf);
382 void (*enable_io_queues)(struct sdp_device *sdpvf);
383 void (*enable_iq)(struct sdp_device *sdpvf, uint32_t q_no);
384 void (*enable_oq)(struct sdp_device *sdpvf, uint32_t q_no);
387 /* SRIOV information */
388 struct sdp_sriov_info {
389 /* Number of rings assigned to VF */
390 uint32_t rings_per_vf;
392 /* Number of VF devices enabled */
397 /* Information to be passed from application */
398 struct sdp_rawdev_info {
399 struct rte_mempool *enqdeq_mpool;
400 const struct sdp_config *app_conf;
403 /* SDP EP VF device */
405 /* PCI device pointer */
406 struct rte_pci_device *pci_dev;
411 /* This device's PCIe port used for traffic. */
415 /* The state of this device */
416 rte_atomic64_t status;
418 /* Memory mapped h/w address */
421 struct sdp_fn_list fn_list;
426 /* The input instruction queues */
427 struct sdp_instr_queue *instr_queue[SDP_VF_MAX_IOQS_PER_RAWDEV];
432 /* The DROQ output queues */
433 struct sdp_droq *droq[SDP_VF_MAX_IOQS_PER_RAWDEV];
435 /* IOQ data buffer pool */
436 struct rte_mempool *enqdeq_mpool;
439 struct sdp_io_enable io_qmask;
442 struct sdp_sriov_info sriov_info;
444 /* Device configuration */
445 const struct sdp_config *conf;
448 const struct sdp_config *sdp_get_defconf(struct sdp_device *sdp_dev);
449 int sdp_setup_iqs(struct sdp_device *sdpvf, uint32_t iq_no);
451 int sdp_setup_oqs(struct sdp_device *sdpvf, uint32_t oq_no);
453 #endif /* _OTX2_EP_RAWDEV_H_ */