1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef _OTX2_EP_RAWDEV_H_
6 #define _OTX2_EP_RAWDEV_H_
8 #include <rte_byteorder.h>
9 #include <rte_spinlock.h>
11 /* IQ instruction req types */
12 #define SDP_REQTYPE_NONE (0)
13 #define SDP_REQTYPE_NORESP (1)
14 #define SDP_REQTYPE_NORESP_GATHER (2)
16 /* Input Request Header format */
17 struct sdp_instr_irh {
21 /* PCIe port to use for response */
24 /* Scatter indicator 1=scatter */
27 /* Size of Expected result OR no. of entries in scatter list */
30 /* Desired destination port for result */
33 /* Opcode Specific parameters */
36 /* Opcode for the return packet */
40 /* SDP 32B instruction format */
41 struct sdp_instr_32B {
42 /* Pointer where the input data is available. */
45 /* SDP Instruction Header. */
48 /** Pointer where the response for a RAW mode packet
49 * will be written by OCTEON TX2.
53 /* Input Request Header. Additional info about the input. */
56 #define SDP_32B_INSTR_SIZE (sizeof(sdp_instr_32B))
58 /* SDP 64B instruction format */
59 struct sdp_instr_64B {
60 /* Pointer where the input data is available. */
63 /* SDP Instruction Header. */
66 /** Pointer where the response for a RAW mode packet
67 * will be written by OCTEON TX2.
71 /* Input Request Header. */
74 /* Additional headers available in a 64-byte instruction. */
77 #define SDP_64B_INSTR_SIZE (sizeof(sdp_instr_64B))
79 struct sdp_soft_instr {
80 /** Input data pointer. It is either pointing directly to input data
81 * or to a gather list.
85 /** Response from OCTEON TX2 comes at this address. It is either
86 * directlty pointing to output data buffer or to a scatter list.
90 /* The instruction header. All input commands have this field. */
91 struct sdp_instr_ih ih;
93 /* Input request header. */
94 struct sdp_instr_irh irh;
96 /** The PCI instruction to be sent to OCTEON TX2. This is stored in the
97 * instr to retrieve the physical address of buffers when instr is
100 struct sdp_instr_64B command;
102 /** If a gather list was allocated, this ptr points to the buffer used
103 * for the gather list. The gather list has to be 8B aligned, so this
104 * value may be different from dptr.
108 /* Total data bytes transferred in the gather mode request. */
109 uint64_t gather_bytes;
111 /** If a scatter list was allocated, this ptr points to the buffer used
112 * for the scatter list. The scatter list has to be 8B aligned, so
113 * this value may be different from rptr.
117 /* Total data bytes to be received in the scatter mode request. */
118 uint64_t scatter_bytes;
120 /* IQ number to which this instruction has to be submitted. */
123 /* IQ instruction request type. */
126 #define SDP_SOFT_INSTR_SIZE (sizeof(sdp_soft_instr))
128 /* SDP IQ request list */
129 struct sdp_instr_list {
133 #define SDP_IQREQ_LIST_SIZE (sizeof(struct sdp_instr_list))
135 /* Input Queue statistics. Each input queue has four stats fields. */
136 struct sdp_iq_stats {
137 uint64_t instr_posted; /* Instructions posted to this queue. */
138 uint64_t instr_processed; /* Instructions processed in this queue. */
139 uint64_t instr_dropped; /* Instructions that could not be processed */
142 /* Structure to define the configuration attributes for each Input queue. */
143 struct sdp_iq_config {
144 /* Max number of IQs available */
147 /* Command size - 32 or 64 bytes */
150 /* Pending list size, usually set to the sum of the size of all IQs */
151 uint32_t pending_list_size;
154 /** The instruction (input) queue.
155 * The input queue is used to post raw (instruction) mode data or packet data
156 * to OCTEON TX2 device from the host. Each IQ of a SDP EP VF device has one
157 * such structure to represent it.
159 struct sdp_instr_queue {
160 /* A spinlock to protect access to the input ring. */
162 rte_spinlock_t post_lock;
164 struct sdp_device *sdp_dev;
165 rte_atomic64_t iq_flush_running;
168 uint32_t pkt_in_done;
170 /* Flag for 64 byte commands. */
171 uint32_t iqcmd_64B:1;
175 /* Number of descriptors in this ring. */
178 /* Input ring index, where the driver should write the next packet */
179 uint32_t host_write_index;
181 /* Input ring index, where the OCTEON TX2 should read the next packet */
182 uint32_t otx_read_index;
184 /** This index aids in finding the window in the queue where OCTEON TX2
185 * has read the commands.
187 uint32_t flush_index;
189 /* This keeps track of the instructions pending in this queue. */
190 rte_atomic64_t instr_pending;
192 uint32_t reset_instr_cnt;
194 /* Pointer to the Virtual Base addr of the input ring. */
197 /* This IQ request list */
198 struct sdp_instr_list *req_list;
200 /* SDP doorbell register for the ring. */
203 /* SDP instruction count register for this ring. */
206 /* Number of instructions pending to be posted to OCTEON TX2. */
209 /* Statistics for this input queue. */
210 struct sdp_iq_stats stats;
212 /* DMA mapped base address of the input descriptor ring. */
213 uint64_t base_addr_dma;
216 const struct rte_memzone *iq_mz;
219 /* DROQ packet format for application i/f. */
220 struct sdp_droq_pkt {
221 /* DROQ packet data buffer pointer. */
224 /* DROQ packet data length */
230 /** Descriptor format.
231 * The descriptor ring is made of descriptors which have 2 64-bit values:
232 * -# Physical (bus) address of the data buffer.
233 * -# Physical (bus) address of a sdp_droq_info structure.
234 * The device DMA's incoming packets and its information at the address
235 * given by these descriptor fields.
237 struct sdp_droq_desc {
238 /* The buffer pointer */
241 /* The Info pointer */
244 #define SDP_DROQ_DESC_SIZE (sizeof(struct sdp_droq_desc))
250 #define SDP_RH_SIZE (sizeof(union sdp_rh))
252 /** Information about packet DMA'ed by OCTEON TX2.
253 * The format of the information available at Info Pointer after OCTEON TX2
254 * has posted a packet. Not all descriptors have valid information. Only
255 * the Info field of the first descriptor for a packet has information
258 struct sdp_droq_info {
259 /* The Output Receive Header. */
262 /* The Length of the packet. */
265 #define SDP_DROQ_INFO_SIZE (sizeof(struct sdp_droq_info))
267 /** Pointer to data buffer.
268 * Driver keeps a pointer to the data buffer that it made available to
269 * the OCTEON TX2 device. Since the descriptor ring keeps physical (bus)
270 * addresses, this field is required for the driver to keep track of
271 * the virtual address pointers.
273 struct sdp_recv_buffer {
274 /* Packet buffer, including meta data. */
277 /* Data in the packet buffer. */
280 #define SDP_DROQ_RECVBUF_SIZE (sizeof(struct sdp_recv_buffer))
282 /* Structure to define the configuration attributes for each Output queue. */
283 struct sdp_oq_config {
284 /* Max number of OQs available */
287 /* If set, the Output queue uses info-pointer mode. (Default: 1 ) */
290 /** The number of buffers that were consumed during packet processing by
291 * the driver on this Output queue before the driver attempts to
292 * replenish the descriptor ring with new buffers.
294 uint32_t refill_threshold;
297 /* The Descriptor Ring Output Queue(DROQ) structure. */
299 /* A spinlock to protect access to this ring. */
302 struct sdp_device *sdp_dev;
303 /* The 8B aligned descriptor ring starts at this address. */
304 struct sdp_droq_desc *desc_ring;
307 uint32_t last_pkt_count;
309 /* Driver should read the next packet at this index */
312 /* OCTEON TX2 will write the next packet at this index */
315 /* At this index, the driver will refill the descriptor's buffer */
318 /* Packets pending to be processed */
319 rte_atomic64_t pkts_pending;
321 /* Number of descriptors in this ring. */
324 /* The number of descriptors pending to refill. */
325 uint32_t refill_count;
327 uint32_t refill_threshold;
329 /* The 8B aligned info ptrs begin from this address. */
330 struct sdp_droq_info *info_list;
332 /* receive buffer list contains virtual addresses of the buffers. */
333 struct sdp_recv_buffer *recv_buf_list;
335 /* The size of each buffer pointed by the buffer pointer. */
336 uint32_t buffer_size;
338 /** Pointer to the mapped packet credit register.
339 * Host writes number of info/buffer ptrs available to this register
341 void *pkts_credit_reg;
343 /** Pointer to the mapped packet sent register. OCTEON TX2 writes the
344 * number of packets DMA'ed to host memory in this register.
348 /* DMA mapped address of the DROQ descriptor ring. */
349 size_t desc_ring_dma;
351 /* Info_ptr list is allocated at this virtual address. */
352 size_t info_base_addr;
354 /* DMA mapped address of the info list */
355 size_t info_list_dma;
357 /* Allocated size of info list. */
358 uint32_t info_alloc_size;
361 const struct rte_memzone *desc_ring_mz;
362 const struct rte_memzone *info_mz;
364 #define SDP_DROQ_SIZE (sizeof(struct sdp_droq))
367 struct sdp_io_enable {
373 /* Structure to define the configuration. */
375 /* Input Queue attributes. */
376 struct sdp_iq_config iq;
378 /* Output Queue attributes. */
379 struct sdp_oq_config oq;
381 /* Num of desc for IQ rings */
382 uint32_t num_iqdef_descs;
384 /* Num of desc for OQ rings */
385 uint32_t num_oqdef_descs;
388 uint32_t oqdef_buf_size;
391 /* Required functions for each VF device */
393 void (*setup_iq_regs)(struct sdp_device *sdpvf, uint32_t q_no);
394 void (*setup_oq_regs)(struct sdp_device *sdpvf, uint32_t q_no);
396 int (*setup_device_regs)(struct sdp_device *sdpvf);
397 uint32_t (*update_iq_read_idx)(struct sdp_instr_queue *iq);
399 void (*enable_io_queues)(struct sdp_device *sdpvf);
400 void (*disable_io_queues)(struct sdp_device *sdpvf);
402 void (*enable_iq)(struct sdp_device *sdpvf, uint32_t q_no);
403 void (*disable_iq)(struct sdp_device *sdpvf, uint32_t q_no);
405 void (*enable_oq)(struct sdp_device *sdpvf, uint32_t q_no);
406 void (*disable_oq)(struct sdp_device *sdpvf, uint32_t q_no);
409 /* SRIOV information */
410 struct sdp_sriov_info {
411 /* Number of rings assigned to VF */
412 uint32_t rings_per_vf;
414 /* Number of VF devices enabled */
419 /* Information to be passed from application */
420 struct sdp_rawdev_info {
421 struct rte_mempool *enqdeq_mpool;
422 const struct sdp_config *app_conf;
425 /* SDP EP VF device */
427 /* PCI device pointer */
428 struct rte_pci_device *pci_dev;
433 /* This device's PCIe port used for traffic. */
437 /* The state of this device */
438 rte_atomic64_t status;
440 /* Memory mapped h/w address */
443 struct sdp_fn_list fn_list;
448 /* The input instruction queues */
449 struct sdp_instr_queue *instr_queue[SDP_VF_MAX_IOQS_PER_RAWDEV];
454 /* The DROQ output queues */
455 struct sdp_droq *droq[SDP_VF_MAX_IOQS_PER_RAWDEV];
457 /* IOQ data buffer pool */
458 struct rte_mempool *enqdeq_mpool;
461 struct sdp_io_enable io_qmask;
464 struct sdp_sriov_info sriov_info;
466 /* Device configuration */
467 const struct sdp_config *conf;
470 const struct sdp_config *sdp_get_defconf(struct sdp_device *sdp_dev);
471 int sdp_setup_iqs(struct sdp_device *sdpvf, uint32_t iq_no);
472 int sdp_delete_iqs(struct sdp_device *sdpvf, uint32_t iq_no);
474 int sdp_setup_oqs(struct sdp_device *sdpvf, uint32_t oq_no);
475 int sdp_delete_oqs(struct sdp_device *sdpvf, uint32_t oq_no);
477 int sdp_rawdev_enqueue(struct rte_rawdev *dev, struct rte_rawdev_buf **buffers,
478 unsigned int count, rte_rawdev_obj_t context);
481 #endif /* _OTX2_EP_RAWDEV_H_ */