drivers/regex/mlx5/mlx5_regex.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2020 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <rte_malloc.h>
   6 #include <rte_log.h>
   7 #include <rte_errno.h>
   8 #include <rte_pci.h>
   9 #include <rte_regexdev.h>
  10 #include <rte_regexdev_core.h>
  11 #include <rte_regexdev_driver.h>
  12 #include <rte_bus_pci.h>
  13
  14 #include <mlx5_common.h>
  15 #include <mlx5_common_mr.h>
  16 #include <mlx5_glue.h>
  17 #include <mlx5_devx_cmds.h>
  18 #include <mlx5_prm.h>
  19
  20 #include "mlx5_regex.h"
  21 #include "mlx5_regex_utils.h"
  22
  23 #define MLX5_REGEX_DRIVER_NAME regex_mlx5
  24
  25 int mlx5_regex_logtype;
  26
  27 const struct rte_regexdev_ops mlx5_regexdev_ops = {
  28         .dev_info_get = mlx5_regex_info_get,
  29         .dev_configure = mlx5_regex_configure,
  30         .dev_db_import = mlx5_regex_rules_db_import,
  31         .dev_qp_setup = mlx5_regex_qp_setup,
  32         .dev_start = mlx5_regex_start,
  33         .dev_stop = mlx5_regex_stop,
  34         .dev_close = mlx5_regex_close,
  35 };
  36
  37 int
  38 mlx5_regex_start(struct rte_regexdev *dev)
  39 {
  40         struct mlx5_regex_priv *priv = dev->data->dev_private;
  41
  42         return mlx5_dev_mempool_subscribe(priv->cdev);
  43 }
  44
  45 int
  46 mlx5_regex_stop(struct rte_regexdev *dev __rte_unused)
  47 {
  48         struct mlx5_regex_priv *priv = dev->data->dev_private;
  49
  50         mlx5_regex_clean_ctrl(dev);
  51         rte_free(priv->qps);
  52         priv->qps = NULL;
  53
  54         return 0;
  55 }
  56
  57 int
  58 mlx5_regex_close(struct rte_regexdev *dev __rte_unused)
  59 {
  60         return 0;
  61 }
  62
  63 static void
  64 mlx5_regex_get_name(char *name, struct rte_device *dev)
  65 {
  66         sprintf(name, "mlx5_regex_%s", dev->name);
  67 }
  68
  69 static int
  70 mlx5_regex_dev_probe(struct mlx5_common_device *cdev)
  71 {
  72         struct mlx5_regex_priv *priv = NULL;
  73         struct mlx5_hca_attr *attr = &cdev->config.hca_attr;
  74         char name[RTE_REGEXDEV_NAME_MAX_LEN];
  75
  76         if ((!attr->regexp_params && !attr->mmo_regex_sq_en && !attr->mmo_regex_qp_en)
  77             || attr->regexp_num_of_engines == 0) {
  78                 DRV_LOG(ERR, "Not enough capabilities to support RegEx, maybe "
  79                         "old FW/OFED version?");
  80                 rte_errno = ENOTSUP;
  81                 return -rte_errno;
  82         }
  83         priv = rte_zmalloc("mlx5 regex device private", sizeof(*priv),
  84                            RTE_CACHE_LINE_SIZE);
  85         if (!priv) {
  86                 DRV_LOG(ERR, "Failed to allocate private memory.");
  87                 rte_errno = ENOMEM;
  88                 return -rte_errno;
  89         }
  90         priv->mmo_regex_qp_cap = attr->mmo_regex_qp_en;
  91         priv->mmo_regex_sq_cap = attr->mmo_regex_sq_en;
  92         priv->cdev = cdev;
  93         priv->nb_engines = 2; /* attr.regexp_num_of_engines */
  94         if (attr->regexp_version == MLX5_RXP_BF2_IDENTIFIER)
  95                 priv->is_bf2 = 1;
  96         /* Default RXP programming mode to Shared. */
  97         priv->prog_mode = MLX5_RXP_SHARED_PROG_MODE;
  98         mlx5_regex_get_name(name, cdev->dev);
  99         priv->regexdev = rte_regexdev_register(name);
 100         if (priv->regexdev == NULL) {
 101                 DRV_LOG(ERR, "Failed to register RegEx device.");
 102                 rte_errno = rte_errno ? rte_errno : EINVAL;
 103                 goto dev_error;
 104         }
 105         /*
 106          * This PMD always claims the write memory barrier on UAR
 107          * registers writings, it is safe to allocate UAR with any
 108          * memory mapping type.
 109          */
 110         priv->uar = mlx5_devx_alloc_uar(priv->cdev->ctx, -1);
 111         if (!priv->uar) {
 112                 DRV_LOG(ERR, "can't allocate uar.");
 113                 rte_errno = ENOMEM;
 114                 goto error;
 115         }
 116         priv->regexdev->dev_ops = &mlx5_regexdev_ops;
 117         priv->regexdev->enqueue = mlx5_regexdev_enqueue;
 118 #ifdef HAVE_MLX5_UMR_IMKEY
 119         if (!attr->umr_indirect_mkey_disabled &&
 120             !attr->umr_modify_entity_size_disabled)
 121                 priv->has_umr = 1;
 122         if (priv->has_umr)
 123                 priv->regexdev->enqueue = mlx5_regexdev_enqueue_gga;
 124 #endif
 125         priv->regexdev->dequeue = mlx5_regexdev_dequeue;
 126         priv->regexdev->device = cdev->dev;
 127         priv->regexdev->data->dev_private = priv;
 128         priv->regexdev->state = RTE_REGEXDEV_READY;
 129         DRV_LOG(INFO, "RegEx GGA is %s.",
 130                 priv->has_umr ? "supported" : "unsupported");
 131         return 0;
 132
 133 error:
 134         if (priv->uar)
 135                 mlx5_glue->devx_free_uar(priv->uar);
 136         if (priv->regexdev)
 137                 rte_regexdev_unregister(priv->regexdev);
 138 dev_error:
 139         if (priv)
 140                 rte_free(priv);
 141         return -rte_errno;
 142 }
 143
 144 static int
 145 mlx5_regex_dev_remove(struct mlx5_common_device *cdev)
 146 {
 147         char name[RTE_REGEXDEV_NAME_MAX_LEN];
 148         struct rte_regexdev *dev;
 149         struct mlx5_regex_priv *priv = NULL;
 150
 151         mlx5_regex_get_name(name, cdev->dev);
 152         dev = rte_regexdev_get_device_by_name(name);
 153         if (!dev)
 154                 return 0;
 155         priv = dev->data->dev_private;
 156         if (priv) {
 157                 if (priv->uar)
 158                         mlx5_glue->devx_free_uar(priv->uar);
 159                 if (priv->regexdev)
 160                         rte_regexdev_unregister(priv->regexdev);
 161                 rte_free(priv);
 162         }
 163         return 0;
 164 }
 165
 166 static const struct rte_pci_id mlx5_regex_pci_id_map[] = {
 167         {
 168                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
 169                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
 170         },
 171         {
 172                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
 173                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
 174         },
 175         {
 176                 .vendor_id = 0
 177         }
 178 };
 179
 180 static struct mlx5_class_driver mlx5_regex_driver = {
 181         .drv_class = MLX5_CLASS_REGEX,
 182         .name = RTE_STR(MLX5_REGEX_DRIVER_NAME),
 183         .id_table = mlx5_regex_pci_id_map,
 184         .probe = mlx5_regex_dev_probe,
 185         .remove = mlx5_regex_dev_remove,
 186 };
 187
 188 RTE_INIT(rte_mlx5_regex_init)
 189 {
 190         mlx5_common_init();
 191         if (mlx5_glue)
 192                 mlx5_class_driver_register(&mlx5_regex_driver);
 193 }
 194
 195 RTE_LOG_REGISTER_DEFAULT(mlx5_regex_logtype, NOTICE)
 196 RTE_PMD_EXPORT_NAME(MLX5_REGEX_DRIVER_NAME, __COUNTER__);
 197 RTE_PMD_REGISTER_PCI_TABLE(MLX5_REGEX_DRIVER_NAME, mlx5_regex_pci_id_map);
 198 RTE_PMD_REGISTER_KMOD_DEP(MLX5_REGEX_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");