1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
5 #include <rte_malloc.h>
9 #include <rte_regexdev.h>
10 #include <rte_regexdev_core.h>
11 #include <rte_regexdev_driver.h>
12 #include <rte_bus_pci.h>
14 #include <mlx5_common.h>
15 #include <mlx5_common_mr.h>
16 #include <mlx5_glue.h>
17 #include <mlx5_devx_cmds.h>
20 #include "mlx5_regex.h"
21 #include "mlx5_regex_utils.h"
22 #include "mlx5_rxp_csrs.h"
24 #define MLX5_REGEX_DRIVER_NAME regex_mlx5
26 int mlx5_regex_logtype;
28 const struct rte_regexdev_ops mlx5_regexdev_ops = {
29 .dev_info_get = mlx5_regex_info_get,
30 .dev_configure = mlx5_regex_configure,
31 .dev_db_import = mlx5_regex_rules_db_import,
32 .dev_qp_setup = mlx5_regex_qp_setup,
33 .dev_start = mlx5_regex_start,
34 .dev_stop = mlx5_regex_stop,
35 .dev_close = mlx5_regex_close,
39 mlx5_regex_start(struct rte_regexdev *dev)
41 struct mlx5_regex_priv *priv = dev->data->dev_private;
43 return mlx5_dev_mempool_subscribe(priv->cdev);
47 mlx5_regex_stop(struct rte_regexdev *dev __rte_unused)
49 struct mlx5_regex_priv *priv = dev->data->dev_private;
52 mlx5_regex_clean_ctrl(dev);
56 for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT); i++) {
57 if (priv->db[i].umem.umem)
58 mlx5_glue->devx_umem_dereg(priv->db[i].umem.umem);
59 rte_free(priv->db[i].ptr);
60 priv->db[i].ptr = NULL;
67 mlx5_regex_close(struct rte_regexdev *dev __rte_unused)
73 mlx5_regex_engines_status(struct ibv_context *ctx, int num_engines)
75 uint32_t fpga_ident = 0;
79 for (i = 0; i < num_engines; i++) {
80 err = mlx5_devx_regex_register_read(ctx, i,
81 MLX5_RXP_CSR_IDENTIFIER,
83 fpga_ident = (fpga_ident & (0x0000FFFF));
84 if (err || fpga_ident != MLX5_RXP_IDENTIFIER) {
85 DRV_LOG(ERR, "Failed setup RXP %d err %d database "
86 "memory 0x%x", i, err, fpga_ident);
96 mlx5_regex_get_name(char *name, struct rte_device *dev)
98 sprintf(name, "mlx5_regex_%s", dev->name);
102 mlx5_regex_dev_probe(struct mlx5_common_device *cdev)
104 struct mlx5_regex_priv *priv = NULL;
105 struct mlx5_hca_attr *attr = &cdev->config.hca_attr;
106 char name[RTE_REGEXDEV_NAME_MAX_LEN];
108 if ((!attr->regexp_params && !attr->mmo_regex_sq_en && !attr->mmo_regex_qp_en)
109 || attr->regexp_num_of_engines == 0) {
110 DRV_LOG(ERR, "Not enough capabilities to support RegEx, maybe "
111 "old FW/OFED version?");
115 if (mlx5_regex_engines_status(cdev->ctx, 2)) {
116 DRV_LOG(ERR, "RegEx engine error.");
120 priv = rte_zmalloc("mlx5 regex device private", sizeof(*priv),
121 RTE_CACHE_LINE_SIZE);
123 DRV_LOG(ERR, "Failed to allocate private memory.");
127 priv->mmo_regex_qp_cap = attr->mmo_regex_qp_en;
128 priv->mmo_regex_sq_cap = attr->mmo_regex_sq_en;
130 priv->nb_engines = 2; /* attr.regexp_num_of_engines */
131 if (attr->regexp_version == MLX5_RXP_BF2_IDENTIFIER)
133 /* Default RXP programming mode to Shared. */
134 priv->prog_mode = MLX5_RXP_SHARED_PROG_MODE;
135 mlx5_regex_get_name(name, cdev->dev);
136 priv->regexdev = rte_regexdev_register(name);
137 if (priv->regexdev == NULL) {
138 DRV_LOG(ERR, "Failed to register RegEx device.");
139 rte_errno = rte_errno ? rte_errno : EINVAL;
143 * This PMD always claims the write memory barrier on UAR
144 * registers writings, it is safe to allocate UAR with any
145 * memory mapping type.
147 priv->uar = mlx5_devx_alloc_uar(priv->cdev->ctx, -1);
149 DRV_LOG(ERR, "can't allocate uar.");
153 priv->regexdev->dev_ops = &mlx5_regexdev_ops;
154 priv->regexdev->enqueue = mlx5_regexdev_enqueue;
155 #ifdef HAVE_MLX5_UMR_IMKEY
156 if (!attr->umr_indirect_mkey_disabled &&
157 !attr->umr_modify_entity_size_disabled)
160 priv->regexdev->enqueue = mlx5_regexdev_enqueue_gga;
162 priv->regexdev->dequeue = mlx5_regexdev_dequeue;
163 priv->regexdev->device = cdev->dev;
164 priv->regexdev->data->dev_private = priv;
165 priv->regexdev->state = RTE_REGEXDEV_READY;
166 DRV_LOG(INFO, "RegEx GGA is %s.",
167 priv->has_umr ? "supported" : "unsupported");
172 mlx5_glue->devx_free_uar(priv->uar);
174 rte_regexdev_unregister(priv->regexdev);
182 mlx5_regex_dev_remove(struct mlx5_common_device *cdev)
184 char name[RTE_REGEXDEV_NAME_MAX_LEN];
185 struct rte_regexdev *dev;
186 struct mlx5_regex_priv *priv = NULL;
188 mlx5_regex_get_name(name, cdev->dev);
189 dev = rte_regexdev_get_device_by_name(name);
192 priv = dev->data->dev_private;
195 mlx5_glue->devx_free_uar(priv->uar);
197 rte_regexdev_unregister(priv->regexdev);
203 static const struct rte_pci_id mlx5_regex_pci_id_map[] = {
205 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
206 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
209 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
210 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
217 static struct mlx5_class_driver mlx5_regex_driver = {
218 .drv_class = MLX5_CLASS_REGEX,
219 .name = RTE_STR(MLX5_REGEX_DRIVER_NAME),
220 .id_table = mlx5_regex_pci_id_map,
221 .probe = mlx5_regex_dev_probe,
222 .remove = mlx5_regex_dev_remove,
225 RTE_INIT(rte_mlx5_regex_init)
229 mlx5_class_driver_register(&mlx5_regex_driver);
232 RTE_LOG_REGISTER_DEFAULT(mlx5_regex_logtype, NOTICE)
233 RTE_PMD_EXPORT_NAME(MLX5_REGEX_DRIVER_NAME, __COUNTER__);
234 RTE_PMD_REGISTER_PCI_TABLE(MLX5_REGEX_DRIVER_NAME, mlx5_regex_pci_id_map);
235 RTE_PMD_REGISTER_KMOD_DEP(MLX5_REGEX_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");