drivers/regex/mlx5/mlx5_regex_fastpath.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2020 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <unistd.h>
   6 #include <strings.h>
   7 #include <stdint.h>
   8 #include <sys/mman.h>
   9
  10 #include <rte_malloc.h>
  11 #include <rte_log.h>
  12 #include <rte_errno.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_pci.h>
  15 #include <rte_regexdev_driver.h>
  16 #include <rte_mbuf.h>
  17
  18 #include <infiniband/mlx5dv.h>
  19 #include <mlx5_glue.h>
  20 #include <mlx5_common.h>
  21 #include <mlx5_prm.h>
  22
  23 #include "mlx5_regex_utils.h"
  24 #include "mlx5_rxp.h"
  25 #include "mlx5_regex.h"
  26
  27 #define MLX5_REGEX_MAX_WQE_INDEX 0xffff
  28 #define MLX5_REGEX_METADATA_SIZE ((size_t)64)
  29 #define MLX5_REGEX_MAX_OUTPUT (((size_t)1) << 11)
  30 #define MLX5_REGEX_WQE_CTRL_OFFSET 12
  31 #define MLX5_REGEX_WQE_METADATA_OFFSET 16
  32 #define MLX5_REGEX_WQE_GATHER_OFFSET 32
  33 #define MLX5_REGEX_WQE_SCATTER_OFFSET 48
  34 #define MLX5_REGEX_METADATA_OFF 32
  35 #define MLX5_REGEX_UMR_WQE_SIZE 192
  36 /* The maximum KLMs can be added to one UMR indirect mkey. */
  37 #define MLX5_REGEX_MAX_KLM_NUM 128
  38 /* The KLM array size for one job. */
  39 #define MLX5_REGEX_KLMS_SIZE \
  40         ((MLX5_REGEX_MAX_KLM_NUM) * sizeof(struct mlx5_klm))
  41 /* In WQE set mode, the pi should be quarter of the MLX5_REGEX_MAX_WQE_INDEX. */
  42 #define MLX5_REGEX_UMR_QP_PI_IDX(pi, ops) \
  43         (((pi) + (ops)) & (MLX5_REGEX_MAX_WQE_INDEX >> 2))
  44
  45 static inline uint32_t
  46 qp_size_get(struct mlx5_regex_hw_qp *qp)
  47 {
  48         return (1U << qp->log_nb_desc);
  49 }
  50
  51 static inline uint32_t
  52 cq_size_get(struct mlx5_regex_cq *cq)
  53 {
  54         return (1U << cq->log_nb_desc);
  55 }
  56
  57 struct mlx5_regex_job {
  58         uint64_t user_id;
  59         volatile uint8_t *output;
  60         volatile uint8_t *metadata;
  61         struct mlx5_klm *imkey_array; /* Indirect mkey's KLM array. */
  62         struct mlx5_devx_obj *imkey; /* UMR WQE's indirect meky. */
  63 } __rte_cached_aligned;
  64
  65 static inline void
  66 set_data_seg(struct mlx5_wqe_data_seg *seg,
  67              uint32_t length, uint32_t lkey,
  68              uintptr_t address)
  69 {
  70         seg->byte_count = rte_cpu_to_be_32(length);
  71         seg->lkey = rte_cpu_to_be_32(lkey);
  72         seg->addr = rte_cpu_to_be_64(address);
  73 }
  74
  75 static inline void
  76 set_metadata_seg(struct mlx5_wqe_metadata_seg *seg,
  77                  uint32_t mmo_control_31_0, uint32_t lkey,
  78                  uintptr_t address)
  79 {
  80         seg->mmo_control_31_0 = htobe32(mmo_control_31_0);
  81         seg->lkey = rte_cpu_to_be_32(lkey);
  82         seg->addr = rte_cpu_to_be_64(address);
  83 }
  84
  85 static inline void
  86 set_regex_ctrl_seg(void *seg, uint8_t le, uint16_t subset_id0,
  87                    uint16_t subset_id1, uint16_t subset_id2,
  88                    uint16_t subset_id3, uint8_t ctrl)
  89 {
  90         MLX5_SET(regexp_mmo_control, seg, le, le);
  91         MLX5_SET(regexp_mmo_control, seg, ctrl, ctrl);
  92         MLX5_SET(regexp_mmo_control, seg, subset_id_0, subset_id0);
  93         MLX5_SET(regexp_mmo_control, seg, subset_id_1, subset_id1);
  94         MLX5_SET(regexp_mmo_control, seg, subset_id_2, subset_id2);
  95         MLX5_SET(regexp_mmo_control, seg, subset_id_3, subset_id3);
  96 }
  97
  98 static inline void
  99 set_wqe_ctrl_seg(struct mlx5_wqe_ctrl_seg *seg, uint16_t pi, uint8_t opcode,
 100                  uint8_t opmod, uint32_t qp_num, uint8_t fm_ce_se, uint8_t ds,
 101                  uint8_t signature, uint32_t imm)
 102 {
 103         seg->opmod_idx_opcode = rte_cpu_to_be_32(((uint32_t)opmod << 24) |
 104                                                  ((uint32_t)pi << 8) |
 105                                                  opcode);
 106         seg->qpn_ds = rte_cpu_to_be_32((qp_num << 8) | ds);
 107         seg->fm_ce_se = fm_ce_se;
 108         seg->signature = signature;
 109         seg->imm = imm;
 110 }
 111
 112 static inline void
 113 __prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_hw_qp *qp_obj,
 114            struct rte_regex_ops *op, struct mlx5_regex_job *job,
 115            size_t pi, struct mlx5_klm *klm)
 116 {
 117         size_t wqe_offset = (pi & (qp_size_get(qp_obj) - 1)) *
 118                             (MLX5_SEND_WQE_BB << (priv->has_umr ? 2 : 0)) +
 119                             (priv->has_umr ? MLX5_REGEX_UMR_WQE_SIZE : 0);
 120         uint16_t group0 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID0_VALID_F ?
 121                                 op->group_id0 : 0;
 122         uint16_t group1 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID1_VALID_F ?
 123                                 op->group_id1 : 0;
 124         uint16_t group2 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID2_VALID_F ?
 125                                 op->group_id2 : 0;
 126         uint16_t group3 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID3_VALID_F ?
 127                                 op->group_id3 : 0;
 128         uint8_t control = op->req_flags &
 129                                 RTE_REGEX_OPS_REQ_MATCH_HIGH_PRIORITY_F ? 1 : 0;
 130
 131         /* For backward compatibility. */
 132         if (!(op->req_flags & (RTE_REGEX_OPS_REQ_GROUP_ID0_VALID_F |
 133                                RTE_REGEX_OPS_REQ_GROUP_ID1_VALID_F |
 134                                RTE_REGEX_OPS_REQ_GROUP_ID2_VALID_F |
 135                                RTE_REGEX_OPS_REQ_GROUP_ID3_VALID_F)))
 136                 group0 = op->group_id0;
 137         uint8_t *wqe = (uint8_t *)(uintptr_t)qp_obj->qp_obj.wqes + wqe_offset;
 138         int ds = 4; /*  ctrl + meta + input + output */
 139
 140         set_wqe_ctrl_seg((struct mlx5_wqe_ctrl_seg *)wqe,
 141                          (priv->has_umr ? (pi * 4 + 3) : pi),
 142                          MLX5_OPCODE_MMO, MLX5_OPC_MOD_MMO_REGEX,
 143                          qp_obj->qp_obj.qp->id, 0, ds, 0, 0);
 144         set_regex_ctrl_seg(wqe + 12, 0, group0, group1, group2, group3,
 145                            control);
 146         struct mlx5_wqe_data_seg *input_seg =
 147                 (struct mlx5_wqe_data_seg *)(wqe +
 148                                              MLX5_REGEX_WQE_GATHER_OFFSET);
 149         input_seg->byte_count = rte_cpu_to_be_32(klm->byte_count);
 150         input_seg->addr = rte_cpu_to_be_64(klm->address);
 151         input_seg->lkey = klm->mkey;
 152         job->user_id = op->user_id;
 153 }
 154
 155 static inline void
 156 prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,
 157          struct mlx5_regex_hw_qp *qp_obj, struct rte_regex_ops *op,
 158          struct mlx5_regex_job *job)
 159 {
 160         struct mlx5_klm klm;
 161
 162         klm.byte_count = rte_pktmbuf_data_len(op->mbuf);
 163         klm.mkey = mlx5_mr_mb2mr(&qp->mr_ctrl, op->mbuf);
 164         klm.address = rte_pktmbuf_mtod(op->mbuf, uintptr_t);
 165         __prep_one(priv, qp_obj, op, job, qp_obj->pi, &klm);
 166         qp_obj->db_pi = qp_obj->pi;
 167         qp_obj->pi = (qp_obj->pi + 1) & MLX5_REGEX_MAX_WQE_INDEX;
 168 }
 169
 170 static inline void
 171 send_doorbell(struct mlx5_regex_priv *priv, struct mlx5_regex_hw_qp *qp)
 172 {
 173         size_t wqe_offset = (qp->db_pi & (qp_size_get(qp) - 1)) *
 174                             (MLX5_SEND_WQE_BB << (priv->has_umr ? 2 : 0)) +
 175                             (priv->has_umr ? MLX5_REGEX_UMR_WQE_SIZE : 0);
 176         uint8_t *wqe = (uint8_t *)(uintptr_t)qp->qp_obj.wqes + wqe_offset;
 177         uint32_t actual_pi = (priv->has_umr ? (qp->db_pi * 4 + 3) : qp->db_pi) &
 178                              MLX5_REGEX_MAX_WQE_INDEX;
 179
 180         /* Or the fm_ce_se instead of set, avoid the fence be cleared. */
 181         ((struct mlx5_wqe_ctrl_seg *)wqe)->fm_ce_se |= MLX5_WQE_CTRL_CQ_UPDATE;
 182         mlx5_doorbell_ring(&priv->uar.bf_db, *(volatile uint64_t *)wqe,
 183                            actual_pi, &qp->qp_obj.db_rec[MLX5_SND_DBR],
 184                            !priv->uar.dbnc);
 185 }
 186
 187 static inline int
 188 get_free(struct mlx5_regex_hw_qp *qp, uint8_t has_umr) {
 189         return (qp_size_get(qp) - ((qp->pi - qp->ci) &
 190                         (has_umr ? (MLX5_REGEX_MAX_WQE_INDEX >> 2) :
 191                         MLX5_REGEX_MAX_WQE_INDEX)));
 192 }
 193
 194 static inline uint32_t
 195 job_id_get(uint32_t qid, size_t qp_size, size_t index) {
 196         return qid * qp_size + (index & (qp_size - 1));
 197 }
 198
 199 #ifdef HAVE_MLX5_UMR_IMKEY
 200 static inline int
 201 mkey_klm_available(struct mlx5_klm *klm, uint32_t pos, uint32_t new)
 202 {
 203         return (klm && ((pos + new) <= MLX5_REGEX_MAX_KLM_NUM));
 204 }
 205
 206 static inline void
 207 complete_umr_wqe(struct mlx5_regex_qp *qp, struct mlx5_regex_hw_qp *qp_obj,
 208                  struct mlx5_regex_job *mkey_job,
 209                  size_t umr_index, uint32_t klm_size, uint32_t total_len)
 210 {
 211         size_t wqe_offset = (umr_index & (qp_size_get(qp_obj) - 1)) *
 212                 (MLX5_SEND_WQE_BB * 4);
 213         struct mlx5_wqe_ctrl_seg *wqe = (struct mlx5_wqe_ctrl_seg *)((uint8_t *)
 214                                    (uintptr_t)qp_obj->qp_obj.wqes + wqe_offset);
 215         struct mlx5_wqe_umr_ctrl_seg *ucseg =
 216                                 (struct mlx5_wqe_umr_ctrl_seg *)(wqe + 1);
 217         struct mlx5_wqe_mkey_context_seg *mkc =
 218                                 (struct mlx5_wqe_mkey_context_seg *)(ucseg + 1);
 219         struct mlx5_klm *iklm = (struct mlx5_klm *)(mkc + 1);
 220         uint16_t klm_align = RTE_ALIGN(klm_size, 4);
 221
 222         memset(wqe, 0, MLX5_REGEX_UMR_WQE_SIZE);
 223         /* Set WQE control seg. Non-inline KLM UMR WQE size must be 9 WQE_DS. */
 224         set_wqe_ctrl_seg(wqe, (umr_index * 4), MLX5_OPCODE_UMR,
 225                          0, qp_obj->qp_obj.qp->id, 0, 9, 0,
 226                          rte_cpu_to_be_32(mkey_job->imkey->id));
 227         /* Set UMR WQE control seg. */
 228         ucseg->mkey_mask |= rte_cpu_to_be_64(MLX5_WQE_UMR_CTRL_MKEY_MASK_LEN |
 229                                 MLX5_WQE_UMR_CTRL_FLAG_TRNSLATION_OFFSET |
 230                                 MLX5_WQE_UMR_CTRL_MKEY_MASK_ACCESS_LOCAL_WRITE);
 231         ucseg->klm_octowords = rte_cpu_to_be_16(klm_align);
 232         /* Set mkey context seg. */
 233         mkc->len = rte_cpu_to_be_64(total_len);
 234         mkc->qpn_mkey = rte_cpu_to_be_32(0xffffff00 |
 235                                         (mkey_job->imkey->id & 0xff));
 236         /* Set UMR pointer to data seg. */
 237         iklm->address = rte_cpu_to_be_64
 238                                 ((uintptr_t)((char *)mkey_job->imkey_array));
 239         iklm->mkey = rte_cpu_to_be_32(qp->imkey_addr->lkey);
 240         iklm->byte_count = rte_cpu_to_be_32(klm_align);
 241         /* Clear the padding memory. */
 242         memset((uint8_t *)&mkey_job->imkey_array[klm_size], 0,
 243                sizeof(struct mlx5_klm) * (klm_align - klm_size));
 244
 245         /* Add the following RegEx WQE with fence. */
 246         wqe = (struct mlx5_wqe_ctrl_seg *)
 247                                 (((uint8_t *)wqe) + MLX5_REGEX_UMR_WQE_SIZE);
 248         wqe->fm_ce_se |= MLX5_WQE_CTRL_INITIATOR_SMALL_FENCE;
 249 }
 250
 251 static inline void
 252 prep_nop_regex_wqe_set(struct mlx5_regex_priv *priv,
 253                 struct mlx5_regex_hw_qp *qp, struct rte_regex_ops *op,
 254                 struct mlx5_regex_job *job, size_t pi, struct mlx5_klm *klm)
 255 {
 256         size_t wqe_offset = (pi & (qp_size_get(qp) - 1)) *
 257                             (MLX5_SEND_WQE_BB << 2);
 258         struct mlx5_wqe_ctrl_seg *wqe = (struct mlx5_wqe_ctrl_seg *)((uint8_t *)
 259                                    (uintptr_t)qp->qp_obj.wqes + wqe_offset);
 260
 261         /* Clear the WQE memory used as UMR WQE previously. */
 262         if ((rte_be_to_cpu_32(wqe->opmod_idx_opcode) & 0xff) != MLX5_OPCODE_NOP)
 263                 memset(wqe, 0, MLX5_REGEX_UMR_WQE_SIZE);
 264         /* UMR WQE size is 9 DS, align nop WQE to 3 WQEBBS(12 DS). */
 265         set_wqe_ctrl_seg(wqe, pi * 4, MLX5_OPCODE_NOP, 0, qp->qp_obj.qp->id,
 266                          0, 12, 0, 0);
 267         __prep_one(priv, qp, op, job, pi, klm);
 268 }
 269
 270 static inline void
 271 prep_regex_umr_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,
 272                 struct mlx5_regex_hw_qp *qp_obj, struct rte_regex_ops **op,
 273                 size_t nb_ops)
 274 {
 275         struct mlx5_regex_job *job = NULL;
 276         size_t hw_qpid = qp_obj->qpn, mkey_job_id = 0;
 277         size_t left_ops = nb_ops;
 278         uint32_t klm_num = 0;
 279         uint32_t len = 0;
 280         struct mlx5_klm *mkey_klm = NULL;
 281         struct mlx5_klm klm;
 282         uintptr_t addr;
 283
 284         while (left_ops--)
 285                 rte_prefetch0(op[left_ops]);
 286         left_ops = nb_ops;
 287         /*
 288          * Build the WQE set by reverse. In case the burst may consume
 289          * multiple mkeys, build the WQE set as normal will hard to
 290          * address the last mkey index, since we will only know the last
 291          * RegEx WQE's index when finishes building.
 292          */
 293         while (left_ops--) {
 294                 struct rte_mbuf *mbuf = op[left_ops]->mbuf;
 295                 size_t pi = MLX5_REGEX_UMR_QP_PI_IDX(qp_obj->pi, left_ops);
 296
 297                 if (mbuf->nb_segs > 1) {
 298                         size_t scatter_size = 0;
 299
 300                         if (!mkey_klm_available(mkey_klm, klm_num,
 301                                                 mbuf->nb_segs)) {
 302                                 /*
 303                                  * The mkey's KLM is full, create the UMR
 304                                  * WQE in the next WQE set.
 305                                  */
 306                                 if (mkey_klm)
 307                                         complete_umr_wqe(qp, qp_obj,
 308                                                 &qp->jobs[mkey_job_id],
 309                                                 MLX5_REGEX_UMR_QP_PI_IDX(pi, 1),
 310                                                 klm_num, len);
 311                                 /*
 312                                  * Get the indircet mkey and KLM array index
 313                                  * from the last WQE set.
 314                                  */
 315                                 mkey_job_id = job_id_get(hw_qpid,
 316                                                 qp_size_get(qp_obj), pi);
 317                                 mkey_klm = qp->jobs[mkey_job_id].imkey_array;
 318                                 klm_num = 0;
 319                                 len = 0;
 320                         }
 321                         /* Build RegEx WQE's data segment KLM. */
 322                         klm.address = len;
 323                         klm.mkey = rte_cpu_to_be_32
 324                                         (qp->jobs[mkey_job_id].imkey->id);
 325                         while (mbuf) {
 326                                 addr = rte_pktmbuf_mtod(mbuf, uintptr_t);
 327                                 /* Build indirect mkey seg's KLM. */
 328                                 mkey_klm->mkey = mlx5_mr_mb2mr(&qp->mr_ctrl,
 329                                                                mbuf);
 330                                 mkey_klm->address = rte_cpu_to_be_64(addr);
 331                                 mkey_klm->byte_count = rte_cpu_to_be_32
 332                                                 (rte_pktmbuf_data_len(mbuf));
 333                                 /*
 334                                  * Save the mbuf's total size for RegEx data
 335                                  * segment.
 336                                  */
 337                                 scatter_size += rte_pktmbuf_data_len(mbuf);
 338                                 mkey_klm++;
 339                                 klm_num++;
 340                                 mbuf = mbuf->next;
 341                         }
 342                         len += scatter_size;
 343                         klm.byte_count = scatter_size;
 344                 } else {
 345                         /* The single mubf case. Build the KLM directly. */
 346                         klm.mkey = mlx5_mr_mb2mr(&qp->mr_ctrl, mbuf);
 347                         klm.address = rte_pktmbuf_mtod(mbuf, uintptr_t);
 348                         klm.byte_count = rte_pktmbuf_data_len(mbuf);
 349                 }
 350                 job = &qp->jobs[job_id_get(hw_qpid, qp_size_get(qp_obj), pi)];
 351                 /*
 352                  * Build the nop + RegEx WQE set by default. The fist nop WQE
 353                  * will be updated later as UMR WQE if scattered mubf exist.
 354                  */
 355                 prep_nop_regex_wqe_set(priv, qp_obj, op[left_ops], job, pi,
 356                                         &klm);
 357         }
 358         /*
 359          * Scattered mbuf have been added to the KLM array. Complete the build
 360          * of UMR WQE, update the first nop WQE as UMR WQE.
 361          */
 362         if (mkey_klm)
 363                 complete_umr_wqe(qp, qp_obj, &qp->jobs[mkey_job_id], qp_obj->pi,
 364                                  klm_num, len);
 365         qp_obj->db_pi = MLX5_REGEX_UMR_QP_PI_IDX(qp_obj->pi, nb_ops - 1);
 366         qp_obj->pi = MLX5_REGEX_UMR_QP_PI_IDX(qp_obj->pi, nb_ops);
 367 }
 368
 369 uint16_t
 370 mlx5_regexdev_enqueue_gga(struct rte_regexdev *dev, uint16_t qp_id,
 371                           struct rte_regex_ops **ops, uint16_t nb_ops)
 372 {
 373         struct mlx5_regex_priv *priv = dev->data->dev_private;
 374         struct mlx5_regex_qp *queue = &priv->qps[qp_id];
 375         struct mlx5_regex_hw_qp *qp_obj;
 376         size_t hw_qpid, nb_left = nb_ops, nb_desc;
 377
 378         while ((hw_qpid = ffs(queue->free_qps))) {
 379                 hw_qpid--; /* ffs returns 1 for bit 0 */
 380                 qp_obj = &queue->qps[hw_qpid];
 381                 nb_desc = get_free(qp_obj, priv->has_umr);
 382                 if (nb_desc) {
 383                         /* The ops be handled can't exceed nb_ops. */
 384                         if (nb_desc > nb_left)
 385                                 nb_desc = nb_left;
 386                         else
 387                                 queue->free_qps &= ~(1 << hw_qpid);
 388                         prep_regex_umr_wqe_set(priv, queue, qp_obj, ops,
 389                                 nb_desc);
 390                         send_doorbell(priv, qp_obj);
 391                         nb_left -= nb_desc;
 392                 }
 393                 if (!nb_left)
 394                         break;
 395                 ops += nb_desc;
 396         }
 397         nb_ops -= nb_left;
 398         queue->pi += nb_ops;
 399         return nb_ops;
 400 }
 401 #endif
 402
 403 uint16_t
 404 mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id,
 405                       struct rte_regex_ops **ops, uint16_t nb_ops)
 406 {
 407         struct mlx5_regex_priv *priv = dev->data->dev_private;
 408         struct mlx5_regex_qp *queue = &priv->qps[qp_id];
 409         struct mlx5_regex_hw_qp *qp_obj;
 410         size_t hw_qpid, job_id, i = 0;
 411
 412         while ((hw_qpid = ffs(queue->free_qps))) {
 413                 hw_qpid--; /* ffs returns 1 for bit 0 */
 414                 qp_obj = &queue->qps[hw_qpid];
 415                 while (get_free(qp_obj, priv->has_umr)) {
 416                         job_id = job_id_get(hw_qpid, qp_size_get(qp_obj),
 417                                 qp_obj->pi);
 418                         prep_one(priv, queue, qp_obj, ops[i],
 419                                 &queue->jobs[job_id]);
 420                         i++;
 421                         if (unlikely(i == nb_ops)) {
 422                                 send_doorbell(priv, qp_obj);
 423                                 goto out;
 424                         }
 425                 }
 426                 queue->free_qps &= ~(1 << hw_qpid);
 427                 send_doorbell(priv, qp_obj);
 428         }
 429
 430 out:
 431         queue->pi += i;
 432         return i;
 433 }
 434
 435 #define MLX5_REGEX_RESP_SZ 8
 436
 437 static inline void
 438 extract_result(struct rte_regex_ops *op, struct mlx5_regex_job *job)
 439 {
 440         size_t j;
 441         size_t offset;
 442         uint16_t status;
 443
 444         op->user_id = job->user_id;
 445         op->nb_matches = MLX5_GET_VOLATILE(regexp_metadata, job->metadata +
 446                                            MLX5_REGEX_METADATA_OFF,
 447                                            match_count);
 448         op->nb_actual_matches = MLX5_GET_VOLATILE(regexp_metadata,
 449                                                   job->metadata +
 450                                                   MLX5_REGEX_METADATA_OFF,
 451                                                   detected_match_count);
 452         for (j = 0; j < op->nb_matches; j++) {
 453                 offset = MLX5_REGEX_RESP_SZ * j;
 454                 op->matches[j].rule_id =
 455                         MLX5_GET_VOLATILE(regexp_match_tuple,
 456                                           (job->output + offset), rule_id);
 457                 op->matches[j].start_offset =
 458                         MLX5_GET_VOLATILE(regexp_match_tuple,
 459                                           (job->output +  offset), start_ptr);
 460                 op->matches[j].len =
 461                         MLX5_GET_VOLATILE(regexp_match_tuple,
 462                                           (job->output +  offset), length);
 463         }
 464         status = MLX5_GET_VOLATILE(regexp_metadata, job->metadata +
 465                                    MLX5_REGEX_METADATA_OFF,
 466                                    status);
 467         op->rsp_flags = 0;
 468         if (status & MLX5_RXP_RESP_STATUS_PMI_SOJ)
 469                 op->rsp_flags |= RTE_REGEX_OPS_RSP_PMI_SOJ_F;
 470         if (status & MLX5_RXP_RESP_STATUS_PMI_EOJ)
 471                 op->rsp_flags |= RTE_REGEX_OPS_RSP_PMI_EOJ_F;
 472         if (status & MLX5_RXP_RESP_STATUS_MAX_LATENCY)
 473                 op->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_SCAN_TIMEOUT_F;
 474         if (status & MLX5_RXP_RESP_STATUS_MAX_MATCH)
 475                 op->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_MATCH_F;
 476         if (status & MLX5_RXP_RESP_STATUS_MAX_PREFIX)
 477                 op->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_PREFIX_F;
 478         if (status & MLX5_RXP_RESP_STATUS_MAX_PRI_THREADS)
 479                 op->rsp_flags |= RTE_REGEX_OPS_RSP_RESOURCE_LIMIT_REACHED_F;
 480         if (status & MLX5_RXP_RESP_STATUS_MAX_SEC_THREADS)
 481                 op->rsp_flags |= RTE_REGEX_OPS_RSP_RESOURCE_LIMIT_REACHED_F;
 482 }
 483
 484 static inline volatile struct mlx5_cqe *
 485 poll_one(struct mlx5_regex_cq *cq)
 486 {
 487         volatile struct mlx5_cqe *cqe;
 488         size_t next_cqe_offset;
 489
 490         next_cqe_offset =  (cq->ci & (cq_size_get(cq) - 1));
 491         cqe = (volatile struct mlx5_cqe *)(cq->cq_obj.cqes + next_cqe_offset);
 492         rte_io_wmb();
 493
 494         int ret = check_cqe(cqe, cq_size_get(cq), cq->ci);
 495
 496         if (unlikely(ret == MLX5_CQE_STATUS_ERR)) {
 497                 DRV_LOG(ERR, "Completion with error on qp 0x%x",  0);
 498                 return NULL;
 499         }
 500
 501         if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN))
 502                 return NULL;
 503
 504         return cqe;
 505 }
 506
 507
 508 /**
 509  * DPDK callback for dequeue.
 510  *
 511  * @param dev
 512  *   Pointer to the regex dev structure.
 513  * @param qp_id
 514  *   The queue to enqueue the traffic to.
 515  * @param ops
 516  *   List of regex ops to dequeue.
 517  * @param nb_ops
 518  *   Number of ops in ops parameter.
 519  *
 520  * @return
 521  *   Number of packets successfully dequeued (<= pkts_n).
 522  */
 523 uint16_t
 524 mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id,
 525                       struct rte_regex_ops **ops, uint16_t nb_ops)
 526 {
 527         struct mlx5_regex_priv *priv = dev->data->dev_private;
 528         struct mlx5_regex_qp *queue = &priv->qps[qp_id];
 529         struct mlx5_regex_cq *cq = &queue->cq;
 530         volatile struct mlx5_cqe *cqe;
 531         size_t i = 0;
 532
 533         while ((cqe = poll_one(cq))) {
 534                 uint16_t wq_counter
 535                         = (rte_be_to_cpu_16(cqe->wqe_counter) + 1) &
 536                           MLX5_REGEX_MAX_WQE_INDEX;
 537                 size_t hw_qpid = cqe->user_index_bytes[2];
 538                 struct mlx5_regex_hw_qp *qp_obj = &queue->qps[hw_qpid];
 539
 540                 /* UMR mode WQE counter move as WQE set(4 WQEBBS).*/
 541                 if (priv->has_umr)
 542                         wq_counter >>= 2;
 543                 while (qp_obj->ci != wq_counter) {
 544                         if (unlikely(i == nb_ops)) {
 545                                 /* Return without updating cq->ci */
 546                                 goto out;
 547                         }
 548                         uint32_t job_id = job_id_get(hw_qpid,
 549                                         qp_size_get(qp_obj), qp_obj->ci);
 550                         extract_result(ops[i], &queue->jobs[job_id]);
 551                         qp_obj->ci = (qp_obj->ci + 1) & (priv->has_umr ?
 552                                  (MLX5_REGEX_MAX_WQE_INDEX >> 2) :
 553                                   MLX5_REGEX_MAX_WQE_INDEX);
 554                         i++;
 555                 }
 556                 cq->ci = (cq->ci + 1) & 0xffffff;
 557                 rte_wmb();
 558                 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->ci);
 559                 queue->free_qps |= (1 << hw_qpid);
 560         }
 561
 562 out:
 563         queue->ci += i;
 564         return i;
 565 }
 566
 567 static void
 568 setup_qps(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *queue)
 569 {
 570         size_t hw_qpid, entry;
 571         uint32_t job_id;
 572         for (hw_qpid = 0; hw_qpid < queue->nb_obj; hw_qpid++) {
 573                 struct mlx5_regex_hw_qp *qp_obj = &queue->qps[hw_qpid];
 574                 uint8_t *wqe = (uint8_t *)(uintptr_t)qp_obj->qp_obj.wqes;
 575                 for (entry = 0 ; entry < qp_size_get(qp_obj); entry++) {
 576                         job_id = hw_qpid * qp_size_get(qp_obj) + entry;
 577                         struct mlx5_regex_job *job = &queue->jobs[job_id];
 578
 579                         /* Fill UMR WQE with NOP in advanced. */
 580                         if (priv->has_umr) {
 581                                 set_wqe_ctrl_seg
 582                                         ((struct mlx5_wqe_ctrl_seg *)wqe,
 583                                          entry * 2, MLX5_OPCODE_NOP, 0,
 584                                          qp_obj->qp_obj.qp->id, 0, 12, 0, 0);
 585                                 wqe += MLX5_REGEX_UMR_WQE_SIZE;
 586                         }
 587                         set_metadata_seg((struct mlx5_wqe_metadata_seg *)
 588                                          (wqe + MLX5_REGEX_WQE_METADATA_OFFSET),
 589                                          0, queue->metadata->lkey,
 590                                          (uintptr_t)job->metadata);
 591                         set_data_seg((struct mlx5_wqe_data_seg *)
 592                                      (wqe + MLX5_REGEX_WQE_SCATTER_OFFSET),
 593                                      MLX5_REGEX_MAX_OUTPUT,
 594                                      queue->outputs->lkey,
 595                                      (uintptr_t)job->output);
 596                         wqe += 64;
 597                 }
 598                 queue->free_qps |= 1 << hw_qpid;
 599         }
 600 }
 601
 602 static int
 603 setup_buffers(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp)
 604 {
 605         struct ibv_pd *pd = priv->cdev->pd;
 606         uint32_t i;
 607         int err;
 608
 609         void *ptr = rte_calloc(__func__, qp->nb_desc,
 610                                MLX5_REGEX_METADATA_SIZE,
 611                                MLX5_REGEX_METADATA_SIZE);
 612         if (!ptr)
 613                 return -ENOMEM;
 614
 615         qp->metadata = mlx5_glue->reg_mr(pd, ptr,
 616                                          MLX5_REGEX_METADATA_SIZE * qp->nb_desc,
 617                                          IBV_ACCESS_LOCAL_WRITE);
 618         if (!qp->metadata) {
 619                 DRV_LOG(ERR, "Failed to register metadata");
 620                 rte_free(ptr);
 621                 return -EINVAL;
 622         }
 623
 624         ptr = rte_calloc(__func__, qp->nb_desc,
 625                          MLX5_REGEX_MAX_OUTPUT,
 626                          MLX5_REGEX_MAX_OUTPUT);
 627         if (!ptr) {
 628                 err = -ENOMEM;
 629                 goto err_output;
 630         }
 631         qp->outputs = mlx5_glue->reg_mr(pd, ptr,
 632                                         MLX5_REGEX_MAX_OUTPUT * qp->nb_desc,
 633                                         IBV_ACCESS_LOCAL_WRITE);
 634         if (!qp->outputs) {
 635                 rte_free(ptr);
 636                 DRV_LOG(ERR, "Failed to register output");
 637                 err = -EINVAL;
 638                 goto err_output;
 639         }
 640
 641         if (priv->has_umr) {
 642                 ptr = rte_calloc(__func__, qp->nb_desc, MLX5_REGEX_KLMS_SIZE,
 643                                  MLX5_REGEX_KLMS_SIZE);
 644                 if (!ptr) {
 645                         err = -ENOMEM;
 646                         goto err_imkey;
 647                 }
 648                 qp->imkey_addr = mlx5_glue->reg_mr(pd, ptr,
 649                                         MLX5_REGEX_KLMS_SIZE * qp->nb_desc,
 650                                         IBV_ACCESS_LOCAL_WRITE);
 651                 if (!qp->imkey_addr) {
 652                         rte_free(ptr);
 653                         DRV_LOG(ERR, "Failed to register output");
 654                         err = -EINVAL;
 655                         goto err_imkey;
 656                 }
 657         }
 658
 659         /* distribute buffers to jobs */
 660         for (i = 0; i < qp->nb_desc; i++) {
 661                 qp->jobs[i].output =
 662                         (uint8_t *)qp->outputs->addr +
 663                         (i % qp->nb_desc) * MLX5_REGEX_MAX_OUTPUT;
 664                 qp->jobs[i].metadata =
 665                         (uint8_t *)qp->metadata->addr +
 666                         (i % qp->nb_desc) * MLX5_REGEX_METADATA_SIZE;
 667                 if (qp->imkey_addr)
 668                         qp->jobs[i].imkey_array = (struct mlx5_klm *)
 669                                 qp->imkey_addr->addr +
 670                                 (i % qp->nb_desc) * MLX5_REGEX_MAX_KLM_NUM;
 671         }
 672
 673         return 0;
 674
 675 err_imkey:
 676         ptr = qp->outputs->addr;
 677         rte_free(ptr);
 678         mlx5_glue->dereg_mr(qp->outputs);
 679 err_output:
 680         ptr = qp->metadata->addr;
 681         rte_free(ptr);
 682         mlx5_glue->dereg_mr(qp->metadata);
 683         return err;
 684 }
 685
 686 int
 687 mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id)
 688 {
 689         struct mlx5_regex_qp *qp = &priv->qps[qp_id];
 690         struct mlx5_klm klm = { 0 };
 691         struct mlx5_devx_mkey_attr attr = {
 692                 .klm_array = &klm,
 693                 .klm_num = 1,
 694                 .umr_en = 1,
 695         };
 696         uint32_t i;
 697         int err = 0;
 698
 699         qp->jobs = rte_calloc(__func__, qp->nb_desc, sizeof(*qp->jobs), 64);
 700         if (!qp->jobs)
 701                 return -ENOMEM;
 702         err = setup_buffers(priv, qp);
 703         if (err) {
 704                 rte_free(qp->jobs);
 705                 qp->jobs = NULL;
 706                 return err;
 707         }
 708
 709         setup_qps(priv, qp);
 710
 711         if (priv->has_umr) {
 712 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 713                 attr.pd = priv->cdev->pdn;
 714 #endif
 715                 for (i = 0; i < qp->nb_desc; i++) {
 716                         attr.klm_num = MLX5_REGEX_MAX_KLM_NUM;
 717                         attr.klm_array = qp->jobs[i].imkey_array;
 718                         qp->jobs[i].imkey = mlx5_devx_cmd_mkey_create
 719                                                        (priv->cdev->ctx, &attr);
 720                         if (!qp->jobs[i].imkey) {
 721                                 err = -rte_errno;
 722                                 DRV_LOG(ERR, "Failed to allocate imkey.");
 723                                 mlx5_regexdev_teardown_fastpath(priv, qp_id);
 724                         }
 725                 }
 726         }
 727         return err;
 728 }
 729
 730 static void
 731 free_buffers(struct mlx5_regex_qp *qp)
 732 {
 733         if (qp->imkey_addr) {
 734                 mlx5_glue->dereg_mr(qp->imkey_addr);
 735                 rte_free(qp->imkey_addr->addr);
 736         }
 737         if (qp->metadata) {
 738                 mlx5_glue->dereg_mr(qp->metadata);
 739                 rte_free(qp->metadata->addr);
 740         }
 741         if (qp->outputs) {
 742                 mlx5_glue->dereg_mr(qp->outputs);
 743                 rte_free(qp->outputs->addr);
 744         }
 745 }
 746
 747 void
 748 mlx5_regexdev_teardown_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id)
 749 {
 750         struct mlx5_regex_qp *qp = &priv->qps[qp_id];
 751         uint32_t i;
 752
 753         if (qp->jobs) {
 754                 for (i = 0; i < qp->nb_desc; i++) {
 755                         if (qp->jobs[i].imkey)
 756                                 claim_zero(mlx5_devx_cmd_destroy
 757                                                         (qp->jobs[i].imkey));
 758                 }
 759                 free_buffers(qp);
 760                 rte_free(qp->jobs);
 761                 qp->jobs = NULL;
 762         }
 763 }