1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
7 #include <rte_malloc.h>
8 #include <rte_regexdev.h>
9 #include <rte_regexdev_core.h>
10 #include <rte_regexdev_driver.h>
13 #include <mlx5_glue.h>
14 #include <mlx5_devx_cmds.h>
16 #include <mlx5_common_os.h>
18 #include "mlx5_regex.h"
19 #include "mlx5_regex_utils.h"
20 #include "mlx5_rxp_csrs.h"
23 #define MLX5_REGEX_MAX_MATCHES MLX5_RXP_MAX_MATCHES
24 #define MLX5_REGEX_MAX_PAYLOAD_SIZE MLX5_RXP_MAX_JOB_LENGTH
25 #define MLX5_REGEX_MAX_RULES_PER_GROUP UINT32_MAX
26 #define MLX5_REGEX_MAX_GROUPS MLX5_RXP_MAX_SUBSETS
28 #define MLX5_REGEX_RXP_ROF2_LINE_LEN 34
30 /* Private Declarations */
32 rxp_poll_csr_for_value(struct ibv_context *ctx, uint32_t *value,
33 uint32_t address, uint32_t expected_value,
34 uint32_t expected_mask, uint32_t timeout_ms, uint8_t id);
36 mlnx_resume_database(struct mlx5_regex_priv *priv, uint8_t id);
38 mlnx_update_database(struct mlx5_regex_priv *priv, uint8_t id);
40 program_rxp_rules(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,
43 rxp_init_eng(struct mlx5_regex_priv *priv, uint8_t id);
45 rxp_db_setup(struct mlx5_regex_priv *priv);
47 rxp_dump_csrs(struct ibv_context *ctx, uint8_t id);
49 rxp_start_engine(struct ibv_context *ctx, uint8_t id);
51 rxp_stop_engine(struct ibv_context *ctx, uint8_t id);
53 static void __rte_unused
54 rxp_dump_csrs(struct ibv_context *ctx __rte_unused, uint8_t id __rte_unused)
59 for (i = 0; i < MLX5_RXP_CSR_NUM_ENTRIES; i++) {
60 if (mlx5_devx_regex_register_read(ctx, id,
61 (MLX5_RXP_CSR_WIDTH * i) +
62 MLX5_RXP_CSR_BASE_ADDRESS,
64 DRV_LOG(ERR, "Failed to read Main CSRs Engine %d!", id);
67 DRV_LOG(DEBUG, "RXP Main CSRs (Eng%d) register (%d): %08x",
71 for (i = 0; i < MLX5_RXP_CSR_NUM_ENTRIES; i++) {
72 if (mlx5_devx_regex_register_read(ctx, id,
73 (MLX5_RXP_CSR_WIDTH * i) +
74 MLX5_RXP_RTRU_CSR_BASE_ADDRESS,
76 DRV_LOG(ERR, "Failed to read RTRU CSRs Engine %d!", id);
79 DRV_LOG(DEBUG, "RXP RTRU CSRs (Eng%d) register (%d): %08x",
83 for (i = 0; i < MLX5_RXP_CSR_NUM_ENTRIES; i++) {
84 if (mlx5_devx_regex_register_read(ctx, id,
85 (MLX5_RXP_CSR_WIDTH * i) +
86 MLX5_RXP_STATS_CSR_BASE_ADDRESS,
88 DRV_LOG(ERR, "Failed to read STAT CSRs Engine %d!", id);
91 DRV_LOG(DEBUG, "RXP STAT CSRs (Eng%d) register (%d): %08x",
97 mlx5_regex_info_get(struct rte_regexdev *dev __rte_unused,
98 struct rte_regexdev_info *info)
100 info->max_matches = MLX5_REGEX_MAX_MATCHES;
101 info->max_payload_size = MLX5_REGEX_MAX_PAYLOAD_SIZE;
102 info->max_rules_per_group = MLX5_REGEX_MAX_RULES_PER_GROUP;
103 info->max_groups = MLX5_REGEX_MAX_GROUPS;
104 info->regexdev_capa = RTE_REGEXDEV_SUPP_PCRE_GREEDY_F |
105 RTE_REGEXDEV_CAPA_QUEUE_PAIR_OOS_F;
106 info->rule_flags = 0;
107 info->max_queue_pairs = UINT16_MAX;
112 rxp_poll_csr_for_value(struct ibv_context *ctx, uint32_t *value,
113 uint32_t address, uint32_t expected_value,
114 uint32_t expected_mask, uint32_t timeout_ms, uint8_t id)
120 for (i = 0; i < timeout_ms; i++) {
121 if (mlx5_devx_regex_register_read(ctx, id, address, value))
123 if ((*value & expected_mask) == expected_value) {
133 rxp_start_engine(struct ibv_context *ctx, uint8_t id)
138 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);
141 ctrl |= MLX5_RXP_CSR_CTRL_GO;
142 ctrl |= MLX5_RXP_CSR_CTRL_DISABLE_L2C;
143 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
148 rxp_stop_engine(struct ibv_context *ctx, uint8_t id)
153 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);
156 ctrl &= ~MLX5_RXP_CSR_CTRL_GO;
157 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
162 rxp_init_rtru(struct mlx5_regex_priv *priv, uint8_t id, uint32_t init_bits)
166 uint32_t expected_value;
167 uint32_t expected_mask;
168 struct ibv_context *ctx = priv->cdev->ctx;
171 /* Read the rtru ctrl CSR. */
172 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
176 /* Clear any previous init modes. */
177 ctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_MASK);
178 if (ctrl_value & MLX5_RXP_RTRU_CSR_CTRL_INIT) {
179 ctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT);
180 mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
183 /* Set the init_mode bits in the rtru ctrl CSR. */
184 ctrl_value |= init_bits;
185 mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
187 /* Need to sleep for a short period after pulsing the rtru init bit. */
189 /* Poll the rtru status CSR until all the init done bits are set. */
190 DRV_LOG(DEBUG, "waiting for RXP rule memory to complete init");
191 /* Set the init bit in the rtru ctrl CSR. */
192 ctrl_value |= MLX5_RXP_RTRU_CSR_CTRL_INIT;
193 mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
195 /* Clear the init bit in the rtru ctrl CSR */
196 ctrl_value &= ~MLX5_RXP_RTRU_CSR_CTRL_INIT;
197 mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
199 /* Check that the following bits are set in the RTRU_CSR. */
200 if (init_bits == MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_L1_L2) {
201 /* Must be incremental mode */
202 expected_value = MLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE;
204 expected_value = MLX5_RXP_RTRU_CSR_STATUS_IM_INIT_DONE |
205 MLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE;
208 expected_value |= MLX5_RXP_RTRU_CSR_STATUS_L2C_INIT_DONE;
211 expected_mask = expected_value;
212 ret = rxp_poll_csr_for_value(ctx, &poll_value,
213 MLX5_RXP_RTRU_CSR_STATUS,
214 expected_value, expected_mask,
215 MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT, id);
218 DRV_LOG(DEBUG, "rule memory initialise: 0x%08X", poll_value);
219 /* Clear the init bit in the rtru ctrl CSR */
220 ctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT);
221 mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
227 rxp_parse_line(char *line, uint32_t *type, uint32_t *address, uint64_t *value)
231 if (*line == '\0' || *line == '#')
233 *type = strtoul(line, &cur_pos, 10);
234 if (*cur_pos != ',' && *cur_pos != '\0')
236 *address = strtoul(cur_pos+1, &cur_pos, 16);
237 if (*cur_pos != ',' && *cur_pos != '\0')
239 *value = strtoul(cur_pos+1, &cur_pos, 16);
240 if (*cur_pos != ',' && *cur_pos != '\0')
246 rxp_get_reg_address(uint32_t address)
251 block = (address >> 16) & 0xFFFF;
253 reg = MLX5_RXP_CSR_BASE_ADDRESS;
255 reg = MLX5_RXP_RTRU_CSR_BASE_ADDRESS;
257 DRV_LOG(ERR, "Invalid ROF register 0x%08X!", address);
260 reg += (address & 0xFFFF) * MLX5_RXP_CSR_WIDTH;
264 #define MLX5_RXP_NUM_LINES_PER_BLOCK 8
267 rxp_program_rof(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,
270 static const char del[] = "\n\r";
282 uint32_t rof_rule_addr;
283 uint64_t tmp_write_swap[4];
284 struct mlx5_rxp_rof_entry rules[8];
289 tmp = rte_malloc("", len, 0);
292 memcpy(tmp, buf, len);
293 db_free = mlnx_update_database(priv, id);
295 DRV_LOG(ERR, "Failed to setup db memory!");
299 for (line = strtok(tmp, del), j = 0; line; line = strtok(NULL, del),
301 ret = rxp_parse_line(line, &type, &address, &val);
308 case MLX5_RXP_ROF_ENTRY_EQ:
309 if (skip == 0 && address == 0)
311 tmp_addr = rxp_get_reg_address(address);
312 if (tmp_addr == UINT32_MAX)
314 ret = mlx5_devx_regex_register_read(priv->cdev->ctx, id,
318 if (skip == -1 && address == 0) {
319 if (val == reg_val) {
323 } else if (skip == 0) {
324 if (val != reg_val) {
326 "got %08X expected == %" PRIx64,
332 case MLX5_RXP_ROF_ENTRY_GTE:
333 if (skip == 0 && address == 0)
335 tmp_addr = rxp_get_reg_address(address);
336 if (tmp_addr == UINT32_MAX)
338 ret = mlx5_devx_regex_register_read(priv->cdev->ctx, id,
342 if (skip == -1 && address == 0) {
343 if (reg_val >= val) {
347 } else if (skip == 0) {
350 "got %08X expected >= %" PRIx64,
356 case MLX5_RXP_ROF_ENTRY_LTE:
357 tmp_addr = rxp_get_reg_address(address);
358 if (tmp_addr == UINT32_MAX)
360 ret = mlx5_devx_regex_register_read(priv->cdev->ctx, id,
364 if (skip == 0 && address == 0 &&
365 last != MLX5_RXP_ROF_ENTRY_GTE) {
367 } else if (skip == 0 && address == 0 &&
368 last == MLX5_RXP_ROF_ENTRY_GTE) {
373 if (skip == -1 && address == 0) {
374 if (reg_val <= val) {
378 } else if (skip == 0) {
381 "got %08X expected <= %" PRIx64,
387 case MLX5_RXP_ROF_ENTRY_CHECKSUM:
389 case MLX5_RXP_ROF_ENTRY_CHECKSUM_EX_EM:
392 tmp_addr = rxp_get_reg_address(address);
393 if (tmp_addr == UINT32_MAX)
396 ret = mlx5_devx_regex_register_read(priv->cdev->ctx, id,
399 DRV_LOG(ERR, "RXP CSR read failed!");
402 if (reg_val != val) {
403 DRV_LOG(ERR, "got %08X expected <= %" PRIx64,
408 case MLX5_RXP_ROF_ENTRY_IM:
412 * NOTE: All rules written to RXP must be carried out in
413 * triplets of: 2xData + 1xAddr.
414 * No optimisation is currently allowed in this
415 * sequence to perform less writes.
418 ret |= mlx5_devx_regex_register_write
419 (priv->cdev->ctx, id,
420 MLX5_RXP_RTRU_CSR_DATA_0, temp);
421 temp = (uint32_t)(val >> 32);
422 ret |= mlx5_devx_regex_register_write
423 (priv->cdev->ctx, id,
424 MLX5_RXP_RTRU_CSR_DATA_0 +
425 MLX5_RXP_CSR_WIDTH, temp);
427 ret |= mlx5_devx_regex_register_write
428 (priv->cdev->ctx, id,
429 MLX5_RXP_RTRU_CSR_ADDR, temp);
432 "Failed to copy instructions to RXP.");
436 case MLX5_RXP_ROF_ENTRY_EM:
439 for (i = 0; i < MLX5_RXP_NUM_LINES_PER_BLOCK; i++) {
440 ret = rxp_parse_line(line, &type,
445 if (i < (MLX5_RXP_NUM_LINES_PER_BLOCK - 1)) {
446 line = strtok(NULL, del);
451 if ((uint8_t *)((uint8_t *)
454 MLX5_RXP_INST_OFFSET))) >=
455 ((uint8_t *)((uint8_t *)
456 priv->db[id].ptr + MLX5_MAX_DB_SIZE))) {
457 DRV_LOG(ERR, "DB exceeded memory!");
461 * Rule address Offset to align with RXP
462 * external instruction offset.
464 rof_rule_addr = (rules[0].addr << MLX5_RXP_INST_OFFSET);
465 /* 32 byte instruction swap (sw work around)! */
466 tmp_write_swap[0] = le64toh(rules[4].value);
467 tmp_write_swap[1] = le64toh(rules[5].value);
468 tmp_write_swap[2] = le64toh(rules[6].value);
469 tmp_write_swap[3] = le64toh(rules[7].value);
470 /* Write only 4 of the 8 instructions. */
471 memcpy((uint8_t *)((uint8_t *)
472 priv->db[id].ptr + rof_rule_addr),
473 &tmp_write_swap, (sizeof(uint64_t) * 4));
474 /* Write 1st 4 rules of block after last 4. */
475 rof_rule_addr = (rules[4].addr << MLX5_RXP_INST_OFFSET);
476 tmp_write_swap[0] = le64toh(rules[0].value);
477 tmp_write_swap[1] = le64toh(rules[1].value);
478 tmp_write_swap[2] = le64toh(rules[2].value);
479 tmp_write_swap[3] = le64toh(rules[3].value);
480 memcpy((uint8_t *)((uint8_t *)
481 priv->db[id].ptr + rof_rule_addr),
482 &tmp_write_swap, (sizeof(uint64_t) * 4));
497 mlnx_resume_database(struct mlx5_regex_priv *priv, uint8_t id)
499 mlx5_devx_regex_database_resume(priv->cdev->ctx, id);
504 * Assign db memory for RXP programming.
507 mlnx_update_database(struct mlx5_regex_priv *priv, uint8_t id)
510 uint8_t db_free = MLX5_RXP_DB_NOT_ASSIGNED;
511 uint8_t eng_assigned = MLX5_RXP_DB_NOT_ASSIGNED;
513 /* Check which database rxp_eng is currently located if any? */
514 for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT);
516 if (priv->db[i].db_assigned_to_eng_num == id) {
522 * If private mode then, we can keep the same db ptr as RXP will be
523 * programming EM itself if necessary, however need to see if
526 if ((priv->prog_mode == MLX5_RXP_PRIVATE_PROG_MODE) &&
527 (eng_assigned != MLX5_RXP_DB_NOT_ASSIGNED))
529 /* Check for inactive db memory to use. */
530 for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT);
532 if (priv->db[i].active == true)
533 continue; /* Already in use, so skip db. */
534 /* Set this db to active now as free to use. */
535 priv->db[i].active = true;
536 /* Now unassign last db index in use by RXP Eng. */
537 if (eng_assigned != MLX5_RXP_DB_NOT_ASSIGNED) {
538 priv->db[eng_assigned].active = false;
539 priv->db[eng_assigned].db_assigned_to_eng_num =
540 MLX5_RXP_DB_NOT_ASSIGNED;
542 /* Set all DB memory to 0's before setting up DB. */
543 memset(priv->db[i].ptr, 0x00, MLX5_MAX_DB_SIZE);
545 /* Now reassign new db index with RXP Engine. */
546 priv->db[i].db_assigned_to_eng_num = id;
550 if (db_free == MLX5_RXP_DB_NOT_ASSIGNED)
556 * Program RXP instruction db to RXP engine/s.
559 program_rxp_rules(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,
564 struct ibv_context *ctx = priv->cdev->ctx;
566 ret = rxp_init_eng(priv, id);
569 /* Confirm the RXP is initialised. */
570 if (mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_STATUS, &val)) {
571 DRV_LOG(ERR, "Failed to read from RXP!");
574 if (!(val & MLX5_RXP_CSR_STATUS_INIT_DONE)) {
575 DRV_LOG(ERR, "RXP not initialised...");
578 ret = mlx5_devx_regex_register_read(ctx, id,
579 MLX5_RXP_RTRU_CSR_CTRL, &val);
581 DRV_LOG(ERR, "CSR read failed!");
584 val |= MLX5_RXP_RTRU_CSR_CTRL_GO;
585 ret = mlx5_devx_regex_register_write(ctx, id,
586 MLX5_RXP_RTRU_CSR_CTRL, val);
588 DRV_LOG(ERR, "Can't program rof file!");
591 ret = rxp_program_rof(priv, buf, len, id);
593 DRV_LOG(ERR, "Can't program rof file!");
597 ret = rxp_poll_csr_for_value
598 (ctx, &val, MLX5_RXP_RTRU_CSR_STATUS,
599 MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE,
600 MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE,
601 MLX5_RXP_POLL_CSR_FOR_VALUE_TIMEOUT, id);
603 DRV_LOG(ERR, "Rules update timeout: 0x%08X", val);
606 DRV_LOG(DEBUG, "Rules update took %d cycles", ret);
608 if (mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
610 DRV_LOG(ERR, "CSR read failed!");
613 val &= ~(MLX5_RXP_RTRU_CSR_CTRL_GO);
614 if (mlx5_devx_regex_register_write(ctx, id,
615 MLX5_RXP_RTRU_CSR_CTRL, val)) {
616 DRV_LOG(ERR, "CSR write failed!");
619 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &val);
622 val &= ~MLX5_RXP_CSR_CTRL_INIT;
623 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, val);
626 rxp_init_rtru(priv, id, MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_L1_L2);
628 ret = rxp_poll_csr_for_value(ctx, &val, MLX5_RXP_CSR_STATUS,
629 MLX5_RXP_CSR_STATUS_INIT_DONE,
630 MLX5_RXP_CSR_STATUS_INIT_DONE,
631 MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT,
634 DRV_LOG(ERR, "Device init failed!");
638 ret = mlnx_resume_database(priv, id);
640 DRV_LOG(ERR, "Failed to resume engine!");
649 rxp_init_eng(struct mlx5_regex_priv *priv, uint8_t id)
653 struct ibv_context *ctx = priv->cdev->ctx;
656 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);
659 if (ctrl & MLX5_RXP_CSR_CTRL_INIT) {
660 ctrl &= ~MLX5_RXP_CSR_CTRL_INIT;
661 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL,
666 ctrl |= MLX5_RXP_CSR_CTRL_INIT;
667 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
670 ctrl &= ~MLX5_RXP_CSR_CTRL_INIT;
671 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
675 ret = rxp_poll_csr_for_value(ctx, &ctrl, MLX5_RXP_CSR_STATUS,
676 MLX5_RXP_CSR_STATUS_INIT_DONE,
677 MLX5_RXP_CSR_STATUS_INIT_DONE,
678 MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT, id);
681 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);
684 ctrl &= ~MLX5_RXP_CSR_CTRL_INIT;
685 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL,
689 ret = rxp_init_rtru(priv, id,
690 MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2);
693 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CAPABILITY_5,
697 DRV_LOG(DEBUG, "max matches: %d, DDOS threshold: %d", reg >> 16,
699 if ((reg >> 16) >= priv->nb_max_matches)
700 ret = mlx5_devx_regex_register_write(ctx, id,
701 MLX5_RXP_CSR_MAX_MATCH,
702 priv->nb_max_matches);
704 ret = mlx5_devx_regex_register_write(ctx, id,
705 MLX5_RXP_CSR_MAX_MATCH,
707 ret |= mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_MAX_PREFIX,
709 ret |= mlx5_devx_regex_register_write(ctx, id,
710 MLX5_RXP_CSR_MAX_LATENCY, 0);
711 ret |= mlx5_devx_regex_register_write(ctx, id,
712 MLX5_RXP_CSR_MAX_PRI_THREAD, 0);
717 rxp_db_setup(struct mlx5_regex_priv *priv)
722 /* Setup database memories for both RXP engines + reprogram memory. */
723 for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT); i++) {
724 priv->db[i].ptr = rte_malloc("", MLX5_MAX_DB_SIZE, 1 << 21);
725 if (!priv->db[i].ptr) {
726 DRV_LOG(ERR, "Failed to alloc db memory!");
730 /* Register the memory. */
731 priv->db[i].umem.umem = mlx5_glue->devx_umem_reg
734 MLX5_MAX_DB_SIZE, 7);
735 if (!priv->db[i].umem.umem) {
736 DRV_LOG(ERR, "Failed to register memory!");
740 /* Ensure set all DB memory to 0's before setting up DB. */
741 memset(priv->db[i].ptr, 0x00, MLX5_MAX_DB_SIZE);
742 /* No data currently in database. */
744 priv->db[i].active = false;
745 priv->db[i].db_assigned_to_eng_num = MLX5_RXP_DB_NOT_ASSIGNED;
749 for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT); i++) {
750 if (priv->db[i].umem.umem)
751 mlx5_glue->devx_umem_dereg(priv->db[i].umem.umem);
752 rte_free(priv->db[i].ptr);
753 priv->db[i].ptr = NULL;
759 mlx5_regex_rules_db_import(struct rte_regexdev *dev,
760 const char *rule_db, uint32_t rule_db_len)
762 struct mlx5_regex_priv *priv = dev->data->dev_private;
763 struct mlx5_rxp_ctl_rules_pgm *rules = NULL;
768 if (priv->prog_mode == MLX5_RXP_MODE_NOT_DEFINED) {
769 DRV_LOG(ERR, "RXP programming mode not set!");
772 if (rule_db == NULL) {
773 DRV_LOG(ERR, "Database empty!");
776 if (rule_db_len == 0)
778 if (mlx5_devx_regex_register_read(priv->cdev->ctx, 0,
779 MLX5_RXP_CSR_BASE_ADDRESS, &ver)) {
780 DRV_LOG(ERR, "Failed to read Main CSRs Engine 0!");
783 /* Need to ensure RXP not busy before stop! */
784 for (id = 0; id < priv->nb_engines; id++) {
785 ret = rxp_stop_engine(priv->cdev->ctx, id);
787 DRV_LOG(ERR, "Can't stop engine.");
791 ret = program_rxp_rules(priv, rule_db, rule_db_len, id);
793 DRV_LOG(ERR, "Failed to program rxp rules.");
797 ret = rxp_start_engine(priv->cdev->ctx, id);
799 DRV_LOG(ERR, "Can't start engine.");
812 mlx5_regex_configure(struct rte_regexdev *dev,
813 const struct rte_regexdev_config *cfg)
815 struct mlx5_regex_priv *priv = dev->data->dev_private;
818 if (priv->prog_mode == MLX5_RXP_MODE_NOT_DEFINED)
820 priv->nb_queues = cfg->nb_queue_pairs;
821 dev->data->dev_conf.nb_queue_pairs = priv->nb_queues;
822 priv->qps = rte_zmalloc(NULL, sizeof(struct mlx5_regex_qp) *
824 if (!priv->nb_queues) {
825 DRV_LOG(ERR, "can't allocate qps memory");
829 priv->nb_max_matches = cfg->nb_max_matches;
830 /* Setup rxp db memories. */
831 if (rxp_db_setup(priv)) {
832 DRV_LOG(ERR, "Failed to setup RXP db memory");
836 if (cfg->rule_db != NULL) {
837 ret = mlx5_regex_rules_db_import(dev, cfg->rule_db,
840 DRV_LOG(ERR, "Failed to program rxp rules.");
842 goto configure_error;
845 DRV_LOG(DEBUG, "Regex config without rules programming!");