1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
7 #include <rte_malloc.h>
8 #include <rte_regexdev.h>
9 #include <rte_regexdev_core.h>
10 #include <rte_regexdev_driver.h>
13 #include <mlx5_glue.h>
14 #include <mlx5_devx_cmds.h>
16 #include <mlx5_common_os.h>
18 #include "mlx5_regex.h"
19 #include "mlx5_regex_utils.h"
20 #include "mlx5_rxp_csrs.h"
23 #define MLX5_REGEX_MAX_MATCHES MLX5_RXP_MAX_MATCHES
24 #define MLX5_REGEX_MAX_PAYLOAD_SIZE MLX5_RXP_MAX_JOB_LENGTH
25 #define MLX5_REGEX_MAX_RULES_PER_GROUP UINT32_MAX
26 #define MLX5_REGEX_MAX_GROUPS MLX5_RXP_MAX_SUBSETS
28 #define MLX5_REGEX_RXP_ROF2_LINE_LEN 34
30 /* Private Declarations */
32 rxp_poll_csr_for_value(struct ibv_context *ctx, uint32_t *value,
33 uint32_t address, uint32_t expected_value,
34 uint32_t expected_mask, uint32_t timeout_ms, uint8_t id);
36 mlnx_set_database(struct mlx5_regex_priv *priv, uint8_t id, uint8_t db_to_use);
38 mlnx_resume_database(struct mlx5_regex_priv *priv, uint8_t id);
40 mlnx_update_database(struct mlx5_regex_priv *priv, uint8_t id);
42 program_rxp_rules(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,
45 rxp_init_eng(struct mlx5_regex_priv *priv, uint8_t id);
47 rxp_db_setup(struct mlx5_regex_priv *priv);
49 rxp_dump_csrs(struct ibv_context *ctx, uint8_t id);
51 rxp_start_engine(struct ibv_context *ctx, uint8_t id);
53 rxp_stop_engine(struct ibv_context *ctx, uint8_t id);
55 static void __rte_unused
56 rxp_dump_csrs(struct ibv_context *ctx __rte_unused, uint8_t id __rte_unused)
61 for (i = 0; i < MLX5_RXP_CSR_NUM_ENTRIES; i++) {
62 if (mlx5_devx_regex_register_read(ctx, id,
63 (MLX5_RXP_CSR_WIDTH * i) +
64 MLX5_RXP_CSR_BASE_ADDRESS,
66 DRV_LOG(ERR, "Failed to read Main CSRs Engine %d!", id);
69 DRV_LOG(DEBUG, "RXP Main CSRs (Eng%d) register (%d): %08x",
73 for (i = 0; i < MLX5_RXP_CSR_NUM_ENTRIES; i++) {
74 if (mlx5_devx_regex_register_read(ctx, id,
75 (MLX5_RXP_CSR_WIDTH * i) +
76 MLX5_RXP_RTRU_CSR_BASE_ADDRESS,
78 DRV_LOG(ERR, "Failed to read RTRU CSRs Engine %d!", id);
81 DRV_LOG(DEBUG, "RXP RTRU CSRs (Eng%d) register (%d): %08x",
85 for (i = 0; i < MLX5_RXP_CSR_NUM_ENTRIES; i++) {
86 if (mlx5_devx_regex_register_read(ctx, id,
87 (MLX5_RXP_CSR_WIDTH * i) +
88 MLX5_RXP_STATS_CSR_BASE_ADDRESS,
90 DRV_LOG(ERR, "Failed to read STAT CSRs Engine %d!", id);
93 DRV_LOG(DEBUG, "RXP STAT CSRs (Eng%d) register (%d): %08x",
99 mlx5_regex_info_get(struct rte_regexdev *dev __rte_unused,
100 struct rte_regexdev_info *info)
102 info->max_matches = MLX5_REGEX_MAX_MATCHES;
103 info->max_payload_size = MLX5_REGEX_MAX_PAYLOAD_SIZE;
104 info->max_rules_per_group = MLX5_REGEX_MAX_RULES_PER_GROUP;
105 info->max_groups = MLX5_REGEX_MAX_GROUPS;
106 info->regexdev_capa = RTE_REGEXDEV_SUPP_PCRE_GREEDY_F |
107 RTE_REGEXDEV_CAPA_QUEUE_PAIR_OOS_F;
108 info->rule_flags = 0;
109 info->max_queue_pairs = UINT16_MAX;
114 rxp_poll_csr_for_value(struct ibv_context *ctx, uint32_t *value,
115 uint32_t address, uint32_t expected_value,
116 uint32_t expected_mask, uint32_t timeout_ms, uint8_t id)
122 for (i = 0; i < timeout_ms; i++) {
123 if (mlx5_devx_regex_register_read(ctx, id, address, value))
125 if ((*value & expected_mask) == expected_value) {
135 rxp_start_engine(struct ibv_context *ctx, uint8_t id)
140 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);
143 ctrl |= MLX5_RXP_CSR_CTRL_GO;
144 ctrl |= MLX5_RXP_CSR_CTRL_DISABLE_L2C;
145 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
150 rxp_stop_engine(struct ibv_context *ctx, uint8_t id)
155 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);
158 ctrl &= ~MLX5_RXP_CSR_CTRL_GO;
159 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
164 rxp_init_rtru(struct mlx5_regex_priv *priv, uint8_t id, uint32_t init_bits)
168 uint32_t expected_value;
169 uint32_t expected_mask;
170 struct ibv_context *ctx = priv->cdev->ctx;
173 /* Read the rtru ctrl CSR. */
174 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
178 /* Clear any previous init modes. */
179 ctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_MASK);
180 if (ctrl_value & MLX5_RXP_RTRU_CSR_CTRL_INIT) {
181 ctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT);
182 mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
185 /* Set the init_mode bits in the rtru ctrl CSR. */
186 ctrl_value |= init_bits;
187 mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
189 /* Need to sleep for a short period after pulsing the rtru init bit. */
191 /* Poll the rtru status CSR until all the init done bits are set. */
192 DRV_LOG(DEBUG, "waiting for RXP rule memory to complete init");
193 /* Set the init bit in the rtru ctrl CSR. */
194 ctrl_value |= MLX5_RXP_RTRU_CSR_CTRL_INIT;
195 mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
197 /* Clear the init bit in the rtru ctrl CSR */
198 ctrl_value &= ~MLX5_RXP_RTRU_CSR_CTRL_INIT;
199 mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
201 /* Check that the following bits are set in the RTRU_CSR. */
202 if (init_bits == MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_L1_L2) {
203 /* Must be incremental mode */
204 expected_value = MLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE;
206 expected_value = MLX5_RXP_RTRU_CSR_STATUS_IM_INIT_DONE |
207 MLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE;
210 expected_value |= MLX5_RXP_RTRU_CSR_STATUS_L2C_INIT_DONE;
213 expected_mask = expected_value;
214 ret = rxp_poll_csr_for_value(ctx, &poll_value,
215 MLX5_RXP_RTRU_CSR_STATUS,
216 expected_value, expected_mask,
217 MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT, id);
220 DRV_LOG(DEBUG, "rule memory initialise: 0x%08X", poll_value);
221 /* Clear the init bit in the rtru ctrl CSR */
222 ctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT);
223 mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
229 rxp_parse_line(char *line, uint32_t *type, uint32_t *address, uint64_t *value)
233 if (*line == '\0' || *line == '#')
235 *type = strtoul(line, &cur_pos, 10);
236 if (*cur_pos != ',' && *cur_pos != '\0')
238 *address = strtoul(cur_pos+1, &cur_pos, 16);
239 if (*cur_pos != ',' && *cur_pos != '\0')
241 *value = strtoul(cur_pos+1, &cur_pos, 16);
242 if (*cur_pos != ',' && *cur_pos != '\0')
248 rxp_get_reg_address(uint32_t address)
253 block = (address >> 16) & 0xFFFF;
255 reg = MLX5_RXP_CSR_BASE_ADDRESS;
257 reg = MLX5_RXP_RTRU_CSR_BASE_ADDRESS;
259 DRV_LOG(ERR, "Invalid ROF register 0x%08X!", address);
262 reg += (address & 0xFFFF) * MLX5_RXP_CSR_WIDTH;
266 #define MLX5_RXP_NUM_LINES_PER_BLOCK 8
269 rxp_program_rof(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,
272 static const char del[] = "\n\r";
284 uint32_t rof_rule_addr;
285 uint64_t tmp_write_swap[4];
286 struct mlx5_rxp_rof_entry rules[8];
291 tmp = rte_malloc("", len, 0);
294 memcpy(tmp, buf, len);
295 db_free = mlnx_update_database(priv, id);
297 DRV_LOG(ERR, "Failed to setup db memory!");
301 for (line = strtok(tmp, del), j = 0; line; line = strtok(NULL, del),
303 ret = rxp_parse_line(line, &type, &address, &val);
310 case MLX5_RXP_ROF_ENTRY_EQ:
311 if (skip == 0 && address == 0)
313 tmp_addr = rxp_get_reg_address(address);
314 if (tmp_addr == UINT32_MAX)
316 ret = mlx5_devx_regex_register_read(priv->cdev->ctx, id,
320 if (skip == -1 && address == 0) {
321 if (val == reg_val) {
325 } else if (skip == 0) {
326 if (val != reg_val) {
328 "got %08X expected == %" PRIx64,
334 case MLX5_RXP_ROF_ENTRY_GTE:
335 if (skip == 0 && address == 0)
337 tmp_addr = rxp_get_reg_address(address);
338 if (tmp_addr == UINT32_MAX)
340 ret = mlx5_devx_regex_register_read(priv->cdev->ctx, id,
344 if (skip == -1 && address == 0) {
345 if (reg_val >= val) {
349 } else if (skip == 0) {
352 "got %08X expected >= %" PRIx64,
358 case MLX5_RXP_ROF_ENTRY_LTE:
359 tmp_addr = rxp_get_reg_address(address);
360 if (tmp_addr == UINT32_MAX)
362 ret = mlx5_devx_regex_register_read(priv->cdev->ctx, id,
366 if (skip == 0 && address == 0 &&
367 last != MLX5_RXP_ROF_ENTRY_GTE) {
369 } else if (skip == 0 && address == 0 &&
370 last == MLX5_RXP_ROF_ENTRY_GTE) {
375 if (skip == -1 && address == 0) {
376 if (reg_val <= val) {
380 } else if (skip == 0) {
383 "got %08X expected <= %" PRIx64,
389 case MLX5_RXP_ROF_ENTRY_CHECKSUM:
391 case MLX5_RXP_ROF_ENTRY_CHECKSUM_EX_EM:
394 tmp_addr = rxp_get_reg_address(address);
395 if (tmp_addr == UINT32_MAX)
398 ret = mlx5_devx_regex_register_read(priv->cdev->ctx, id,
401 DRV_LOG(ERR, "RXP CSR read failed!");
404 if (reg_val != val) {
405 DRV_LOG(ERR, "got %08X expected <= %" PRIx64,
410 case MLX5_RXP_ROF_ENTRY_IM:
414 * NOTE: All rules written to RXP must be carried out in
415 * triplets of: 2xData + 1xAddr.
416 * No optimisation is currently allowed in this
417 * sequence to perform less writes.
420 ret |= mlx5_devx_regex_register_write
421 (priv->cdev->ctx, id,
422 MLX5_RXP_RTRU_CSR_DATA_0, temp);
423 temp = (uint32_t)(val >> 32);
424 ret |= mlx5_devx_regex_register_write
425 (priv->cdev->ctx, id,
426 MLX5_RXP_RTRU_CSR_DATA_0 +
427 MLX5_RXP_CSR_WIDTH, temp);
429 ret |= mlx5_devx_regex_register_write
430 (priv->cdev->ctx, id,
431 MLX5_RXP_RTRU_CSR_ADDR, temp);
434 "Failed to copy instructions to RXP.");
438 case MLX5_RXP_ROF_ENTRY_EM:
441 for (i = 0; i < MLX5_RXP_NUM_LINES_PER_BLOCK; i++) {
442 ret = rxp_parse_line(line, &type,
447 if (i < (MLX5_RXP_NUM_LINES_PER_BLOCK - 1)) {
448 line = strtok(NULL, del);
453 if ((uint8_t *)((uint8_t *)
456 MLX5_RXP_INST_OFFSET))) >=
457 ((uint8_t *)((uint8_t *)
458 priv->db[id].ptr + MLX5_MAX_DB_SIZE))) {
459 DRV_LOG(ERR, "DB exceeded memory!");
463 * Rule address Offset to align with RXP
464 * external instruction offset.
466 rof_rule_addr = (rules[0].addr << MLX5_RXP_INST_OFFSET);
467 /* 32 byte instruction swap (sw work around)! */
468 tmp_write_swap[0] = le64toh(rules[4].value);
469 tmp_write_swap[1] = le64toh(rules[5].value);
470 tmp_write_swap[2] = le64toh(rules[6].value);
471 tmp_write_swap[3] = le64toh(rules[7].value);
472 /* Write only 4 of the 8 instructions. */
473 memcpy((uint8_t *)((uint8_t *)
474 priv->db[id].ptr + rof_rule_addr),
475 &tmp_write_swap, (sizeof(uint64_t) * 4));
476 /* Write 1st 4 rules of block after last 4. */
477 rof_rule_addr = (rules[4].addr << MLX5_RXP_INST_OFFSET);
478 tmp_write_swap[0] = le64toh(rules[0].value);
479 tmp_write_swap[1] = le64toh(rules[1].value);
480 tmp_write_swap[2] = le64toh(rules[2].value);
481 tmp_write_swap[3] = le64toh(rules[3].value);
482 memcpy((uint8_t *)((uint8_t *)
483 priv->db[id].ptr + rof_rule_addr),
484 &tmp_write_swap, (sizeof(uint64_t) * 4));
491 ret = mlnx_set_database(priv, id, db_free);
493 DRV_LOG(ERR, "Failed to register db memory!");
504 mlnx_set_database(struct mlx5_regex_priv *priv, uint8_t id, uint8_t db_to_use)
509 ret = mlx5_devx_regex_database_stop(priv->cdev->ctx, id);
511 DRV_LOG(ERR, "stop engine failed!");
514 umem_id = mlx5_os_get_umem_id(priv->db[db_to_use].umem.umem);
515 ret = mlx5_devx_regex_database_program(priv->cdev->ctx, id, umem_id, 0);
517 DRV_LOG(ERR, "program db failed!");
524 mlnx_resume_database(struct mlx5_regex_priv *priv, uint8_t id)
526 mlx5_devx_regex_database_resume(priv->cdev->ctx, id);
531 * Assign db memory for RXP programming.
534 mlnx_update_database(struct mlx5_regex_priv *priv, uint8_t id)
537 uint8_t db_free = MLX5_RXP_DB_NOT_ASSIGNED;
538 uint8_t eng_assigned = MLX5_RXP_DB_NOT_ASSIGNED;
540 /* Check which database rxp_eng is currently located if any? */
541 for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT);
543 if (priv->db[i].db_assigned_to_eng_num == id) {
549 * If private mode then, we can keep the same db ptr as RXP will be
550 * programming EM itself if necessary, however need to see if
553 if ((priv->prog_mode == MLX5_RXP_PRIVATE_PROG_MODE) &&
554 (eng_assigned != MLX5_RXP_DB_NOT_ASSIGNED))
556 /* Check for inactive db memory to use. */
557 for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT);
559 if (priv->db[i].active == true)
560 continue; /* Already in use, so skip db. */
561 /* Set this db to active now as free to use. */
562 priv->db[i].active = true;
563 /* Now unassign last db index in use by RXP Eng. */
564 if (eng_assigned != MLX5_RXP_DB_NOT_ASSIGNED) {
565 priv->db[eng_assigned].active = false;
566 priv->db[eng_assigned].db_assigned_to_eng_num =
567 MLX5_RXP_DB_NOT_ASSIGNED;
569 /* Set all DB memory to 0's before setting up DB. */
570 memset(priv->db[i].ptr, 0x00, MLX5_MAX_DB_SIZE);
572 /* Now reassign new db index with RXP Engine. */
573 priv->db[i].db_assigned_to_eng_num = id;
577 if (db_free == MLX5_RXP_DB_NOT_ASSIGNED)
583 * Program RXP instruction db to RXP engine/s.
586 program_rxp_rules(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,
591 struct ibv_context *ctx = priv->cdev->ctx;
593 ret = rxp_init_eng(priv, id);
596 /* Confirm the RXP is initialised. */
597 if (mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_STATUS, &val)) {
598 DRV_LOG(ERR, "Failed to read from RXP!");
601 if (!(val & MLX5_RXP_CSR_STATUS_INIT_DONE)) {
602 DRV_LOG(ERR, "RXP not initialised...");
605 ret = mlx5_devx_regex_register_read(ctx, id,
606 MLX5_RXP_RTRU_CSR_CTRL, &val);
608 DRV_LOG(ERR, "CSR read failed!");
611 val |= MLX5_RXP_RTRU_CSR_CTRL_GO;
612 ret = mlx5_devx_regex_register_write(ctx, id,
613 MLX5_RXP_RTRU_CSR_CTRL, val);
615 DRV_LOG(ERR, "Can't program rof file!");
618 ret = rxp_program_rof(priv, buf, len, id);
620 DRV_LOG(ERR, "Can't program rof file!");
624 ret = rxp_poll_csr_for_value
625 (ctx, &val, MLX5_RXP_RTRU_CSR_STATUS,
626 MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE,
627 MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE,
628 MLX5_RXP_POLL_CSR_FOR_VALUE_TIMEOUT, id);
630 DRV_LOG(ERR, "Rules update timeout: 0x%08X", val);
633 DRV_LOG(DEBUG, "Rules update took %d cycles", ret);
635 if (mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
637 DRV_LOG(ERR, "CSR read failed!");
640 val &= ~(MLX5_RXP_RTRU_CSR_CTRL_GO);
641 if (mlx5_devx_regex_register_write(ctx, id,
642 MLX5_RXP_RTRU_CSR_CTRL, val)) {
643 DRV_LOG(ERR, "CSR write failed!");
646 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &val);
649 val &= ~MLX5_RXP_CSR_CTRL_INIT;
650 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, val);
653 rxp_init_rtru(priv, id, MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_L1_L2);
655 ret = rxp_poll_csr_for_value(ctx, &val, MLX5_RXP_CSR_STATUS,
656 MLX5_RXP_CSR_STATUS_INIT_DONE,
657 MLX5_RXP_CSR_STATUS_INIT_DONE,
658 MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT,
661 DRV_LOG(ERR, "Device init failed!");
665 ret = mlnx_resume_database(priv, id);
667 DRV_LOG(ERR, "Failed to resume engine!");
676 rxp_init_eng(struct mlx5_regex_priv *priv, uint8_t id)
680 struct ibv_context *ctx = priv->cdev->ctx;
683 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);
686 if (ctrl & MLX5_RXP_CSR_CTRL_INIT) {
687 ctrl &= ~MLX5_RXP_CSR_CTRL_INIT;
688 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL,
693 ctrl |= MLX5_RXP_CSR_CTRL_INIT;
694 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
697 ctrl &= ~MLX5_RXP_CSR_CTRL_INIT;
698 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
702 ret = rxp_poll_csr_for_value(ctx, &ctrl, MLX5_RXP_CSR_STATUS,
703 MLX5_RXP_CSR_STATUS_INIT_DONE,
704 MLX5_RXP_CSR_STATUS_INIT_DONE,
705 MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT, id);
708 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);
711 ctrl &= ~MLX5_RXP_CSR_CTRL_INIT;
712 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL,
716 ret = rxp_init_rtru(priv, id,
717 MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2);
720 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CAPABILITY_5,
724 DRV_LOG(DEBUG, "max matches: %d, DDOS threshold: %d", reg >> 16,
726 if ((reg >> 16) >= priv->nb_max_matches)
727 ret = mlx5_devx_regex_register_write(ctx, id,
728 MLX5_RXP_CSR_MAX_MATCH,
729 priv->nb_max_matches);
731 ret = mlx5_devx_regex_register_write(ctx, id,
732 MLX5_RXP_CSR_MAX_MATCH,
734 ret |= mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_MAX_PREFIX,
736 ret |= mlx5_devx_regex_register_write(ctx, id,
737 MLX5_RXP_CSR_MAX_LATENCY, 0);
738 ret |= mlx5_devx_regex_register_write(ctx, id,
739 MLX5_RXP_CSR_MAX_PRI_THREAD, 0);
744 rxp_db_setup(struct mlx5_regex_priv *priv)
749 /* Setup database memories for both RXP engines + reprogram memory. */
750 for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT); i++) {
751 priv->db[i].ptr = rte_malloc("", MLX5_MAX_DB_SIZE, 1 << 21);
752 if (!priv->db[i].ptr) {
753 DRV_LOG(ERR, "Failed to alloc db memory!");
757 /* Register the memory. */
758 priv->db[i].umem.umem = mlx5_glue->devx_umem_reg
761 MLX5_MAX_DB_SIZE, 7);
762 if (!priv->db[i].umem.umem) {
763 DRV_LOG(ERR, "Failed to register memory!");
767 /* Ensure set all DB memory to 0's before setting up DB. */
768 memset(priv->db[i].ptr, 0x00, MLX5_MAX_DB_SIZE);
769 /* No data currently in database. */
771 priv->db[i].active = false;
772 priv->db[i].db_assigned_to_eng_num = MLX5_RXP_DB_NOT_ASSIGNED;
776 for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT); i++) {
777 if (priv->db[i].umem.umem)
778 mlx5_glue->devx_umem_dereg(priv->db[i].umem.umem);
779 rte_free(priv->db[i].ptr);
780 priv->db[i].ptr = NULL;
786 mlx5_regex_rules_db_import(struct rte_regexdev *dev,
787 const char *rule_db, uint32_t rule_db_len)
789 struct mlx5_regex_priv *priv = dev->data->dev_private;
790 struct mlx5_rxp_ctl_rules_pgm *rules = NULL;
795 if (priv->prog_mode == MLX5_RXP_MODE_NOT_DEFINED) {
796 DRV_LOG(ERR, "RXP programming mode not set!");
799 if (rule_db == NULL) {
800 DRV_LOG(ERR, "Database empty!");
803 if (rule_db_len == 0)
805 if (mlx5_devx_regex_register_read(priv->cdev->ctx, 0,
806 MLX5_RXP_CSR_BASE_ADDRESS, &ver)) {
807 DRV_LOG(ERR, "Failed to read Main CSRs Engine 0!");
810 /* Need to ensure RXP not busy before stop! */
811 for (id = 0; id < priv->nb_engines; id++) {
812 ret = rxp_stop_engine(priv->cdev->ctx, id);
814 DRV_LOG(ERR, "Can't stop engine.");
818 ret = program_rxp_rules(priv, rule_db, rule_db_len, id);
820 DRV_LOG(ERR, "Failed to program rxp rules.");
824 ret = rxp_start_engine(priv->cdev->ctx, id);
826 DRV_LOG(ERR, "Can't start engine.");
839 mlx5_regex_configure(struct rte_regexdev *dev,
840 const struct rte_regexdev_config *cfg)
842 struct mlx5_regex_priv *priv = dev->data->dev_private;
845 if (priv->prog_mode == MLX5_RXP_MODE_NOT_DEFINED)
847 priv->nb_queues = cfg->nb_queue_pairs;
848 dev->data->dev_conf.nb_queue_pairs = priv->nb_queues;
849 priv->qps = rte_zmalloc(NULL, sizeof(struct mlx5_regex_qp) *
851 if (!priv->nb_queues) {
852 DRV_LOG(ERR, "can't allocate qps memory");
856 priv->nb_max_matches = cfg->nb_max_matches;
857 /* Setup rxp db memories. */
858 if (rxp_db_setup(priv)) {
859 DRV_LOG(ERR, "Failed to setup RXP db memory");
863 if (cfg->rule_db != NULL) {
864 ret = mlx5_regex_rules_db_import(dev, cfg->rule_db,
867 DRV_LOG(ERR, "Failed to program rxp rules.");
869 goto configure_error;
872 DRV_LOG(DEBUG, "Regex config without rules programming!");