1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
7 #include <rte_malloc.h>
8 #include <rte_regexdev.h>
9 #include <rte_regexdev_core.h>
10 #include <rte_regexdev_driver.h>
12 #include <mlx5_glue.h>
13 #include <mlx5_devx_cmds.h>
15 #include <mlx5_common_os.h>
17 #include "mlx5_regex.h"
18 #include "mlx5_regex_utils.h"
19 #include "mlx5_rxp_csrs.h"
22 #define MLX5_REGEX_MAX_MATCHES MLX5_RXP_MAX_MATCHES
23 #define MLX5_REGEX_MAX_PAYLOAD_SIZE MLX5_RXP_MAX_JOB_LENGTH
24 #define MLX5_REGEX_MAX_RULES_PER_GROUP UINT32_MAX
25 #define MLX5_REGEX_MAX_GROUPS MLX5_RXP_MAX_SUBSETS
27 /* Private Declarations */
29 rxp_poll_csr_for_value(struct ibv_context *ctx, uint32_t *value,
30 uint32_t address, uint32_t expected_value,
31 uint32_t expected_mask, uint32_t timeout_ms, uint8_t id);
33 mlnx_set_database(struct mlx5_regex_priv *priv, uint8_t id, uint8_t db_to_use);
35 mlnx_resume_database(struct mlx5_regex_priv *priv, uint8_t id);
37 mlnx_update_database(struct mlx5_regex_priv *priv, uint8_t id);
39 program_rxp_rules(struct mlx5_regex_priv *priv,
40 struct mlx5_rxp_ctl_rules_pgm *rules, uint8_t id);
42 rxp_init_eng(struct mlx5_regex_priv *priv, uint8_t id);
44 write_private_rules(struct mlx5_regex_priv *priv,
45 struct mlx5_rxp_ctl_rules_pgm *rules,
48 write_shared_rules(struct mlx5_regex_priv *priv,
49 struct mlx5_rxp_ctl_rules_pgm *rules, uint32_t count,
50 uint8_t db_to_program);
52 rxp_db_setup(struct mlx5_regex_priv *priv);
54 rxp_dump_csrs(struct ibv_context *ctx, uint8_t id);
56 rxp_write_rules_via_cp(struct ibv_context *ctx,
57 struct mlx5_rxp_rof_entry *rules,
58 int count, uint8_t id);
60 rxp_flush_rules(struct ibv_context *ctx, struct mlx5_rxp_rof_entry *rules,
61 int count, uint8_t id);
63 rxp_start_engine(struct ibv_context *ctx, uint8_t id);
65 rxp_stop_engine(struct ibv_context *ctx, uint8_t id);
67 static void __rte_unused
68 rxp_dump_csrs(struct ibv_context *ctx __rte_unused, uint8_t id __rte_unused)
73 for (i = 0; i < MLX5_RXP_CSR_NUM_ENTRIES; i++) {
74 if (mlx5_devx_regex_register_read(ctx, id,
75 (MLX5_RXP_CSR_WIDTH * i) +
76 MLX5_RXP_CSR_BASE_ADDRESS,
78 DRV_LOG(ERR, "Failed to read Main CSRs Engine %d!", id);
81 DRV_LOG(DEBUG, "RXP Main CSRs (Eng%d) register (%d): %08x",
85 for (i = 0; i < MLX5_RXP_CSR_NUM_ENTRIES; i++) {
86 if (mlx5_devx_regex_register_read(ctx, id,
87 (MLX5_RXP_CSR_WIDTH * i) +
88 MLX5_RXP_RTRU_CSR_BASE_ADDRESS,
90 DRV_LOG(ERR, "Failed to read RTRU CSRs Engine %d!", id);
93 DRV_LOG(DEBUG, "RXP RTRU CSRs (Eng%d) register (%d): %08x",
97 for (i = 0; i < MLX5_RXP_CSR_NUM_ENTRIES; i++) {
98 if (mlx5_devx_regex_register_read(ctx, id,
99 (MLX5_RXP_CSR_WIDTH * i) +
100 MLX5_RXP_STATS_CSR_BASE_ADDRESS,
102 DRV_LOG(ERR, "Failed to read STAT CSRs Engine %d!", id);
105 DRV_LOG(DEBUG, "RXP STAT CSRs (Eng%d) register (%d): %08x",
111 mlx5_regex_info_get(struct rte_regexdev *dev __rte_unused,
112 struct rte_regexdev_info *info)
114 info->max_matches = MLX5_REGEX_MAX_MATCHES;
115 info->max_payload_size = MLX5_REGEX_MAX_PAYLOAD_SIZE;
116 info->max_rules_per_group = MLX5_REGEX_MAX_RULES_PER_GROUP;
117 info->max_groups = MLX5_REGEX_MAX_GROUPS;
118 info->max_queue_pairs = 1;
119 info->regexdev_capa = RTE_REGEXDEV_SUPP_PCRE_GREEDY_F;
120 info->rule_flags = 0;
121 info->max_queue_pairs = 10;
126 * Actual writing of RXP instructions to RXP via CSRs.
129 rxp_write_rules_via_cp(struct ibv_context *ctx,
130 struct mlx5_rxp_rof_entry *rules,
131 int count, uint8_t id)
136 for (i = 0; i < count; i++) {
137 tmp = (uint32_t)rules[i].value;
138 ret |= mlx5_devx_regex_register_write(ctx, id,
139 MLX5_RXP_RTRU_CSR_DATA_0,
141 tmp = (uint32_t)(rules[i].value >> 32);
142 ret |= mlx5_devx_regex_register_write(ctx, id,
143 MLX5_RXP_RTRU_CSR_DATA_0 +
144 MLX5_RXP_CSR_WIDTH, tmp);
146 ret |= mlx5_devx_regex_register_write(ctx, id,
147 MLX5_RXP_RTRU_CSR_ADDR,
150 DRV_LOG(ERR, "Failed to copy instructions to RXP.");
154 DRV_LOG(DEBUG, "Written %d instructions", count);
159 rxp_flush_rules(struct ibv_context *ctx, struct mlx5_rxp_rof_entry *rules,
160 int count, uint8_t id)
162 uint32_t val, fifo_depth;
165 ret = rxp_write_rules_via_cp(ctx, rules, count, id);
167 DRV_LOG(ERR, "Failed to write rules via CSRs.");
170 ret = mlx5_devx_regex_register_read(ctx, id,
171 MLX5_RXP_RTRU_CSR_CAPABILITY,
174 DRV_LOG(ERR, "CSR read failed!");
177 ret = rxp_poll_csr_for_value(ctx, &val, MLX5_RXP_RTRU_CSR_FIFO_STAT,
179 MLX5_RXP_POLL_CSR_FOR_VALUE_TIMEOUT, id);
181 DRV_LOG(ERR, "Rules not rx by RXP: credit: %d, depth: %d", val,
185 DRV_LOG(DEBUG, "RTRU FIFO depth: 0x%x", fifo_depth);
186 DRV_LOG(DEBUG, "Rules flush took %d cycles.", ret);
187 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
190 DRV_LOG(ERR, "CSR read failed!");
193 val |= MLX5_RXP_RTRU_CSR_CTRL_GO;
194 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
196 ret = rxp_poll_csr_for_value(ctx, &val, MLX5_RXP_RTRU_CSR_STATUS,
197 MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE,
198 MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE,
199 MLX5_RXP_POLL_CSR_FOR_VALUE_TIMEOUT, id);
201 DRV_LOG(ERR, "Rules update timeout: 0x%08X", val);
204 DRV_LOG(DEBUG, "Rules update took %d cycles", ret);
205 if (mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
207 DRV_LOG(ERR, "CSR read failed!");
210 val &= ~(MLX5_RXP_RTRU_CSR_CTRL_GO);
211 if (mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
213 DRV_LOG(ERR, "CSR write write failed!");
217 DRV_LOG(DEBUG, "RXP Flush rules finished.");
222 rxp_poll_csr_for_value(struct ibv_context *ctx, uint32_t *value,
223 uint32_t address, uint32_t expected_value,
224 uint32_t expected_mask, uint32_t timeout_ms, uint8_t id)
230 for (i = 0; i < timeout_ms; i++) {
231 if (mlx5_devx_regex_register_read(ctx, id, address, value))
233 if ((*value & expected_mask) == expected_value) {
243 rxp_start_engine(struct ibv_context *ctx, uint8_t id)
248 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);
251 ctrl |= MLX5_RXP_CSR_CTRL_GO;
252 ctrl |= MLX5_RXP_CSR_CTRL_DISABLE_L2C;
253 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
258 rxp_stop_engine(struct ibv_context *ctx, uint8_t id)
263 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);
266 ctrl &= ~MLX5_RXP_CSR_CTRL_GO;
267 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
272 rxp_init_rtru(struct ibv_context *ctx, uint8_t id, uint32_t init_bits)
276 uint32_t expected_value;
277 uint32_t expected_mask;
280 /* Read the rtru ctrl CSR. */
281 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
285 /* Clear any previous init modes. */
286 ctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_MASK);
287 if (ctrl_value & MLX5_RXP_RTRU_CSR_CTRL_INIT) {
288 ctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT);
289 mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
292 /* Set the init_mode bits in the rtru ctrl CSR. */
293 ctrl_value |= init_bits;
294 mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
296 /* Need to sleep for a short period after pulsing the rtru init bit. */
298 /* Poll the rtru status CSR until all the init done bits are set. */
299 DRV_LOG(DEBUG, "waiting for RXP rule memory to complete init");
300 /* Set the init bit in the rtru ctrl CSR. */
301 ctrl_value |= MLX5_RXP_RTRU_CSR_CTRL_INIT;
302 mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
304 /* Clear the init bit in the rtru ctrl CSR */
305 ctrl_value &= ~MLX5_RXP_RTRU_CSR_CTRL_INIT;
306 mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
308 /* Check that the following bits are set in the RTRU_CSR. */
309 if (init_bits == MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_L1_L2) {
310 /* Must be incremental mode */
311 expected_value = MLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE |
312 MLX5_RXP_RTRU_CSR_STATUS_L2C_INIT_DONE;
314 expected_value = MLX5_RXP_RTRU_CSR_STATUS_IM_INIT_DONE |
315 MLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE |
316 MLX5_RXP_RTRU_CSR_STATUS_L2C_INIT_DONE;
318 expected_mask = expected_value;
319 ret = rxp_poll_csr_for_value(ctx, &poll_value,
320 MLX5_RXP_RTRU_CSR_STATUS,
321 expected_value, expected_mask,
322 MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT, id);
325 DRV_LOG(DEBUG, "rule memory initialise: 0x%08X", poll_value);
326 /* Clear the init bit in the rtru ctrl CSR */
327 ctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT);
328 mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
334 rxp_parse_rof(const char *buf, uint32_t len,
335 struct mlx5_rxp_ctl_rules_pgm **rules)
337 static const char del[] = "\n\r";
343 struct mlx5_rxp_rof_entry *curentry;
345 tmp = rte_malloc("", len, 0);
348 memcpy(tmp, buf, len);
349 line = strtok(tmp, del);
351 if (line[0] != '#' && line[0] != '\0')
353 line = strtok(NULL, del);
355 *rules = rte_malloc("", lines * sizeof(*curentry) + sizeof(**rules), 0);
360 memset(*rules, 0, lines * sizeof(curentry) + sizeof(**rules));
361 curentry = (*rules)->rules;
362 (*rules)->hdr.cmd = MLX5_RXP_CTL_RULES_PGM;
364 memcpy(tmp, buf, len);
365 line = strtok(tmp, del);
367 if (line[0] == '#' || line[0] == '\0') {
368 line = strtok(NULL, del);
371 curentry->type = strtoul(line, &cur_pos, 10);
372 if (cur_pos == line || cur_pos[0] != ',')
375 curentry->addr = strtoul(cur_pos, &cur_pos, 16);
376 if (cur_pos[0] != ',')
379 curentry->value = strtoull(cur_pos, &cur_pos, 16);
380 if (cur_pos[0] != '\0' && cur_pos[0] != '\n')
386 line = strtok(NULL, del);
388 (*rules)->count = entries;
389 (*rules)->hdr.len = entries * sizeof(*curentry) + sizeof(**rules);
400 mlnx_set_database(struct mlx5_regex_priv *priv, uint8_t id, uint8_t db_to_use)
405 ret = mlx5_devx_regex_database_stop(priv->ctx, id);
407 DRV_LOG(ERR, "stop engine failed!");
410 umem_id = mlx5_os_get_umem_id(priv->db[db_to_use].umem.umem);
411 ret = mlx5_devx_regex_database_program(priv->ctx, id, umem_id, 0);
413 DRV_LOG(ERR, "program db failed!");
420 mlnx_resume_database(struct mlx5_regex_priv *priv, uint8_t id)
422 mlx5_devx_regex_database_resume(priv->ctx, id);
427 * Assign db memory for RXP programming.
430 mlnx_update_database(struct mlx5_regex_priv *priv, uint8_t id)
433 uint8_t db_free = MLX5_RXP_DB_NOT_ASSIGNED;
434 uint8_t eng_assigned = MLX5_RXP_DB_NOT_ASSIGNED;
436 /* Check which database rxp_eng is currently located if any? */
437 for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT);
439 if (priv->db[i].db_assigned_to_eng_num == id) {
445 * If private mode then, we can keep the same db ptr as RXP will be
446 * programming EM itself if necessary, however need to see if
449 if ((priv->prog_mode == MLX5_RXP_PRIVATE_PROG_MODE) &&
450 (eng_assigned != MLX5_RXP_DB_NOT_ASSIGNED))
452 /* Check for inactive db memory to use. */
453 for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT);
455 if (priv->db[i].active == true)
456 continue; /* Already in use, so skip db. */
457 /* Set this db to active now as free to use. */
458 priv->db[i].active = true;
459 /* Now unassign last db index in use by RXP Eng. */
460 if (eng_assigned != MLX5_RXP_DB_NOT_ASSIGNED) {
461 priv->db[eng_assigned].active = false;
462 priv->db[eng_assigned].db_assigned_to_eng_num =
463 MLX5_RXP_DB_NOT_ASSIGNED;
465 /* Set all DB memory to 0's before setting up DB. */
466 memset(priv->db[i].ptr, 0x00, MLX5_MAX_DB_SIZE);
468 /* Now reassign new db index with RXP Engine. */
469 priv->db[i].db_assigned_to_eng_num = id;
473 if (db_free == MLX5_RXP_DB_NOT_ASSIGNED)
479 * Program RXP instruction db to RXP engine/s.
482 program_rxp_rules(struct mlx5_regex_priv *priv,
483 struct mlx5_rxp_ctl_rules_pgm *rules, uint8_t id)
488 rule_cnt = rules->count;
489 db_free = mlnx_update_database(priv, id);
491 DRV_LOG(ERR, "Failed to setup db memory!");
494 if (priv->prog_mode == MLX5_RXP_PRIVATE_PROG_MODE) {
495 /* Register early to ensure RXP writes to EM use valid addr. */
496 ret = mlnx_set_database(priv, id, db_free);
498 DRV_LOG(ERR, "Failed to register db memory!");
502 ret = write_private_rules(priv, rules, id);
504 DRV_LOG(ERR, "Failed to write rules!");
507 if (priv->prog_mode == MLX5_RXP_SHARED_PROG_MODE) {
508 /* Write external rules directly to EM. */
509 rules->count = rule_cnt;
510 /* Now write external instructions to EM. */
511 ret = write_shared_rules(priv, rules, rules->hdr.len, db_free);
513 DRV_LOG(ERR, "Failed to write EM rules!");
516 ret = mlnx_set_database(priv, id, db_free);
518 DRV_LOG(ERR, "Failed to register db memory!");
522 ret = mlnx_resume_database(priv, id);
524 DRV_LOG(ERR, "Failed to resume engine!");
527 DRV_LOG(DEBUG, "Programmed RXP Engine %d\n", id);
528 rules->count = rule_cnt;
533 rxp_init_eng(struct mlx5_regex_priv *priv, uint8_t id)
537 struct ibv_context *ctx = priv->ctx;
540 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);
543 if (ctrl & MLX5_RXP_CSR_CTRL_INIT) {
544 ctrl &= ~MLX5_RXP_CSR_CTRL_INIT;
545 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL,
550 ctrl |= MLX5_RXP_CSR_CTRL_INIT;
551 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
554 ctrl &= ~MLX5_RXP_CSR_CTRL_INIT;
555 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
557 ret = rxp_poll_csr_for_value(ctx, &ctrl, MLX5_RXP_CSR_STATUS,
558 MLX5_RXP_CSR_STATUS_INIT_DONE,
559 MLX5_RXP_CSR_STATUS_INIT_DONE,
560 MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT, id);
563 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);
566 ctrl &= ~MLX5_RXP_CSR_CTRL_INIT;
567 ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL,
571 ret = rxp_init_rtru(ctx, id, MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2);
574 ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CAPABILITY_5,
578 DRV_LOG(DEBUG, "max matches: %d, DDOS threshold: %d", reg >> 16,
580 if ((reg >> 16) >= priv->nb_max_matches)
581 ret = mlx5_devx_regex_register_write(ctx, id,
582 MLX5_RXP_CSR_MAX_MATCH,
583 priv->nb_max_matches);
585 ret = mlx5_devx_regex_register_write(ctx, id,
586 MLX5_RXP_CSR_MAX_MATCH,
588 ret |= mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_MAX_PREFIX,
590 ret |= mlx5_devx_regex_register_write(ctx, id,
591 MLX5_RXP_CSR_MAX_LATENCY, 0);
592 ret |= mlx5_devx_regex_register_write(ctx, id,
593 MLX5_RXP_CSR_MAX_PRI_THREAD, 0);
598 write_private_rules(struct mlx5_regex_priv *priv,
599 struct mlx5_rxp_ctl_rules_pgm *rules,
602 unsigned int pending;
603 uint32_t block, reg, val, rule_cnt, rule_offset, rtru_max_num_entries;
606 if (priv->prog_mode == MLX5_RXP_MODE_NOT_DEFINED)
608 if (rules->hdr.len == 0 || rules->hdr.cmd < MLX5_RXP_CTL_RULES_PGM ||
609 rules->hdr.cmd > MLX5_RXP_CTL_RULES_PGM_INCR)
611 /* For a non-incremental rules program, re-init the RXP. */
612 if (rules->hdr.cmd == MLX5_RXP_CTL_RULES_PGM) {
613 ret = rxp_init_eng(priv, id);
616 } else if (rules->hdr.cmd == MLX5_RXP_CTL_RULES_PGM_INCR) {
617 /* Flush RXP L1 and L2 cache by using MODE_L1_L2. */
618 ret = rxp_init_rtru(priv->ctx, id,
619 MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_L1_L2);
623 if (rules->count == 0)
625 /* Confirm the RXP is initialised. */
626 if (mlx5_devx_regex_register_read(priv->ctx, id,
627 MLX5_RXP_CSR_STATUS, &val)) {
628 DRV_LOG(ERR, "Failed to read from RXP!");
631 if (!(val & MLX5_RXP_CSR_STATUS_INIT_DONE)) {
632 DRV_LOG(ERR, "RXP not initialised...");
635 /* Get the RTRU maximum number of entries allowed. */
636 if (mlx5_devx_regex_register_read(priv->ctx, id,
637 MLX5_RXP_RTRU_CSR_CAPABILITY, &rtru_max_num_entries)) {
638 DRV_LOG(ERR, "Failed to read RTRU capability!");
641 rtru_max_num_entries = (rtru_max_num_entries & 0x00FF);
644 while (rules->count > 0) {
645 if ((rules->rules[rule_cnt].type == MLX5_RXP_ROF_ENTRY_INST) ||
646 (rules->rules[rule_cnt].type == MLX5_RXP_ROF_ENTRY_IM) ||
647 (rules->rules[rule_cnt].type == MLX5_RXP_ROF_ENTRY_EM)) {
648 if ((rules->rules[rule_cnt].type ==
649 MLX5_RXP_ROF_ENTRY_EM) &&
650 (priv->prog_mode == MLX5_RXP_SHARED_PROG_MODE)) {
651 /* Skip EM rules programming. */
653 /* Flush any rules that are pending. */
654 rule_offset = (rule_cnt - pending);
655 ret = rxp_flush_rules(priv->ctx,
656 &rules->rules[rule_offset],
659 DRV_LOG(ERR, "Flushing rules.");
669 * If parsing the last rule, or if reached the
670 * maximum number of rules for this batch, then
671 * flush the rules batch to the RXP.
673 if ((rules->count == 1) ||
674 (pending == rtru_max_num_entries)) {
675 rule_offset = (rule_cnt - pending);
676 ret = rxp_flush_rules(priv->ctx,
677 &rules->rules[rule_offset],
680 DRV_LOG(ERR, "Flushing rules.");
686 } else if ((rules->rules[rule_cnt].type ==
687 MLX5_RXP_ROF_ENTRY_EQ) ||
688 (rules->rules[rule_cnt].type ==
689 MLX5_RXP_ROF_ENTRY_GTE) ||
690 (rules->rules[rule_cnt].type ==
691 MLX5_RXP_ROF_ENTRY_LTE) ||
692 (rules->rules[rule_cnt].type ==
693 MLX5_RXP_ROF_ENTRY_CHECKSUM) ||
694 (rules->rules[rule_cnt].type ==
695 MLX5_RXP_ROF_ENTRY_CHECKSUM_EX_EM)) {
697 /* Flush rules before checking reg values. */
698 rule_offset = (rule_cnt - pending);
699 ret = rxp_flush_rules(priv->ctx,
700 &rules->rules[rule_offset],
703 DRV_LOG(ERR, "Failed to flush rules.");
707 block = (rules->rules[rule_cnt].addr >> 16) & 0xFFFF;
709 reg = MLX5_RXP_CSR_BASE_ADDRESS;
711 reg = MLX5_RXP_RTRU_CSR_BASE_ADDRESS;
713 DRV_LOG(ERR, "Invalid ROF register 0x%08X!",
714 rules->rules[rule_cnt].addr);
717 reg += (rules->rules[rule_cnt].addr & 0xFFFF) *
719 ret = mlx5_devx_regex_register_read(priv->ctx, id,
722 DRV_LOG(ERR, "RXP CSR read failed!");
725 if ((priv->prog_mode == MLX5_RXP_SHARED_PROG_MODE) &&
726 ((rules->rules[rule_cnt].type ==
727 MLX5_RXP_ROF_ENTRY_CHECKSUM_EX_EM) &&
728 (val != rules->rules[rule_cnt].value))) {
729 DRV_LOG(ERR, "Unexpected value for register:");
730 DRV_LOG(ERR, "reg %x" PRIu32 " got %x" PRIu32,
731 rules->rules[rule_cnt].addr, val);
732 DRV_LOG(ERR, "expected %" PRIx64 ".",
733 rules->rules[rule_cnt].value);
735 } else if ((priv->prog_mode ==
736 MLX5_RXP_PRIVATE_PROG_MODE) &&
737 (rules->rules[rule_cnt].type ==
738 MLX5_RXP_ROF_ENTRY_CHECKSUM) &&
739 (val != rules->rules[rule_cnt].value)) {
740 DRV_LOG(ERR, "Unexpected value for register:");
741 DRV_LOG(ERR, "reg %x" PRIu32 " got %x" PRIu32,
742 rules->rules[rule_cnt].addr, val);
743 DRV_LOG(ERR, "expected %" PRIx64 ".",
744 rules->rules[rule_cnt].value);
746 } else if ((rules->rules[rule_cnt].type ==
747 MLX5_RXP_ROF_ENTRY_EQ) &&
748 (val != rules->rules[rule_cnt].value)) {
749 DRV_LOG(ERR, "Unexpected value for register:");
750 DRV_LOG(ERR, "reg %x" PRIu32 " got %x" PRIu32,
751 rules->rules[rule_cnt].addr, val);
752 DRV_LOG(ERR, "expected %" PRIx64 ".",
753 rules->rules[rule_cnt].value);
755 } else if ((rules->rules[rule_cnt].type ==
756 MLX5_RXP_ROF_ENTRY_GTE) &&
757 (val < rules->rules[rule_cnt].value)) {
758 DRV_LOG(ERR, "Unexpected value reg 0x%08X,",
759 rules->rules[rule_cnt].addr);
760 DRV_LOG(ERR, "got %X, expected >= %" PRIx64 ".",
761 val, rules->rules[rule_cnt].value);
763 } else if ((rules->rules[rule_cnt].type ==
764 MLX5_RXP_ROF_ENTRY_LTE) &&
765 (val > rules->rules[rule_cnt].value)) {
766 DRV_LOG(ERR, "Unexpected value reg 0x%08X,",
767 rules->rules[rule_cnt].addr);
768 DRV_LOG(ERR, "got %08X expected <= %" PRIx64,
769 val, rules->rules[rule_cnt].value);
775 DRV_LOG(ERR, "Error: Invalid rule type %d!",
776 rules->rules[rule_cnt].type);
785 * Shared memory programming mode, here all external db instructions are written
786 * to EM via the host.
789 write_shared_rules(struct mlx5_regex_priv *priv,
790 struct mlx5_rxp_ctl_rules_pgm *rules, uint32_t count,
791 uint8_t db_to_program)
793 uint32_t rule_cnt, rof_rule_addr;
794 uint64_t tmp_write_swap[4];
796 if (priv->prog_mode == MLX5_RXP_MODE_NOT_DEFINED)
798 if ((rules->count == 0) || (count == 0))
802 * Note the following section of code carries out a 32byte swap of
803 * instruction to coincide with HW 32byte swap. This may need removed
804 * in new variants of this programming function!
806 while (rule_cnt < rules->count) {
807 if ((rules->rules[rule_cnt].type == MLX5_RXP_ROF_ENTRY_EM) &&
808 (priv->prog_mode == MLX5_RXP_SHARED_PROG_MODE)) {
810 * Note there are always blocks of 8 instructions for
811 * 7's written sequentially. However there is no
812 * guarantee that all blocks are sequential!
814 if (count >= (rule_cnt + MLX5_RXP_INST_BLOCK_SIZE)) {
816 * Ensure memory write not exceeding boundary
817 * Check essential to ensure 0x10000 offset
820 if ((uint8_t *)((uint8_t *)
821 priv->db[db_to_program].ptr +
822 ((rules->rules[rule_cnt + 7].addr <<
823 MLX5_RXP_INST_OFFSET))) >=
824 ((uint8_t *)((uint8_t *)
825 priv->db[db_to_program].ptr +
826 MLX5_MAX_DB_SIZE))) {
827 DRV_LOG(ERR, "DB exceeded memory!");
831 * Rule address Offset to align with RXP
832 * external instruction offset.
834 rof_rule_addr = (rules->rules[rule_cnt].addr <<
835 MLX5_RXP_INST_OFFSET);
836 /* 32 byte instruction swap (sw work around)! */
837 tmp_write_swap[0] = le64toh(
838 rules->rules[(rule_cnt + 4)].value);
839 tmp_write_swap[1] = le64toh(
840 rules->rules[(rule_cnt + 5)].value);
841 tmp_write_swap[2] = le64toh(
842 rules->rules[(rule_cnt + 6)].value);
843 tmp_write_swap[3] = le64toh(
844 rules->rules[(rule_cnt + 7)].value);
845 /* Write only 4 of the 8 instructions. */
846 memcpy((uint8_t *)((uint8_t *)
847 priv->db[db_to_program].ptr +
848 rof_rule_addr), &tmp_write_swap,
849 (sizeof(uint64_t) * 4));
850 /* Write 1st 4 rules of block after last 4. */
851 rof_rule_addr = (rules->rules[
852 (rule_cnt + 4)].addr <<
853 MLX5_RXP_INST_OFFSET);
854 tmp_write_swap[0] = le64toh(
855 rules->rules[(rule_cnt + 0)].value);
856 tmp_write_swap[1] = le64toh(
857 rules->rules[(rule_cnt + 1)].value);
858 tmp_write_swap[2] = le64toh(
859 rules->rules[(rule_cnt + 2)].value);
860 tmp_write_swap[3] = le64toh(
861 rules->rules[(rule_cnt + 3)].value);
862 memcpy((uint8_t *)((uint8_t *)
863 priv->db[db_to_program].ptr +
864 rof_rule_addr), &tmp_write_swap,
865 (sizeof(uint64_t) * 4));
868 /* Fast forward as already handled block of 8. */
869 rule_cnt += MLX5_RXP_INST_BLOCK_SIZE;
871 rule_cnt++; /* Must be something other than EM rule. */
877 rxp_db_setup(struct mlx5_regex_priv *priv)
882 /* Setup database memories for both RXP engines + reprogram memory. */
883 for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT); i++) {
884 priv->db[i].ptr = rte_malloc("", MLX5_MAX_DB_SIZE, 0);
885 if (!priv->db[i].ptr) {
886 DRV_LOG(ERR, "Failed to alloc db memory!");
890 /* Register the memory. */
891 priv->db[i].umem.umem = mlx5_glue->devx_umem_reg(priv->ctx,
893 MLX5_MAX_DB_SIZE, 7);
894 if (!priv->db[i].umem.umem) {
895 DRV_LOG(ERR, "Failed to register memory!");
899 /* Ensure set all DB memory to 0's before setting up DB. */
900 memset(priv->db[i].ptr, 0x00, MLX5_MAX_DB_SIZE);
901 /* No data currently in database. */
903 priv->db[i].active = false;
904 priv->db[i].db_assigned_to_eng_num = MLX5_RXP_DB_NOT_ASSIGNED;
908 for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT); i++) {
910 rte_free(priv->db[i].ptr);
911 if (priv->db[i].umem.umem)
912 mlx5_glue->devx_umem_dereg(priv->db[i].umem.umem);
918 mlx5_regex_rules_db_import(struct rte_regexdev *dev,
919 const char *rule_db, uint32_t rule_db_len)
921 struct mlx5_regex_priv *priv = dev->data->dev_private;
922 struct mlx5_rxp_ctl_rules_pgm *rules = NULL;
926 if (priv->prog_mode == MLX5_RXP_MODE_NOT_DEFINED) {
927 DRV_LOG(ERR, "RXP programming mode not set!");
930 if (rule_db == NULL) {
931 DRV_LOG(ERR, "Database empty!");
934 if (rule_db_len == 0)
936 ret = rxp_parse_rof(rule_db, rule_db_len, &rules);
938 DRV_LOG(ERR, "Can't parse ROF file.");
941 /* Need to ensure RXP not busy before stop! */
942 for (id = 0; id < priv->nb_engines; id++) {
943 ret = rxp_stop_engine(priv->ctx, id);
945 DRV_LOG(ERR, "Can't stop engine.");
949 ret = program_rxp_rules(priv, rules, id);
951 DRV_LOG(ERR, "Failed to program rxp rules.");
955 ret = rxp_start_engine(priv->ctx, id);
957 DRV_LOG(ERR, "Can't start engine.");
970 mlx5_regex_configure(struct rte_regexdev *dev,
971 const struct rte_regexdev_config *cfg)
973 struct mlx5_regex_priv *priv = dev->data->dev_private;
976 if (priv->prog_mode == MLX5_RXP_MODE_NOT_DEFINED)
978 priv->nb_queues = cfg->nb_queue_pairs;
979 dev->data->dev_conf.nb_queue_pairs = priv->nb_queues;
980 priv->qps = rte_zmalloc(NULL, sizeof(struct mlx5_regex_qp) *
982 if (!priv->nb_queues) {
983 DRV_LOG(ERR, "can't allocate qps memory");
987 priv->nb_max_matches = cfg->nb_max_matches;
988 /* Setup rxp db memories. */
989 if (rxp_db_setup(priv)) {
990 DRV_LOG(ERR, "Failed to setup RXP db memory");
994 if (cfg->rule_db != NULL) {
995 ret = mlx5_regex_rules_db_import(dev, cfg->rule_db,
998 DRV_LOG(ERR, "Failed to program rxp rules.");
1000 goto configure_error;
1003 DRV_LOG(DEBUG, "Regex config without rules programming!");
1007 rte_free(priv->qps);