1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_REGEX_RXP_H_
6 #define RTE_PMD_MLX5_REGEX_RXP_H_
8 #define MLX5_RXP_BF2_IDENTIFIER 0x0
9 #define MLX5_RXP_MAX_JOB_LENGTH 16384
10 #define MLX5_RXP_MAX_SUBSETS 4095
11 #define MLX5_RXP_CSR_NUM_ENTRIES 31
13 #define MLX5_RXP_CTRL_TYPE_MASK 7
14 #define MLX5_RXP_CTRL_TYPE_JOB_DESCRIPTOR 0
15 #define MLX5_RXP_CTRL_TYPE_RESPONSE_DESCRIPTOR 1
16 #define MLX5_RXP_CTRL_TYPE_MEMORY_WRITE 4
17 #define MLX5_RXP_CSR_CTRL_DISABLE_L2C (1 << 7)
19 #define MLX5_RXP_CTRL_JOB_DESC_SOF 0x0010
20 #define MLX5_RXP_CTRL_JOB_DESC_EOF 0x0020
21 #define MLX5_RXP_CTRL_JOB_DESC_HPM_ENABLE 0x0100
22 #define MLX5_RXP_CTRL_JOB_DESC_ANYMATCH_ENABLE 0x0200
23 #define MLX5_RXP_CTRL_JOB_DESC_FLAGS (MLX5_RXP_CTRL_JOB_DESC_SOF | \
24 MLX5_RXP_CTRL_JOB_DESC_EOF | \
25 MLX5_RXP_CTRL_JOB_DESC_HPM_ENABLE | \
26 MLX5_RXP_CTRL_JOB_DESC_ANYMATCH_ENABLE)
28 #define MLX5_RXP_CTRL_VALID 0x8000
30 #define MLX5_RXP_RESP_STATUS_MAX_PRI_THREADS (1 << 3)
31 #define MLX5_RXP_RESP_STATUS_MAX_SEC_THREADS (1 << 4)
32 #define MLX5_RXP_RESP_STATUS_MAX_LATENCY (1 << 5)
33 #define MLX5_RXP_RESP_STATUS_MAX_MATCH (1 << 6)
34 #define MLX5_RXP_RESP_STATUS_MAX_PREFIX (1 << 7)
35 #define MLX5_RXP_RESP_STATUS_HPM (1 << 8)
36 #define MLX5_RXP_RESP_STATUS_ANYMATCH (1 << 9)
37 #define MLX5_RXP_RESP_STATUS_PMI_SOJ (1 << 13)
38 #define MLX5_RXP_RESP_STATUS_PMI_EOJ (1 << 14)
40 /* This describes the header the RXP expects for any search data. */
41 struct mlx5_rxp_job_desc {
48 struct mlx5_rxp_response_desc {
51 uint8_t detected_match_count;
53 uint16_t primary_thread_count;
54 uint16_t instruction_count;
55 uint16_t latency_count;
56 uint16_t pmi_min_byte_ptr;
59 struct mlx5_rxp_match_tuple {
65 struct mlx5_rxp_response {
66 struct mlx5_rxp_response_desc header;
67 struct mlx5_rxp_match_tuple matches[0];
70 #define MLX5_RXP_MAX_MATCHES 254
72 #define MLX5_RXP_CTL_RULES_PGM 1
73 #define MLX5_RXP_CTL_RULES_PGM_INCR 2
75 #define MLX5_RXP_ROF_ENTRY_INST 0
76 #define MLX5_RXP_ROF_ENTRY_EQ 1
77 #define MLX5_RXP_ROF_ENTRY_GTE 2
78 #define MLX5_RXP_ROF_ENTRY_LTE 3
79 #define MLX5_RXP_ROF_ENTRY_CHECKSUM 4
80 #define MLX5_RXP_ROF_ENTRY_CHECKSUM_EX_EM 5
81 #define MLX5_RXP_ROF_ENTRY_IM 6
82 #define MLX5_RXP_ROF_ENTRY_EM 7
83 #define MLX5_RXP_ROF_ENTRY_TYPE_MAX 7
85 #define MLX5_RXP_INST_OFFSET 3
86 #define MLX5_RXP_INST_BLOCK_SIZE 8
87 #define MLX5_MAX_SIZE_RES_DES (sizeof(struct mlx5_rxp_response_desc))
88 #define MLX5_MAX_DB_SIZE (1u << 27u)
89 #define MLX5_MAX_SIZE_MATCH_RESP (254 * sizeof(struct mlx5_rxp_match_tuple))
90 #define MLX5_RXP_SQ_NOT_BUSY false
91 #define MLX5_RXP_SQ_BUSY true
94 struct mlx5_rxp_ctl_hdr {
99 struct mlx5_rxp_rof_entry {
105 struct mlx5_rxp_rof {
106 uint32_t rof_version;
108 char *rxp_compiler_version;
109 uint32_t rof_revision;
110 uint32_t number_of_entries;
111 struct mlx5_rxp_rof_entry *rof_entries;
114 struct mlx5_rxp_ctl_rules_pgm {
115 struct mlx5_rxp_ctl_hdr hdr;
117 struct mlx5_rxp_rof_entry rules[0];
120 /* RXP programming mode setting. */
121 enum mlx5_rxp_program_mode {
122 MLX5_RXP_MODE_NOT_DEFINED = 0,
123 MLX5_RXP_SHARED_PROG_MODE,
124 MLX5_RXP_PRIVATE_PROG_MODE,
127 #define MLX5_RXP_POLL_CSR_FOR_VALUE_TIMEOUT 3000 /* Poll timeout in ms. */
128 #define MLX5_RXP_INITIALIZATION_TIMEOUT 60000 /* Initialize timeout in ms. */
129 #define MLX5_RXP_MAX_ENGINES 2u /* Number of RXP engines. */
130 #define MLX5_RXP_EM_COUNT 1u /* Extra External Memories to use. */
131 #define MLX5_RXP_DB_NOT_ASSIGNED 0xFF
133 struct mlx5_regex_mkey {
134 struct mlx5dv_devx_umem *umem;
135 struct mlx5_devx_obj *mkey;
139 #endif /* RTE_PMD_MLX5_REGEX_RXP_H_ */