1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
5 #ifndef _MLX5_RXP_CSRS_H_
6 #define _MLX5_RXP_CSRS_H_
9 #define MLX5_RXP_BF2_IDENTIFIER 0x07055254ul
12 * Common to all RXP implementations
14 #define MLX5_RXP_CSR_BASE_ADDRESS 0x0000ul
15 #define MLX5_RXP_RTRU_CSR_BASE_ADDRESS 0x0100ul
16 #define MLX5_RXP_STATS_CSR_BASE_ADDRESS 0x0200ul
17 #define MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS 0x0600ul
19 #define MLX5_RXP_CSR_WIDTH 4
21 /* This is the identifier we expect to see in the first RXP CSR */
22 #define MLX5_RXP_IDENTIFIER 0x5254
24 /* Hyperion specific BAR0 offsets */
25 #define MLX5_RXP_FPGA_BASE_ADDRESS 0x0000ul
26 #define MLX5_RXP_PCIE_BASE_ADDRESS 0x1000ul
27 #define MLX5_RXP_IDMA_BASE_ADDRESS 0x2000ul
28 #define MLX5_RXP_EDMA_BASE_ADDRESS 0x3000ul
29 #define MLX5_RXP_SYSMON_BASE_ADDRESS 0xf300ul
30 #define MLX5_RXP_ISP_CSR_BASE_ADDRESS 0xf400ul
32 /* Offset to the RXP common 4K CSR space */
33 #define MLX5_RXP_PCIE_CSR_BASE_ADDRESS 0xf000ul
37 #define MLX5_RXP_FPGA_VERSION (MLX5_RXP_FPGA_BASE_ADDRESS + \
38 MLX5_RXP_CSR_WIDTH * 0)
41 #define MLX5_RXP_PCIE_INIT_ISR (MLX5_RXP_PCIE_BASE_ADDRESS + \
42 MLX5_RXP_CSR_WIDTH * 0)
43 #define MLX5_RXP_PCIE_INIT_IMR (MLX5_RXP_PCIE_BASE_ADDRESS + \
44 MLX5_RXP_CSR_WIDTH * 1)
45 #define MLX5_RXP_PCIE_INIT_CFG_STAT (MLX5_RXP_PCIE_BASE_ADDRESS + \
46 MLX5_RXP_CSR_WIDTH * 2)
47 #define MLX5_RXP_PCIE_INIT_FLR (MLX5_RXP_PCIE_BASE_ADDRESS + \
48 MLX5_RXP_CSR_WIDTH * 3)
49 #define MLX5_RXP_PCIE_INIT_CTRL (MLX5_RXP_PCIE_BASE_ADDRESS + \
50 MLX5_RXP_CSR_WIDTH * 4)
53 #define MLX5_RXP_IDMA_ISR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 0)
54 #define MLX5_RXP_IDMA_IMR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 1)
55 #define MLX5_RXP_IDMA_CSR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 4)
56 #define MLX5_RXP_IDMA_CSR_RST_MSK 0x0001
57 #define MLX5_RXP_IDMA_CSR_PDONE_MSK 0x0002
58 #define MLX5_RXP_IDMA_CSR_INIT_MSK 0x0004
59 #define MLX5_RXP_IDMA_CSR_EN_MSK 0x0008
60 #define MLX5_RXP_IDMA_QCR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 5)
61 #define MLX5_RXP_IDMA_QCR_QAVAIL_MSK 0x00FF
62 #define MLX5_RXP_IDMA_QCR_QEN_MSK 0xFF00
63 #define MLX5_RXP_IDMA_DCR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 6)
64 #define MLX5_RXP_IDMA_DWCTR (MLX5_RXP_IDMA_BASE_ADDRESS + \
65 MLX5_RXP_CSR_WIDTH * 7)
66 #define MLX5_RXP_IDMA_DWTOR (MLX5_RXP_IDMA_BASE_ADDRESS + \
67 MLX5_RXP_CSR_WIDTH * 8)
68 #define MLX5_RXP_IDMA_PADCR (MLX5_RXP_IDMA_BASE_ADDRESS + \
69 MLX5_RXP_CSR_WIDTH * 9)
70 #define MLX5_RXP_IDMA_DFCR (MLX5_RXP_IDMA_BASE_ADDRESS + \
71 MLX5_RXP_CSR_WIDTH * 10)
72 #define MLX5_RXP_IDMA_FOFLR0 (MLX5_RXP_IDMA_BASE_ADDRESS + \
73 MLX5_RXP_CSR_WIDTH * 16)
74 #define MLX5_RXP_IDMA_FOFLR1 (MLX5_RXP_IDMA_BASE_ADDRESS + \
75 MLX5_RXP_CSR_WIDTH * 17)
76 #define MLX5_RXP_IDMA_FOFLR2 (MLX5_RXP_IDMA_BASE_ADDRESS + \
77 MLX5_RXP_CSR_WIDTH * 18)
78 #define MLX5_RXP_IDMA_FUFLR0 (MLX5_RXP_IDMA_BASE_ADDRESS + \
79 MLX5_RXP_CSR_WIDTH * 24)
80 #define MLX5_RXP_IDMA_FUFLR1 (MLX5_RXP_IDMA_BASE_ADDRESS + \
81 MLX5_RXP_CSR_WIDTH * 25)
82 #define MLX5_RXP_IDMA_FUFLR2 (MLX5_RXP_IDMA_BASE_ADDRESS + \
83 MLX5_RXP_CSR_WIDTH * 26)
85 #define MLX5_RXP_IDMA_QCSR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
86 MLX5_RXP_CSR_WIDTH * 128)
87 #define MLX5_RXP_IDMA_QCSR_RST_MSK 0x0001
88 #define MLX5_RXP_IDMA_QCSR_PDONE_MSK 0x0002
89 #define MLX5_RXP_IDMA_QCSR_INIT_MSK 0x0004
90 #define MLX5_RXP_IDMA_QCSR_EN_MSK 0x0008
91 #define MLX5_RXP_IDMA_QDPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
92 MLX5_RXP_CSR_WIDTH * 192)
93 #define MLX5_RXP_IDMA_QTPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
94 MLX5_RXP_CSR_WIDTH * 256)
95 #define MLX5_RXP_IDMA_QDRPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
96 MLX5_RXP_CSR_WIDTH * 320)
97 #define MLX5_RXP_IDMA_QDRALR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
98 MLX5_RXP_CSR_WIDTH * 384)
99 #define MLX5_RXP_IDMA_QDRAHR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
100 MLX5_RXP_CSR_WIDTH * 385)
103 #define MLX5_RXP_EDMA_ISR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 0)
104 #define MLX5_RXP_EDMA_IMR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 1)
105 #define MLX5_RXP_EDMA_CSR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 4)
106 #define MLX5_RXP_EDMA_CSR_RST_MSK 0x0001
107 #define MLX5_RXP_EDMA_CSR_PDONE_MSK 0x0002
108 #define MLX5_RXP_EDMA_CSR_INIT_MSK 0x0004
109 #define MLX5_RXP_EDMA_CSR_EN_MSK 0x0008
110 #define MLX5_RXP_EDMA_QCR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 5)
111 #define MLX5_RXP_EDMA_QCR_QAVAIL_MSK 0x00FF
112 #define MLX5_RXP_EDMA_QCR_QEN_MSK 0xFF00
113 #define MLX5_RXP_EDMA_DCR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 6)
114 #define MLX5_RXP_EDMA_DWCTR (MLX5_RXP_EDMA_BASE_ADDRESS + \
115 MLX5_RXP_CSR_WIDTH * 7)
116 #define MLX5_RXP_EDMA_DWTOR (MLX5_RXP_EDMA_BASE_ADDRESS + \
117 MLX5_RXP_CSR_WIDTH * 8)
118 #define MLX5_RXP_EDMA_DFCR (MLX5_RXP_EDMA_BASE_ADDRESS + \
119 MLX5_RXP_CSR_WIDTH * 10)
120 #define MLX5_RXP_EDMA_FOFLR0 (MLX5_RXP_EDMA_BASE_ADDRESS + \
121 MLX5_RXP_CSR_WIDTH * 16)
122 #define MLX5_RXP_EDMA_FOFLR1 (MLX5_RXP_EDMA_BASE_ADDRESS + \
123 MLX5_RXP_CSR_WIDTH * 17)
124 #define MLX5_RXP_EDMA_FOFLR2 (MLX5_RXP_EDMA_BASE_ADDRESS + \
125 MLX5_RXP_CSR_WIDTH * 18)
126 #define MLX5_RXP_EDMA_FUFLR0 (MLX5_RXP_EDMA_BASE_ADDRESS + \
127 MLX5_RXP_CSR_WIDTH * 24)
128 #define MLX5_RXP_EDMA_FUFLR1 (MLX5_RXP_EDMA_BASE_ADDRESS +\
129 MLX5_RXP_CSR_WIDTH * 25)
130 #define MLX5_RXP_EDMA_FUFLR2 (MLX5_RXP_EDMA_BASE_ADDRESS + \
131 MLX5_RXP_CSR_WIDTH * 26)
133 #define MLX5_RXP_EDMA_QCSR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \
134 MLX5_RXP_CSR_WIDTH * 128)
135 #define MLX5_RXP_EDMA_QCSR_RST_MSK 0x0001
136 #define MLX5_RXP_EDMA_QCSR_PDONE_MSK 0x0002
137 #define MLX5_RXP_EDMA_QCSR_INIT_MSK 0x0004
138 #define MLX5_RXP_EDMA_QCSR_EN_MSK 0x0008
139 #define MLX5_RXP_EDMA_QTPTR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \
140 MLX5_RXP_CSR_WIDTH * 256)
141 #define MLX5_RXP_EDMA_QDRPTR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \
142 MLX5_RXP_CSR_WIDTH * 320)
143 #define MLX5_RXP_EDMA_QDRALR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \
144 MLX5_RXP_CSR_WIDTH * 384)
145 #define MLX5_RXP_EDMA_QDRAHR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \
146 MLX5_RXP_CSR_WIDTH * 385)
149 #define MLX5_RXP_CSR_IDENTIFIER (MLX5_RXP_CSR_BASE_ADDRESS + \
150 MLX5_RXP_CSR_WIDTH * 0)
151 #define MLX5_RXP_CSR_REVISION (MLX5_RXP_CSR_BASE_ADDRESS + \
152 MLX5_RXP_CSR_WIDTH * 1)
153 #define MLX5_RXP_CSR_CAPABILITY_0 (MLX5_RXP_CSR_BASE_ADDRESS + \
154 MLX5_RXP_CSR_WIDTH * 2)
155 #define MLX5_RXP_CSR_CAPABILITY_1 (MLX5_RXP_CSR_BASE_ADDRESS + \
156 MLX5_RXP_CSR_WIDTH * 3)
157 #define MLX5_RXP_CSR_CAPABILITY_2 (MLX5_RXP_CSR_BASE_ADDRESS + \
158 MLX5_RXP_CSR_WIDTH * 4)
159 #define MLX5_RXP_CSR_CAPABILITY_3 (MLX5_RXP_CSR_BASE_ADDRESS + \
160 MLX5_RXP_CSR_WIDTH * 5)
161 #define MLX5_RXP_CSR_CAPABILITY_4 (MLX5_RXP_CSR_BASE_ADDRESS + \
162 MLX5_RXP_CSR_WIDTH * 6)
163 #define MLX5_RXP_CSR_CAPABILITY_5 (MLX5_RXP_CSR_BASE_ADDRESS + \
164 MLX5_RXP_CSR_WIDTH * 7)
165 #define MLX5_RXP_CSR_CAPABILITY_6 (MLX5_RXP_CSR_BASE_ADDRESS + \
166 MLX5_RXP_CSR_WIDTH * 8)
167 #define MLX5_RXP_CSR_CAPABILITY_7 (MLX5_RXP_CSR_BASE_ADDRESS + \
168 MLX5_RXP_CSR_WIDTH * 9)
169 #define MLX5_RXP_CSR_STATUS (MLX5_RXP_CSR_BASE_ADDRESS + \
170 MLX5_RXP_CSR_WIDTH * 10)
171 #define MLX5_RXP_CSR_STATUS_INIT_DONE 0x0001
172 #define MLX5_RXP_CSR_STATUS_GOING 0x0008
173 #define MLX5_RXP_CSR_STATUS_IDLE 0x0040
174 #define MLX5_RXP_CSR_STATUS_TRACKER_OK 0x0080
175 #define MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT 0x0100
176 #define MLX5_RXP_CSR_FIFO_STATUS_0 (MLX5_RXP_CSR_BASE_ADDRESS + \
177 MLX5_RXP_CSR_WIDTH * 11)
178 #define MLX5_RXP_CSR_FIFO_STATUS_1 (MLX5_RXP_CSR_BASE_ADDRESS + \
179 MLX5_RXP_CSR_WIDTH * 12)
180 #define MLX5_RXP_CSR_JOB_DDOS_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
181 MLX5_RXP_CSR_WIDTH * 13)
182 /* 14 + 15 reserved */
183 #define MLX5_RXP_CSR_CORE_CLK_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
184 MLX5_RXP_CSR_WIDTH * 16)
185 #define MLX5_RXP_CSR_WRITE_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
186 MLX5_RXP_CSR_WIDTH * 17)
187 #define MLX5_RXP_CSR_JOB_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
188 MLX5_RXP_CSR_WIDTH * 18)
189 #define MLX5_RXP_CSR_JOB_ERROR_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
190 MLX5_RXP_CSR_WIDTH * 19)
191 #define MLX5_RXP_CSR_JOB_BYTE_COUNT0 (MLX5_RXP_CSR_BASE_ADDRESS + \
192 MLX5_RXP_CSR_WIDTH * 20)
193 #define MLX5_RXP_CSR_JOB_BYTE_COUNT1 (MLX5_RXP_CSR_BASE_ADDRESS + \
194 MLX5_RXP_CSR_WIDTH * 21)
195 #define MLX5_RXP_CSR_RESPONSE_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
196 MLX5_RXP_CSR_WIDTH * 22)
197 #define MLX5_RXP_CSR_MATCH_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
198 MLX5_RXP_CSR_WIDTH * 23)
199 #define MLX5_RXP_CSR_CTRL (MLX5_RXP_CSR_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 24)
200 #define MLX5_RXP_CSR_CTRL_INIT 0x0001
201 #define MLX5_RXP_CSR_CTRL_GO 0x0008
202 #define MLX5_RXP_CSR_MAX_MATCH (MLX5_RXP_CSR_BASE_ADDRESS + \
203 MLX5_RXP_CSR_WIDTH * 25)
204 #define MLX5_RXP_CSR_MAX_PREFIX (MLX5_RXP_CSR_BASE_ADDRESS + \
205 MLX5_RXP_CSR_WIDTH * 26)
206 #define MLX5_RXP_CSR_MAX_PRI_THREAD (MLX5_RXP_CSR_BASE_ADDRESS + \
207 MLX5_RXP_CSR_WIDTH * 27)
208 #define MLX5_RXP_CSR_MAX_LATENCY (MLX5_RXP_CSR_BASE_ADDRESS + \
209 MLX5_RXP_CSR_WIDTH * 28)
210 #define MLX5_RXP_CSR_SCRATCH_1 (MLX5_RXP_CSR_BASE_ADDRESS + \
211 MLX5_RXP_CSR_WIDTH * 29)
212 #define MLX5_RXP_CSR_CLUSTER_MASK (MLX5_RXP_CSR_BASE_ADDRESS + \
213 MLX5_RXP_CSR_WIDTH * 30)
214 #define MLX5_RXP_CSR_INTRA_CLUSTER_MASK (MLX5_RXP_CSR_BASE_ADDRESS + \
215 MLX5_RXP_CSR_WIDTH * 31)
217 /* Runtime Rule Update CSRs */
219 #define MLX5_RXP_RTRU_CSR_CAPABILITY (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
220 MLX5_RXP_CSR_WIDTH * 2)
222 #define MLX5_RXP_RTRU_CSR_STATUS (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
223 MLX5_RXP_CSR_WIDTH * 10)
224 #define MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE 0x0002
225 #define MLX5_RXP_RTRU_CSR_STATUS_IM_INIT_DONE 0x0010
226 #define MLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE 0x0020
227 #define MLX5_RXP_RTRU_CSR_STATUS_L2C_INIT_DONE 0x0040
228 #define MLX5_RXP_RTRU_CSR_STATUS_EM_INIT_DONE 0x0080
229 #define MLX5_RXP_RTRU_CSR_FIFO_STAT (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
230 MLX5_RXP_CSR_WIDTH * 11)
232 #define MLX5_RXP_RTRU_CSR_CHECKSUM_0 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
233 MLX5_RXP_CSR_WIDTH * 16)
234 #define MLX5_RXP_RTRU_CSR_CHECKSUM_1 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
235 MLX5_RXP_CSR_WIDTH * 17)
236 #define MLX5_RXP_RTRU_CSR_CHECKSUM_2 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
237 MLX5_RXP_CSR_WIDTH * 18)
238 /* 19 + 20 reserved */
239 #define MLX5_RXP_RTRU_CSR_RTRU_COUNT (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
240 MLX5_RXP_CSR_WIDTH * 21)
241 #define MLX5_RXP_RTRU_CSR_ROF_REV (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
242 MLX5_RXP_CSR_WIDTH * 22)
244 #define MLX5_RXP_RTRU_CSR_CTRL (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
245 MLX5_RXP_CSR_WIDTH * 24)
246 #define MLX5_RXP_RTRU_CSR_CTRL_INIT 0x0001
247 #define MLX5_RXP_RTRU_CSR_CTRL_GO 0x0002
248 #define MLX5_RXP_RTRU_CSR_CTRL_SIP 0x0004
249 #define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_MASK (3 << 4)
250 #define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2_EM (0 << 4)
251 #define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2 (1 << 4)
252 #define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_L1_L2 (2 << 4)
253 #define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_EM (3 << 4)
254 #define MLX5_RXP_RTRU_CSR_ADDR (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
255 MLX5_RXP_CSR_WIDTH * 25)
256 #define MLX5_RXP_RTRU_CSR_DATA_0 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
257 MLX5_RXP_CSR_WIDTH * 26)
258 #define MLX5_RXP_RTRU_CSR_DATA_1 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
259 MLX5_RXP_CSR_WIDTH * 27)
262 /* Statistics CSRs */
263 #define MLX5_RXP_STATS_CSR_CLUSTER (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
264 MLX5_RXP_CSR_WIDTH * 0)
265 #define MLX5_RXP_STATS_CSR_L2_CACHE (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
266 MLX5_RXP_CSR_WIDTH * 24)
267 #define MLX5_RXP_STATS_CSR_MPFE_FIFO (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
268 MLX5_RXP_CSR_WIDTH * 25)
269 #define MLX5_RXP_STATS_CSR_PE (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
270 MLX5_RXP_CSR_WIDTH * 28)
271 #define MLX5_RXP_STATS_CSR_CP (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
272 MLX5_RXP_CSR_WIDTH * 30)
273 #define MLX5_RXP_STATS_CSR_DP (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
274 MLX5_RXP_CSR_WIDTH * 31)
276 /* Sysmon Stats CSRs */
277 #define MLX5_RXP_SYSMON_CSR_T_FPGA (MLX5_RXP_SYSMON_BASE_ADDRESS + \
278 MLX5_RXP_CSR_WIDTH * 0)
279 #define MLX5_RXP_SYSMON_CSR_V_VCCINT (MLX5_RXP_SYSMON_BASE_ADDRESS + \
280 MLX5_RXP_CSR_WIDTH * 1)
281 #define MLX5_RXP_SYSMON_CSR_V_VCCAUX (MLX5_RXP_SYSMON_BASE_ADDRESS + \
282 MLX5_RXP_CSR_WIDTH * 2)
283 #define MLX5_RXP_SYSMON_CSR_T_U1 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
284 MLX5_RXP_CSR_WIDTH * 20)
285 #define MLX5_RXP_SYSMON_CSR_I_EDG12V (MLX5_RXP_SYSMON_BASE_ADDRESS + \
286 MLX5_RXP_CSR_WIDTH * 21)
287 #define MLX5_RXP_SYSMON_CSR_I_VCC3V3 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
288 MLX5_RXP_CSR_WIDTH * 22)
289 #define MLX5_RXP_SYSMON_CSR_I_VCC2V5 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
290 MLX5_RXP_CSR_WIDTH * 23)
291 #define MLX5_RXP_SYSMON_CSR_T_U2 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
292 MLX5_RXP_CSR_WIDTH * 28)
293 #define MLX5_RXP_SYSMON_CSR_I_AUX12V (MLX5_RXP_SYSMON_BASE_ADDRESS + \
294 MLX5_RXP_CSR_WIDTH * 29)
295 #define MLX5_RXP_SYSMON_CSR_I_VCC1V8 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
296 MLX5_RXP_CSR_WIDTH * 30)
297 #define MLX5_RXP_SYSMON_CSR_I_VDDR3 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
298 MLX5_RXP_CSR_WIDTH * 31)
300 /* In Service Programming CSRs */
302 /* RXP-F1 and RXP-ZYNQ specific CSRs */
303 #define MLX5_RXP_MQ_CP_BASE (0x0500ul)
304 #define MLX5_RXP_MQ_CP_CAPABILITY_BASE (MLX5_RXP_MQ_CP_BASE + \
305 2 * MLX5_RXP_CSR_WIDTH)
306 #define MLX5_RXP_MQ_CP_CAPABILITY_0 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \
307 0 * MLX5_RXP_CSR_WIDTH)
308 #define MLX5_RXP_MQ_CP_CAPABILITY_1 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \
309 1 * MLX5_RXP_CSR_WIDTH)
310 #define MLX5_RXP_MQ_CP_CAPABILITY_2 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \
311 2 * MLX5_RXP_CSR_WIDTH)
312 #define MLX5_RXP_MQ_CP_CAPABILITY_3 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \
313 3 * MLX5_RXP_CSR_WIDTH)
314 #define MLX5_RXP_MQ_CP_FIFO_STATUS_BASE (MLX5_RXP_MQ_CP_BASE + \
315 11 * MLX5_RXP_CSR_WIDTH)
316 #define MLX5_RXP_MQ_CP_FIFO_STATUS_C0 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \
317 0 * MLX5_RXP_CSR_WIDTH)
318 #define MLX5_RXP_MQ_CP_FIFO_STATUS_C1 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \
319 1 * MLX5_RXP_CSR_WIDTH)
320 #define MLX5_RXP_MQ_CP_FIFO_STATUS_C2 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \
321 2 * MLX5_RXP_CSR_WIDTH)
322 #define MLX5_RXP_MQ_CP_FIFO_STATUS_C3 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \
323 3 * MLX5_RXP_CSR_WIDTH)
325 /* Royalty tracker / licensing related CSRs */
326 #define MLX5_RXPL__CSR_IDENT (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \
327 0 * MLX5_RXP_CSR_WIDTH)
328 #define MLX5_RXPL__IDENTIFIER 0x4c505852 /* MLX5_RXPL_ */
329 #define MLX5_RXPL__CSR_CAPABILITY (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \
330 2 * MLX5_RXP_CSR_WIDTH)
331 #define MLX5_RXPL__TYPE_MASK 0xFF
332 #define MLX5_RXPL__TYPE_NONE 0
333 #define MLX5_RXPL__TYPE_MAXIM 1
334 #define MLX5_RXPL__TYPE_XILINX_DNA 2
335 #define MLX5_RXPL__CSR_STATUS (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \
336 10 * MLX5_RXP_CSR_WIDTH)
337 #define MLX5_RXPL__CSR_IDENT_0 (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \
338 16 * MLX5_RXP_CSR_WIDTH)
339 #define MLX5_RXPL__CSR_KEY_0 (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \
340 24 * MLX5_RXP_CSR_WIDTH)
342 #endif /* _MLX5_RXP_CSRS_H_ */