1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
7 #include <sys/eventfd.h>
9 #include <rte_malloc.h>
10 #include <rte_memory.h>
11 #include <rte_errno.h>
12 #include <rte_lcore.h>
13 #include <rte_atomic.h>
14 #include <rte_common.h>
16 #include <rte_alarm.h>
18 #include <mlx5_common.h>
19 #include <mlx5_common_os.h>
20 #include <mlx5_common_devx.h>
21 #include <mlx5_glue.h>
23 #include "mlx5_vdpa_utils.h"
24 #include "mlx5_vdpa.h"
27 #define MLX5_VDPA_ERROR_TIME_SEC 3u
30 mlx5_vdpa_event_qp_global_release(struct mlx5_vdpa_priv *priv)
33 mlx5_glue->devx_free_uar(priv->uar);
36 #ifdef HAVE_IBV_DEVX_EVENT
39 struct mlx5dv_devx_async_event_hdr event_resp;
40 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr)
44 /* Clean all pending events. */
45 while (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,
47 (ssize_t)sizeof(out.event_resp.cookie))
49 mlx5_os_devx_destroy_event_channel(priv->eventc);
55 /* Prepare all the global resources for all the event objects.*/
57 mlx5_vdpa_event_qp_global_prepare(struct mlx5_vdpa_priv *priv)
63 priv->eventc = mlx5_os_devx_create_event_channel(priv->ctx,
64 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);
67 DRV_LOG(ERR, "Failed to create event channel %d.",
71 flags = fcntl(priv->eventc->fd, F_GETFL);
72 ret = fcntl(priv->eventc->fd, F_SETFL, flags | O_NONBLOCK);
74 DRV_LOG(ERR, "Failed to change event channel FD.");
78 * This PMD always claims the write memory barrier on UAR
79 * registers writings, it is safe to allocate UAR with any
80 * memory mapping type.
82 priv->uar = mlx5_devx_alloc_uar(priv->ctx, -1);
85 DRV_LOG(ERR, "Failed to allocate UAR.");
90 mlx5_vdpa_event_qp_global_release(priv);
95 mlx5_vdpa_cq_destroy(struct mlx5_vdpa_cq *cq)
97 mlx5_devx_cq_destroy(&cq->cq_obj);
98 memset(cq, 0, sizeof(*cq));
101 static inline void __rte_unused
102 mlx5_vdpa_cq_arm(struct mlx5_vdpa_priv *priv, struct mlx5_vdpa_cq *cq)
104 uint32_t arm_sn = cq->arm_sn << MLX5_CQ_SQN_OFFSET;
105 uint32_t cq_ci = cq->cq_ci & MLX5_CI_MASK;
106 uint32_t doorbell_hi = arm_sn | MLX5_CQ_DBR_CMD_ALL | cq_ci;
107 uint64_t doorbell = ((uint64_t)doorbell_hi << 32) | cq->cq_obj.cq->id;
108 uint64_t db_be = rte_cpu_to_be_64(doorbell);
109 uint32_t *addr = RTE_PTR_ADD(priv->uar->base_addr, MLX5_CQ_DOORBELL);
112 cq->cq_obj.db_rec[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
115 *(uint64_t *)addr = db_be;
117 *(uint32_t *)addr = db_be;
119 *((uint32_t *)addr + 1) = db_be >> 32;
126 mlx5_vdpa_cq_create(struct mlx5_vdpa_priv *priv, uint16_t log_desc_n,
127 int callfd, struct mlx5_vdpa_cq *cq)
129 struct mlx5_devx_cq_attr attr = {
131 .uar_page_id = priv->uar->page_id,
133 uint16_t event_nums[1] = {0};
136 ret = mlx5_devx_cq_create(priv->ctx, &cq->cq_obj, log_desc_n, &attr,
141 cq->log_desc_n = log_desc_n;
142 rte_spinlock_init(&cq->sl);
143 /* Subscribe CQ event to the event channel controlled by the driver. */
144 ret = mlx5_os_devx_subscribe_devx_event(priv->eventc,
146 sizeof(event_nums), event_nums,
147 (uint64_t)(uintptr_t)cq);
149 DRV_LOG(ERR, "Failed to subscribe CQE event.");
154 /* Init CQ to ones to be in HW owner in the start. */
155 cq->cq_obj.cqes[0].op_own = MLX5_CQE_OWNER_MASK;
156 cq->cq_obj.cqes[0].wqe_counter = rte_cpu_to_be_16(UINT16_MAX);
158 mlx5_vdpa_cq_arm(priv, cq);
161 mlx5_vdpa_cq_destroy(cq);
165 static inline uint32_t
166 mlx5_vdpa_cq_poll(struct mlx5_vdpa_cq *cq)
168 struct mlx5_vdpa_event_qp *eqp =
169 container_of(cq, struct mlx5_vdpa_event_qp, cq);
170 const unsigned int cq_size = 1 << cq->log_desc_n;
173 uint16_t wqe_counter;
179 uint16_t next_wqe_counter = cq->cq_ci;
180 uint16_t cur_wqe_counter;
183 last_word.word = rte_read32(&cq->cq_obj.cqes[0].wqe_counter);
184 cur_wqe_counter = rte_be_to_cpu_16(last_word.wqe_counter);
185 comp = cur_wqe_counter + (uint16_t)1 - next_wqe_counter;
188 MLX5_ASSERT(MLX5_CQE_OPCODE(last_word.op_own) !=
190 if (unlikely(!(MLX5_CQE_OPCODE(last_word.op_own) ==
192 MLX5_CQE_OPCODE(last_word.op_own) ==
196 /* Ring CQ doorbell record. */
197 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
199 /* Ring SW QP doorbell record. */
200 eqp->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci + cq_size);
206 mlx5_vdpa_arm_all_cqs(struct mlx5_vdpa_priv *priv)
208 struct mlx5_vdpa_cq *cq;
211 for (i = 0; i < priv->nr_virtqs; i++) {
212 cq = &priv->virtqs[i].eqp.cq;
213 if (cq->cq_obj.cq && !cq->armed)
214 mlx5_vdpa_cq_arm(priv, cq);
219 mlx5_vdpa_timer_sleep(struct mlx5_vdpa_priv *priv, uint32_t max)
221 if (priv->event_mode == MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER) {
224 priv->timer_delay_us += priv->event_us;
229 priv->timer_delay_us /= max;
233 if (priv->timer_delay_us)
234 usleep(priv->timer_delay_us);
238 mlx5_vdpa_poll_handle(void *arg)
240 struct mlx5_vdpa_priv *priv = arg;
242 struct mlx5_vdpa_cq *cq;
244 uint64_t current_tic;
246 pthread_mutex_lock(&priv->timer_lock);
247 while (!priv->timer_on)
248 pthread_cond_wait(&priv->timer_cond, &priv->timer_lock);
249 pthread_mutex_unlock(&priv->timer_lock);
250 priv->timer_delay_us = priv->event_mode ==
251 MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER ?
252 MLX5_VDPA_DEFAULT_TIMER_DELAY_US :
256 pthread_mutex_lock(&priv->vq_config_lock);
257 for (i = 0; i < priv->nr_virtqs; i++) {
258 cq = &priv->virtqs[i].eqp.cq;
259 if (cq->cq_obj.cq && !cq->armed) {
260 uint32_t comp = mlx5_vdpa_cq_poll(cq);
263 /* Notify guest for descs consuming. */
264 if (cq->callfd != -1)
265 eventfd_write(cq->callfd,
272 current_tic = rte_rdtsc();
274 /* No traffic ? stop timer and load interrupts. */
275 if (current_tic - priv->last_traffic_tic >=
276 rte_get_timer_hz() * priv->no_traffic_time_s) {
277 DRV_LOG(DEBUG, "Device %s traffic was stopped.",
278 priv->vdev->device->name);
279 mlx5_vdpa_arm_all_cqs(priv);
280 pthread_mutex_unlock(&priv->vq_config_lock);
281 pthread_mutex_lock(&priv->timer_lock);
283 while (!priv->timer_on)
284 pthread_cond_wait(&priv->timer_cond,
286 pthread_mutex_unlock(&priv->timer_lock);
287 priv->timer_delay_us = priv->event_mode ==
288 MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER ?
289 MLX5_VDPA_DEFAULT_TIMER_DELAY_US :
294 priv->last_traffic_tic = current_tic;
296 pthread_mutex_unlock(&priv->vq_config_lock);
297 mlx5_vdpa_timer_sleep(priv, max);
303 mlx5_vdpa_interrupt_handler(void *cb_arg)
305 struct mlx5_vdpa_priv *priv = cb_arg;
306 #ifdef HAVE_IBV_DEVX_EVENT
308 struct mlx5dv_devx_async_event_hdr event_resp;
309 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
312 pthread_mutex_lock(&priv->vq_config_lock);
313 while (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,
315 (ssize_t)sizeof(out.event_resp.cookie)) {
316 struct mlx5_vdpa_cq *cq = (struct mlx5_vdpa_cq *)
317 (uintptr_t)out.event_resp.cookie;
318 struct mlx5_vdpa_event_qp *eqp = container_of(cq,
319 struct mlx5_vdpa_event_qp, cq);
320 struct mlx5_vdpa_virtq *virtq = container_of(eqp,
321 struct mlx5_vdpa_virtq, eqp);
325 mlx5_vdpa_cq_poll(cq);
326 /* Notify guest for descs consuming. */
327 if (cq->callfd != -1)
328 eventfd_write(cq->callfd, (eventfd_t)1);
329 if (priv->event_mode == MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT) {
330 mlx5_vdpa_cq_arm(priv, cq);
331 pthread_mutex_unlock(&priv->vq_config_lock);
334 /* Don't arm again - timer will take control. */
335 DRV_LOG(DEBUG, "Device %s virtq %d cq %d event was captured."
336 " Timer is %s, cq ci is %u.\n",
337 priv->vdev->device->name,
338 (int)virtq->index, cq->cq_obj.cq->id,
339 priv->timer_on ? "on" : "off", cq->cq_ci);
344 /* Traffic detected: make sure timer is on. */
345 priv->last_traffic_tic = rte_rdtsc();
346 pthread_mutex_lock(&priv->timer_lock);
347 if (!priv->timer_on) {
349 pthread_cond_signal(&priv->timer_cond);
351 pthread_mutex_unlock(&priv->timer_lock);
352 pthread_mutex_unlock(&priv->vq_config_lock);
356 mlx5_vdpa_err_interrupt_handler(void *cb_arg __rte_unused)
358 #ifdef HAVE_IBV_DEVX_EVENT
359 struct mlx5_vdpa_priv *priv = cb_arg;
361 struct mlx5dv_devx_async_event_hdr event_resp;
362 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
364 uint32_t vq_index, i, version;
365 struct mlx5_vdpa_virtq *virtq;
368 pthread_mutex_lock(&priv->vq_config_lock);
369 while (mlx5_glue->devx_get_event(priv->err_chnl, &out.event_resp,
371 (ssize_t)sizeof(out.event_resp.cookie)) {
372 vq_index = out.event_resp.cookie & UINT32_MAX;
373 version = out.event_resp.cookie >> 32;
374 if (vq_index >= priv->nr_virtqs) {
375 DRV_LOG(ERR, "Invalid device %s error event virtq %d.",
376 priv->vdev->device->name, vq_index);
379 virtq = &priv->virtqs[vq_index];
380 if (!virtq->enable || virtq->version != version)
382 if (rte_rdtsc() / rte_get_tsc_hz() < MLX5_VDPA_ERROR_TIME_SEC)
384 virtq->stopped = true;
385 /* Query error info. */
386 if (mlx5_vdpa_virtq_query(priv, vq_index))
389 if (mlx5_vdpa_virtq_enable(priv, vq_index, 0)) {
390 DRV_LOG(ERR, "Failed to disable virtq %d.", vq_index);
393 /* Retry if error happens less than N times in 3 seconds. */
394 sec = (rte_rdtsc() - virtq->err_time[0]) / rte_get_tsc_hz();
395 if (sec > MLX5_VDPA_ERROR_TIME_SEC) {
397 if (mlx5_vdpa_virtq_enable(priv, vq_index, 1))
398 DRV_LOG(ERR, "Failed to enable virtq %d.",
401 DRV_LOG(WARNING, "Recover virtq %d: %u.",
402 vq_index, ++virtq->n_retry);
404 /* Retry timeout, give up. */
405 DRV_LOG(ERR, "Device %s virtq %d failed to recover.",
406 priv->vdev->device->name, vq_index);
409 /* Shift in current time to error time log end. */
410 for (i = 1; i < RTE_DIM(virtq->err_time); i++)
411 virtq->err_time[i - 1] = virtq->err_time[i];
412 virtq->err_time[RTE_DIM(virtq->err_time) - 1] = rte_rdtsc();
414 pthread_mutex_unlock(&priv->vq_config_lock);
419 mlx5_vdpa_err_event_setup(struct mlx5_vdpa_priv *priv)
424 /* Setup device event channel. */
425 priv->err_chnl = mlx5_glue->devx_create_event_channel(priv->ctx, 0);
426 if (!priv->err_chnl) {
428 DRV_LOG(ERR, "Failed to create device event channel %d.",
432 flags = fcntl(priv->err_chnl->fd, F_GETFL);
433 ret = fcntl(priv->err_chnl->fd, F_SETFL, flags | O_NONBLOCK);
435 DRV_LOG(ERR, "Failed to change device event channel FD.");
438 priv->err_intr_handle.fd = priv->err_chnl->fd;
439 priv->err_intr_handle.type = RTE_INTR_HANDLE_EXT;
440 if (rte_intr_callback_register(&priv->err_intr_handle,
441 mlx5_vdpa_err_interrupt_handler,
443 priv->err_intr_handle.fd = 0;
444 DRV_LOG(ERR, "Failed to register error interrupt for device %d.",
448 DRV_LOG(DEBUG, "Registered error interrupt for device%d.",
453 mlx5_vdpa_err_event_unset(priv);
458 mlx5_vdpa_err_event_unset(struct mlx5_vdpa_priv *priv)
460 int retries = MLX5_VDPA_INTR_RETRIES;
463 if (!priv->err_intr_handle.fd)
465 while (retries-- && ret == -EAGAIN) {
466 ret = rte_intr_callback_unregister(&priv->err_intr_handle,
467 mlx5_vdpa_err_interrupt_handler,
469 if (ret == -EAGAIN) {
470 DRV_LOG(DEBUG, "Try again to unregister fd %d "
471 "of error interrupt, retries = %d.",
472 priv->err_intr_handle.fd, retries);
476 memset(&priv->err_intr_handle, 0, sizeof(priv->err_intr_handle));
477 if (priv->err_chnl) {
478 #ifdef HAVE_IBV_DEVX_EVENT
480 struct mlx5dv_devx_async_event_hdr event_resp;
481 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) +
485 /* Clean all pending events. */
486 while (mlx5_glue->devx_get_event(priv->err_chnl,
487 &out.event_resp, sizeof(out.buf)) >=
488 (ssize_t)sizeof(out.event_resp.cookie))
491 mlx5_glue->devx_destroy_event_channel(priv->err_chnl);
492 priv->err_chnl = NULL;
497 mlx5_vdpa_cqe_event_setup(struct mlx5_vdpa_priv *priv)
505 /* All virtqs are in poll mode. */
507 if (priv->event_mode != MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT) {
508 pthread_mutex_init(&priv->timer_lock, NULL);
509 pthread_cond_init(&priv->timer_cond, NULL);
511 pthread_attr_init(&attr);
513 if (priv->event_core != -1)
514 CPU_SET(priv->event_core, &cpuset);
516 cpuset = rte_lcore_cpuset(rte_get_main_lcore());
517 ret = pthread_attr_setaffinity_np(&attr, sizeof(cpuset),
520 DRV_LOG(ERR, "Failed to set thread affinity.");
523 ret = pthread_create(&priv->timer_tid, &attr,
524 mlx5_vdpa_poll_handle, (void *)priv);
526 DRV_LOG(ERR, "Failed to create timer thread.");
529 snprintf(name, sizeof(name), "vDPA-mlx5-%d", priv->vid);
530 ret = pthread_setname_np(priv->timer_tid, name);
532 DRV_LOG(ERR, "Failed to set timer thread name.");
536 priv->intr_handle.fd = priv->eventc->fd;
537 priv->intr_handle.type = RTE_INTR_HANDLE_EXT;
538 if (rte_intr_callback_register(&priv->intr_handle,
539 mlx5_vdpa_interrupt_handler, priv)) {
540 priv->intr_handle.fd = 0;
541 DRV_LOG(ERR, "Failed to register CQE interrupt %d.", rte_errno);
546 mlx5_vdpa_cqe_event_unset(priv);
551 mlx5_vdpa_cqe_event_unset(struct mlx5_vdpa_priv *priv)
553 int retries = MLX5_VDPA_INTR_RETRIES;
557 if (priv->intr_handle.fd) {
558 while (retries-- && ret == -EAGAIN) {
559 ret = rte_intr_callback_unregister(&priv->intr_handle,
560 mlx5_vdpa_interrupt_handler,
562 if (ret == -EAGAIN) {
563 DRV_LOG(DEBUG, "Try again to unregister fd %d "
564 "of CQ interrupt, retries = %d.",
565 priv->intr_handle.fd, retries);
569 memset(&priv->intr_handle, 0, sizeof(priv->intr_handle));
571 if (priv->timer_tid) {
572 pthread_cancel(priv->timer_tid);
573 pthread_join(priv->timer_tid, &status);
579 mlx5_vdpa_event_qp_destroy(struct mlx5_vdpa_event_qp *eqp)
582 claim_zero(mlx5_devx_cmd_destroy(eqp->sw_qp));
584 claim_zero(mlx5_glue->devx_umem_dereg(eqp->umem_obj));
586 rte_free(eqp->umem_buf);
588 claim_zero(mlx5_devx_cmd_destroy(eqp->fw_qp));
589 mlx5_vdpa_cq_destroy(&eqp->cq);
590 memset(eqp, 0, sizeof(*eqp));
594 mlx5_vdpa_qps2rts(struct mlx5_vdpa_event_qp *eqp)
596 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RST2INIT_QP,
598 DRV_LOG(ERR, "Failed to modify FW QP to INIT state(%u).",
602 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RST2INIT_QP,
604 DRV_LOG(ERR, "Failed to modify SW QP to INIT state(%u).",
608 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_INIT2RTR_QP,
610 DRV_LOG(ERR, "Failed to modify FW QP to RTR state(%u).",
614 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_INIT2RTR_QP,
616 DRV_LOG(ERR, "Failed to modify SW QP to RTR state(%u).",
620 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RTR2RTS_QP,
622 DRV_LOG(ERR, "Failed to modify FW QP to RTS state(%u).",
626 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RTR2RTS_QP,
628 DRV_LOG(ERR, "Failed to modify SW QP to RTS state(%u).",
636 mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,
637 int callfd, struct mlx5_vdpa_event_qp *eqp)
639 struct mlx5_devx_qp_attr attr = {0};
640 uint16_t log_desc_n = rte_log2_u32(desc_n);
641 uint32_t umem_size = (1 << log_desc_n) * MLX5_WSEG_SIZE +
642 sizeof(*eqp->db_rec) * 2;
644 if (mlx5_vdpa_event_qp_global_prepare(priv))
646 if (mlx5_vdpa_cq_create(priv, log_desc_n, callfd, &eqp->cq))
649 eqp->fw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
651 DRV_LOG(ERR, "Failed to create FW QP(%u).", rte_errno);
654 eqp->umem_buf = rte_zmalloc(__func__, umem_size, 4096);
655 if (!eqp->umem_buf) {
656 DRV_LOG(ERR, "Failed to allocate memory for SW QP.");
660 eqp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
661 (void *)(uintptr_t)eqp->umem_buf,
663 IBV_ACCESS_LOCAL_WRITE);
664 if (!eqp->umem_obj) {
665 DRV_LOG(ERR, "Failed to register umem for SW QP.");
668 attr.uar_index = priv->uar->page_id;
669 attr.cqn = eqp->cq.cq_obj.cq->id;
670 attr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE));
671 attr.rq_size = 1 << log_desc_n;
672 attr.log_rq_stride = rte_log2_u32(MLX5_WSEG_SIZE);
673 attr.sq_size = 0; /* No need SQ. */
674 attr.dbr_umem_valid = 1;
675 attr.wq_umem_id = eqp->umem_obj->umem_id;
676 attr.wq_umem_offset = 0;
677 attr.dbr_umem_id = eqp->umem_obj->umem_id;
678 attr.dbr_address = (1 << log_desc_n) * MLX5_WSEG_SIZE;
679 eqp->sw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
681 DRV_LOG(ERR, "Failed to create SW QP(%u).", rte_errno);
684 eqp->db_rec = RTE_PTR_ADD(eqp->umem_buf, (uintptr_t)attr.dbr_address);
685 if (mlx5_vdpa_qps2rts(eqp))
688 rte_write32(rte_cpu_to_be_32(1 << log_desc_n), &eqp->db_rec[0]);
691 mlx5_vdpa_event_qp_destroy(eqp);