1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
7 #include <sys/eventfd.h>
9 #include <rte_malloc.h>
10 #include <rte_errno.h>
11 #include <rte_lcore.h>
12 #include <rte_atomic.h>
13 #include <rte_common.h>
15 #include <rte_alarm.h>
17 #include <mlx5_common.h>
19 #include "mlx5_vdpa_utils.h"
20 #include "mlx5_vdpa.h"
24 mlx5_vdpa_event_qp_global_release(struct mlx5_vdpa_priv *priv)
27 mlx5_glue->devx_free_uar(priv->uar);
30 #ifdef HAVE_IBV_DEVX_EVENT
33 struct mlx5dv_devx_async_event_hdr event_resp;
34 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr)
38 /* Clean all pending events. */
39 while (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,
41 (ssize_t)sizeof(out.event_resp.cookie))
43 mlx5_glue->devx_destroy_event_channel(priv->eventc);
50 /* Prepare all the global resources for all the event objects.*/
52 mlx5_vdpa_event_qp_global_prepare(struct mlx5_vdpa_priv *priv)
56 if (mlx5_glue->devx_query_eqn(priv->ctx, 0, &priv->eqn)) {
58 DRV_LOG(ERR, "Failed to query EQ number %d.", rte_errno);
61 priv->eventc = mlx5_glue->devx_create_event_channel(priv->ctx,
62 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);
65 DRV_LOG(ERR, "Failed to create event channel %d.",
69 priv->uar = mlx5_glue->devx_alloc_uar(priv->ctx, 0);
72 DRV_LOG(ERR, "Failed to allocate UAR.");
77 mlx5_vdpa_event_qp_global_release(priv);
82 mlx5_vdpa_cq_destroy(struct mlx5_vdpa_cq *cq)
85 claim_zero(mlx5_devx_cmd_destroy(cq->cq));
87 claim_zero(mlx5_glue->devx_umem_dereg(cq->umem_obj));
89 rte_free((void *)(uintptr_t)cq->umem_buf);
90 memset(cq, 0, sizeof(*cq));
93 static inline void __rte_unused
94 mlx5_vdpa_cq_arm(struct mlx5_vdpa_priv *priv, struct mlx5_vdpa_cq *cq)
96 uint32_t arm_sn = cq->arm_sn << MLX5_CQ_SQN_OFFSET;
97 uint32_t cq_ci = cq->cq_ci & MLX5_CI_MASK;
98 uint32_t doorbell_hi = arm_sn | MLX5_CQ_DBR_CMD_ALL | cq_ci;
99 uint64_t doorbell = ((uint64_t)doorbell_hi << 32) | cq->cq->id;
100 uint64_t db_be = rte_cpu_to_be_64(doorbell);
101 uint32_t *addr = RTE_PTR_ADD(priv->uar->base_addr, MLX5_CQ_DOORBELL);
104 cq->db_rec[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
107 *(uint64_t *)addr = db_be;
109 *(uint32_t *)addr = db_be;
111 *((uint32_t *)addr + 1) = db_be >> 32;
118 mlx5_vdpa_cq_create(struct mlx5_vdpa_priv *priv, uint16_t log_desc_n,
119 int callfd, struct mlx5_vdpa_cq *cq)
121 struct mlx5_devx_cq_attr attr = {0};
122 size_t pgsize = sysconf(_SC_PAGESIZE);
124 uint16_t event_nums[1] = {0};
125 uint16_t cq_size = 1 << log_desc_n;
128 cq->log_desc_n = log_desc_n;
129 umem_size = sizeof(struct mlx5_cqe) * cq_size + sizeof(*cq->db_rec) * 2;
130 cq->umem_buf = rte_zmalloc(__func__, umem_size, 4096);
132 DRV_LOG(ERR, "Failed to allocate memory for CQ.");
136 cq->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
137 (void *)(uintptr_t)cq->umem_buf,
139 IBV_ACCESS_LOCAL_WRITE);
141 DRV_LOG(ERR, "Failed to register umem for CQ.");
144 attr.q_umem_valid = 1;
145 attr.db_umem_valid = 1;
146 attr.use_first_only = 1;
147 attr.overrun_ignore = 0;
148 attr.uar_page_id = priv->uar->page_id;
149 attr.q_umem_id = cq->umem_obj->umem_id;
150 attr.q_umem_offset = 0;
151 attr.db_umem_id = cq->umem_obj->umem_id;
152 attr.db_umem_offset = sizeof(struct mlx5_cqe) * cq_size;
153 attr.eqn = priv->eqn;
154 attr.log_cq_size = log_desc_n;
155 attr.log_page_size = rte_log2_u32(pgsize);
156 cq->cq = mlx5_devx_cmd_create_cq(priv->ctx, &attr);
159 cq->db_rec = RTE_PTR_ADD(cq->umem_buf, (uintptr_t)attr.db_umem_offset);
161 rte_spinlock_init(&cq->sl);
162 /* Subscribe CQ event to the event channel controlled by the driver. */
163 ret = mlx5_glue->devx_subscribe_devx_event(priv->eventc, cq->cq->obj,
166 (uint64_t)(uintptr_t)cq);
168 DRV_LOG(ERR, "Failed to subscribe CQE event.");
173 /* Init CQ to ones to be in HW owner in the start. */
174 cq->cqes[0].op_own = MLX5_CQE_OWNER_MASK;
175 cq->cqes[0].wqe_counter = rte_cpu_to_be_16(cq_size - 1);
177 mlx5_vdpa_cq_arm(priv, cq);
180 mlx5_vdpa_cq_destroy(cq);
184 static inline uint32_t
185 mlx5_vdpa_cq_poll(struct mlx5_vdpa_cq *cq)
187 struct mlx5_vdpa_event_qp *eqp =
188 container_of(cq, struct mlx5_vdpa_event_qp, cq);
189 const unsigned int cq_size = 1 << cq->log_desc_n;
190 const unsigned int cq_mask = cq_size - 1;
193 uint16_t wqe_counter;
199 uint16_t next_wqe_counter = cq->cq_ci & cq_mask;
200 uint16_t cur_wqe_counter;
203 last_word.word = rte_read32(&cq->cqes[0].wqe_counter);
204 cur_wqe_counter = rte_be_to_cpu_16(last_word.wqe_counter);
205 comp = (cur_wqe_counter + 1u - next_wqe_counter) & cq_mask;
208 MLX5_ASSERT(!!(cq->cq_ci & cq_size) ==
209 MLX5_CQE_OWNER(last_word.op_own));
210 MLX5_ASSERT(MLX5_CQE_OPCODE(last_word.op_own) !=
212 if (unlikely(!(MLX5_CQE_OPCODE(last_word.op_own) ==
214 MLX5_CQE_OPCODE(last_word.op_own) ==
218 /* Ring CQ doorbell record. */
219 cq->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
221 /* Ring SW QP doorbell record. */
222 eqp->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci + cq_size);
228 mlx5_vdpa_arm_all_cqs(struct mlx5_vdpa_priv *priv)
230 struct mlx5_vdpa_cq *cq;
233 for (i = 0; i < priv->nr_virtqs; i++) {
234 cq = &priv->virtqs[i].eqp.cq;
235 if (cq->cq && !cq->armed)
236 mlx5_vdpa_cq_arm(priv, cq);
241 mlx5_vdpa_timer_sleep(struct mlx5_vdpa_priv *priv, uint32_t max)
243 if (priv->event_mode == MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER) {
246 priv->timer_delay_us += priv->event_us;
251 priv->timer_delay_us /= max;
255 usleep(priv->timer_delay_us);
259 mlx5_vdpa_poll_handle(void *arg)
261 struct mlx5_vdpa_priv *priv = arg;
263 struct mlx5_vdpa_cq *cq;
265 uint64_t current_tic;
267 pthread_mutex_lock(&priv->timer_lock);
268 while (!priv->timer_on)
269 pthread_cond_wait(&priv->timer_cond, &priv->timer_lock);
270 pthread_mutex_unlock(&priv->timer_lock);
271 priv->timer_delay_us = priv->event_mode ==
272 MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER ?
273 MLX5_VDPA_DEFAULT_TIMER_DELAY_US :
277 pthread_mutex_lock(&priv->vq_config_lock);
278 for (i = 0; i < priv->nr_virtqs; i++) {
279 cq = &priv->virtqs[i].eqp.cq;
280 if (cq->cq && !cq->armed) {
281 uint32_t comp = mlx5_vdpa_cq_poll(cq);
284 /* Notify guest for descs consuming. */
285 if (cq->callfd != -1)
286 eventfd_write(cq->callfd,
293 current_tic = rte_rdtsc();
295 /* No traffic ? stop timer and load interrupts. */
296 if (current_tic - priv->last_traffic_tic >=
297 rte_get_timer_hz() * priv->no_traffic_time_s) {
298 DRV_LOG(DEBUG, "Device %s traffic was stopped.",
299 priv->vdev->device->name);
300 mlx5_vdpa_arm_all_cqs(priv);
301 pthread_mutex_unlock(&priv->vq_config_lock);
302 pthread_mutex_lock(&priv->timer_lock);
304 while (!priv->timer_on)
305 pthread_cond_wait(&priv->timer_cond,
307 pthread_mutex_unlock(&priv->timer_lock);
308 priv->timer_delay_us = priv->event_mode ==
309 MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER ?
310 MLX5_VDPA_DEFAULT_TIMER_DELAY_US :
315 priv->last_traffic_tic = current_tic;
317 pthread_mutex_unlock(&priv->vq_config_lock);
318 mlx5_vdpa_timer_sleep(priv, max);
324 mlx5_vdpa_interrupt_handler(void *cb_arg)
326 struct mlx5_vdpa_priv *priv = cb_arg;
327 #ifdef HAVE_IBV_DEVX_EVENT
329 struct mlx5dv_devx_async_event_hdr event_resp;
330 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
333 pthread_mutex_lock(&priv->vq_config_lock);
334 while (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,
336 (ssize_t)sizeof(out.event_resp.cookie)) {
337 struct mlx5_vdpa_cq *cq = (struct mlx5_vdpa_cq *)
338 (uintptr_t)out.event_resp.cookie;
339 struct mlx5_vdpa_event_qp *eqp = container_of(cq,
340 struct mlx5_vdpa_event_qp, cq);
341 struct mlx5_vdpa_virtq *virtq = container_of(eqp,
342 struct mlx5_vdpa_virtq, eqp);
346 mlx5_vdpa_cq_poll(cq);
347 /* Notify guest for descs consuming. */
348 if (cq->callfd != -1)
349 eventfd_write(cq->callfd, (eventfd_t)1);
350 if (priv->event_mode == MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT) {
351 mlx5_vdpa_cq_arm(priv, cq);
352 pthread_mutex_unlock(&priv->vq_config_lock);
355 /* Don't arm again - timer will take control. */
356 DRV_LOG(DEBUG, "Device %s virtq %d cq %d event was captured."
357 " Timer is %s, cq ci is %u.\n",
358 priv->vdev->device->name,
359 (int)virtq->index, cq->cq->id,
360 priv->timer_on ? "on" : "off", cq->cq_ci);
365 /* Traffic detected: make sure timer is on. */
366 priv->last_traffic_tic = rte_rdtsc();
367 pthread_mutex_lock(&priv->timer_lock);
368 if (!priv->timer_on) {
370 pthread_cond_signal(&priv->timer_cond);
372 pthread_mutex_unlock(&priv->timer_lock);
373 pthread_mutex_unlock(&priv->vq_config_lock);
377 mlx5_vdpa_cqe_event_setup(struct mlx5_vdpa_priv *priv)
383 /* All virtqs are in poll mode. */
385 if (priv->event_mode != MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT) {
386 pthread_mutex_init(&priv->timer_lock, NULL);
387 pthread_cond_init(&priv->timer_cond, NULL);
389 ret = pthread_create(&priv->timer_tid, NULL,
390 mlx5_vdpa_poll_handle, (void *)priv);
392 DRV_LOG(ERR, "Failed to create timer thread.");
396 flags = fcntl(priv->eventc->fd, F_GETFL);
397 ret = fcntl(priv->eventc->fd, F_SETFL, flags | O_NONBLOCK);
399 DRV_LOG(ERR, "Failed to change event channel FD.");
402 priv->intr_handle.fd = priv->eventc->fd;
403 priv->intr_handle.type = RTE_INTR_HANDLE_EXT;
404 if (rte_intr_callback_register(&priv->intr_handle,
405 mlx5_vdpa_interrupt_handler, priv)) {
406 priv->intr_handle.fd = 0;
407 DRV_LOG(ERR, "Failed to register CQE interrupt %d.", rte_errno);
412 mlx5_vdpa_cqe_event_unset(priv);
417 mlx5_vdpa_cqe_event_unset(struct mlx5_vdpa_priv *priv)
419 int retries = MLX5_VDPA_INTR_RETRIES;
423 if (priv->intr_handle.fd) {
424 while (retries-- && ret == -EAGAIN) {
425 ret = rte_intr_callback_unregister(&priv->intr_handle,
426 mlx5_vdpa_interrupt_handler,
428 if (ret == -EAGAIN) {
429 DRV_LOG(DEBUG, "Try again to unregister fd %d "
430 "of CQ interrupt, retries = %d.",
431 priv->intr_handle.fd, retries);
435 memset(&priv->intr_handle, 0, sizeof(priv->intr_handle));
437 if (priv->timer_tid) {
438 pthread_cancel(priv->timer_tid);
439 pthread_join(priv->timer_tid, &status);
445 mlx5_vdpa_event_qp_destroy(struct mlx5_vdpa_event_qp *eqp)
448 claim_zero(mlx5_devx_cmd_destroy(eqp->sw_qp));
450 claim_zero(mlx5_glue->devx_umem_dereg(eqp->umem_obj));
452 rte_free(eqp->umem_buf);
454 claim_zero(mlx5_devx_cmd_destroy(eqp->fw_qp));
455 mlx5_vdpa_cq_destroy(&eqp->cq);
456 memset(eqp, 0, sizeof(*eqp));
460 mlx5_vdpa_qps2rts(struct mlx5_vdpa_event_qp *eqp)
462 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RST2INIT_QP,
464 DRV_LOG(ERR, "Failed to modify FW QP to INIT state(%u).",
468 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RST2INIT_QP,
470 DRV_LOG(ERR, "Failed to modify SW QP to INIT state(%u).",
474 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_INIT2RTR_QP,
476 DRV_LOG(ERR, "Failed to modify FW QP to RTR state(%u).",
480 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_INIT2RTR_QP,
482 DRV_LOG(ERR, "Failed to modify SW QP to RTR state(%u).",
486 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RTR2RTS_QP,
488 DRV_LOG(ERR, "Failed to modify FW QP to RTS state(%u).",
492 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RTR2RTS_QP,
494 DRV_LOG(ERR, "Failed to modify SW QP to RTS state(%u).",
502 mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,
503 int callfd, struct mlx5_vdpa_event_qp *eqp)
505 struct mlx5_devx_qp_attr attr = {0};
506 uint16_t log_desc_n = rte_log2_u32(desc_n);
507 uint32_t umem_size = (1 << log_desc_n) * MLX5_WSEG_SIZE +
508 sizeof(*eqp->db_rec) * 2;
510 if (mlx5_vdpa_event_qp_global_prepare(priv))
512 if (mlx5_vdpa_cq_create(priv, log_desc_n, callfd, &eqp->cq))
515 eqp->fw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
517 DRV_LOG(ERR, "Failed to create FW QP(%u).", rte_errno);
520 eqp->umem_buf = rte_zmalloc(__func__, umem_size, 4096);
521 if (!eqp->umem_buf) {
522 DRV_LOG(ERR, "Failed to allocate memory for SW QP.");
526 eqp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
527 (void *)(uintptr_t)eqp->umem_buf,
529 IBV_ACCESS_LOCAL_WRITE);
530 if (!eqp->umem_obj) {
531 DRV_LOG(ERR, "Failed to register umem for SW QP.");
534 attr.uar_index = priv->uar->page_id;
535 attr.cqn = eqp->cq.cq->id;
536 attr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE));
537 attr.rq_size = 1 << log_desc_n;
538 attr.log_rq_stride = rte_log2_u32(MLX5_WSEG_SIZE);
539 attr.sq_size = 0; /* No need SQ. */
540 attr.dbr_umem_valid = 1;
541 attr.wq_umem_id = eqp->umem_obj->umem_id;
542 attr.wq_umem_offset = 0;
543 attr.dbr_umem_id = eqp->umem_obj->umem_id;
544 attr.dbr_address = (1 << log_desc_n) * MLX5_WSEG_SIZE;
545 eqp->sw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
547 DRV_LOG(ERR, "Failed to create SW QP(%u).", rte_errno);
550 eqp->db_rec = RTE_PTR_ADD(eqp->umem_buf, (uintptr_t)attr.dbr_address);
551 if (mlx5_vdpa_qps2rts(eqp))
554 rte_write32(rte_cpu_to_be_32(1 << log_desc_n), &eqp->db_rec[0]);
557 mlx5_vdpa_event_qp_destroy(eqp);