1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
8 #include <sys/eventfd.h>
10 #include <rte_malloc.h>
11 #include <rte_memory.h>
12 #include <rte_errno.h>
13 #include <rte_lcore.h>
14 #include <rte_atomic.h>
15 #include <rte_common.h>
17 #include <rte_alarm.h>
19 #include <mlx5_common.h>
20 #include <mlx5_common_os.h>
21 #include <mlx5_common_devx.h>
22 #include <mlx5_glue.h>
24 #include "mlx5_vdpa_utils.h"
25 #include "mlx5_vdpa.h"
28 #define MLX5_VDPA_ERROR_TIME_SEC 3u
31 mlx5_vdpa_event_qp_global_release(struct mlx5_vdpa_priv *priv)
33 mlx5_devx_uar_release(&priv->uar);
34 #ifdef HAVE_IBV_DEVX_EVENT
36 mlx5_os_devx_destroy_event_channel(priv->eventc);
42 /* Prepare all the global resources for all the event objects.*/
44 mlx5_vdpa_event_qp_global_prepare(struct mlx5_vdpa_priv *priv)
46 priv->eventc = mlx5_os_devx_create_event_channel(priv->cdev->ctx,
47 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);
50 DRV_LOG(ERR, "Failed to create event channel %d.",
54 if (mlx5_devx_uar_prepare(priv->cdev, &priv->uar) != 0) {
55 DRV_LOG(ERR, "Failed to allocate UAR.");
60 mlx5_vdpa_event_qp_global_release(priv);
65 mlx5_vdpa_cq_destroy(struct mlx5_vdpa_cq *cq)
67 mlx5_devx_cq_destroy(&cq->cq_obj);
68 memset(cq, 0, sizeof(*cq));
71 static inline void __rte_unused
72 mlx5_vdpa_cq_arm(struct mlx5_vdpa_priv *priv, struct mlx5_vdpa_cq *cq)
74 uint32_t arm_sn = cq->arm_sn << MLX5_CQ_SQN_OFFSET;
75 uint32_t cq_ci = cq->cq_ci & MLX5_CI_MASK;
76 uint32_t doorbell_hi = arm_sn | MLX5_CQ_DBR_CMD_ALL | cq_ci;
77 uint64_t doorbell = ((uint64_t)doorbell_hi << 32) | cq->cq_obj.cq->id;
78 uint64_t db_be = rte_cpu_to_be_64(doorbell);
80 mlx5_doorbell_ring(&priv->uar.cq_db, db_be, doorbell_hi,
81 &cq->cq_obj.db_rec[MLX5_CQ_ARM_DB], 0);
87 mlx5_vdpa_cq_create(struct mlx5_vdpa_priv *priv, uint16_t log_desc_n,
88 int callfd, struct mlx5_vdpa_cq *cq)
90 struct mlx5_devx_cq_attr attr = {
92 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar.obj),
94 uint16_t event_nums[1] = {0};
97 ret = mlx5_devx_cq_create(priv->cdev->ctx, &cq->cq_obj, log_desc_n,
98 &attr, SOCKET_ID_ANY);
102 cq->log_desc_n = log_desc_n;
103 rte_spinlock_init(&cq->sl);
104 /* Subscribe CQ event to the event channel controlled by the driver. */
105 ret = mlx5_os_devx_subscribe_devx_event(priv->eventc,
107 sizeof(event_nums), event_nums,
108 (uint64_t)(uintptr_t)cq);
110 DRV_LOG(ERR, "Failed to subscribe CQE event.");
115 /* Init CQ to ones to be in HW owner in the start. */
116 cq->cq_obj.cqes[0].op_own = MLX5_CQE_OWNER_MASK;
117 cq->cq_obj.cqes[0].wqe_counter = rte_cpu_to_be_16(UINT16_MAX);
119 mlx5_vdpa_cq_arm(priv, cq);
122 mlx5_vdpa_cq_destroy(cq);
126 static inline uint32_t
127 mlx5_vdpa_cq_poll(struct mlx5_vdpa_cq *cq)
129 struct mlx5_vdpa_event_qp *eqp =
130 container_of(cq, struct mlx5_vdpa_event_qp, cq);
131 const unsigned int cq_size = 1 << cq->log_desc_n;
134 uint16_t wqe_counter;
140 uint16_t next_wqe_counter = cq->cq_ci;
141 uint16_t cur_wqe_counter;
144 last_word.word = rte_read32(&cq->cq_obj.cqes[0].wqe_counter);
145 cur_wqe_counter = rte_be_to_cpu_16(last_word.wqe_counter);
146 comp = cur_wqe_counter + (uint16_t)1 - next_wqe_counter;
149 MLX5_ASSERT(MLX5_CQE_OPCODE(last_word.op_own) !=
151 if (unlikely(!(MLX5_CQE_OPCODE(last_word.op_own) ==
153 MLX5_CQE_OPCODE(last_word.op_own) ==
157 /* Ring CQ doorbell record. */
158 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
160 /* Ring SW QP doorbell record. */
161 eqp->sw_qp.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci + cq_size);
167 mlx5_vdpa_arm_all_cqs(struct mlx5_vdpa_priv *priv)
169 struct mlx5_vdpa_cq *cq;
172 for (i = 0; i < priv->nr_virtqs; i++) {
173 cq = &priv->virtqs[i].eqp.cq;
174 if (cq->cq_obj.cq && !cq->armed)
175 mlx5_vdpa_cq_arm(priv, cq);
180 mlx5_vdpa_timer_sleep(struct mlx5_vdpa_priv *priv, uint32_t max)
182 if (priv->event_mode == MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER) {
185 priv->timer_delay_us += priv->event_us;
190 priv->timer_delay_us /= max;
194 if (priv->timer_delay_us)
195 usleep(priv->timer_delay_us);
197 /* Give-up CPU to improve polling threads scheduling. */
201 /* Notify virtio device for specific virtq new traffic. */
203 mlx5_vdpa_queue_complete(struct mlx5_vdpa_cq *cq)
208 comp = mlx5_vdpa_cq_poll(cq);
210 if (cq->callfd != -1)
211 eventfd_write(cq->callfd, (eventfd_t)1);
218 /* Notify virtio device for any virtq new traffic. */
220 mlx5_vdpa_queues_complete(struct mlx5_vdpa_priv *priv)
225 for (i = 0; i < priv->nr_virtqs; i++) {
226 struct mlx5_vdpa_cq *cq = &priv->virtqs[i].eqp.cq;
227 uint32_t comp = mlx5_vdpa_queue_complete(cq);
235 /* Wait on all CQs channel for completion event. */
236 static struct mlx5_vdpa_cq *
237 mlx5_vdpa_event_wait(struct mlx5_vdpa_priv *priv __rte_unused)
239 #ifdef HAVE_IBV_DEVX_EVENT
241 struct mlx5dv_devx_async_event_hdr event_resp;
242 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
244 int ret = mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,
248 return (struct mlx5_vdpa_cq *)(uintptr_t)out.event_resp.cookie;
249 DRV_LOG(INFO, "Got error in devx_get_event, ret = %d, errno = %d.",
256 mlx5_vdpa_event_handle(void *arg)
258 struct mlx5_vdpa_priv *priv = arg;
259 struct mlx5_vdpa_cq *cq;
262 switch (priv->event_mode) {
263 case MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER:
264 case MLX5_VDPA_EVENT_MODE_FIXED_TIMER:
265 priv->timer_delay_us = priv->event_us;
267 pthread_mutex_lock(&priv->vq_config_lock);
268 max = mlx5_vdpa_queues_complete(priv);
269 if (max == 0 && priv->no_traffic_counter++ >=
270 priv->no_traffic_max) {
271 DRV_LOG(DEBUG, "Device %s traffic was stopped.",
272 priv->vdev->device->name);
273 mlx5_vdpa_arm_all_cqs(priv);
276 (&priv->vq_config_lock);
277 cq = mlx5_vdpa_event_wait(priv);
279 (&priv->vq_config_lock);
281 mlx5_vdpa_queue_complete(cq) > 0)
284 priv->timer_delay_us = priv->event_us;
285 priv->no_traffic_counter = 0;
286 } else if (max != 0) {
287 priv->no_traffic_counter = 0;
289 pthread_mutex_unlock(&priv->vq_config_lock);
290 mlx5_vdpa_timer_sleep(priv, max);
293 case MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT:
295 cq = mlx5_vdpa_event_wait(priv);
297 pthread_mutex_lock(&priv->vq_config_lock);
298 if (mlx5_vdpa_queue_complete(cq) > 0)
299 mlx5_vdpa_cq_arm(priv, cq);
300 pthread_mutex_unlock(&priv->vq_config_lock);
310 mlx5_vdpa_err_interrupt_handler(void *cb_arg __rte_unused)
312 #ifdef HAVE_IBV_DEVX_EVENT
313 struct mlx5_vdpa_priv *priv = cb_arg;
315 struct mlx5dv_devx_async_event_hdr event_resp;
316 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
318 uint32_t vq_index, i, version;
319 struct mlx5_vdpa_virtq *virtq;
322 pthread_mutex_lock(&priv->vq_config_lock);
323 while (mlx5_glue->devx_get_event(priv->err_chnl, &out.event_resp,
325 (ssize_t)sizeof(out.event_resp.cookie)) {
326 vq_index = out.event_resp.cookie & UINT32_MAX;
327 version = out.event_resp.cookie >> 32;
328 if (vq_index >= priv->nr_virtqs) {
329 DRV_LOG(ERR, "Invalid device %s error event virtq %d.",
330 priv->vdev->device->name, vq_index);
333 virtq = &priv->virtqs[vq_index];
334 if (!virtq->enable || virtq->version != version)
336 if (rte_rdtsc() / rte_get_tsc_hz() < MLX5_VDPA_ERROR_TIME_SEC)
338 virtq->stopped = true;
339 /* Query error info. */
340 if (mlx5_vdpa_virtq_query(priv, vq_index))
343 if (mlx5_vdpa_virtq_enable(priv, vq_index, 0)) {
344 DRV_LOG(ERR, "Failed to disable virtq %d.", vq_index);
347 /* Retry if error happens less than N times in 3 seconds. */
348 sec = (rte_rdtsc() - virtq->err_time[0]) / rte_get_tsc_hz();
349 if (sec > MLX5_VDPA_ERROR_TIME_SEC) {
351 if (mlx5_vdpa_virtq_enable(priv, vq_index, 1))
352 DRV_LOG(ERR, "Failed to enable virtq %d.",
355 DRV_LOG(WARNING, "Recover virtq %d: %u.",
356 vq_index, ++virtq->n_retry);
358 /* Retry timeout, give up. */
359 DRV_LOG(ERR, "Device %s virtq %d failed to recover.",
360 priv->vdev->device->name, vq_index);
363 /* Shift in current time to error time log end. */
364 for (i = 1; i < RTE_DIM(virtq->err_time); i++)
365 virtq->err_time[i - 1] = virtq->err_time[i];
366 virtq->err_time[RTE_DIM(virtq->err_time) - 1] = rte_rdtsc();
368 pthread_mutex_unlock(&priv->vq_config_lock);
373 mlx5_vdpa_err_event_setup(struct mlx5_vdpa_priv *priv)
378 /* Setup device event channel. */
379 priv->err_chnl = mlx5_glue->devx_create_event_channel(priv->cdev->ctx,
381 if (!priv->err_chnl) {
383 DRV_LOG(ERR, "Failed to create device event channel %d.",
387 flags = fcntl(priv->err_chnl->fd, F_GETFL);
388 ret = fcntl(priv->err_chnl->fd, F_SETFL, flags | O_NONBLOCK);
391 DRV_LOG(ERR, "Failed to change device event channel FD.");
394 priv->err_intr_handle =
395 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
396 if (priv->err_intr_handle == NULL) {
397 DRV_LOG(ERR, "Fail to allocate intr_handle");
400 if (rte_intr_fd_set(priv->err_intr_handle, priv->err_chnl->fd))
403 if (rte_intr_type_set(priv->err_intr_handle, RTE_INTR_HANDLE_EXT))
406 ret = rte_intr_callback_register(priv->err_intr_handle,
407 mlx5_vdpa_err_interrupt_handler,
410 rte_intr_fd_set(priv->err_intr_handle, 0);
411 DRV_LOG(ERR, "Failed to register error interrupt for device %d.",
416 DRV_LOG(DEBUG, "Registered error interrupt for device%d.",
421 mlx5_vdpa_err_event_unset(priv);
426 mlx5_vdpa_err_event_unset(struct mlx5_vdpa_priv *priv)
428 int retries = MLX5_VDPA_INTR_RETRIES;
431 if (!rte_intr_fd_get(priv->err_intr_handle))
433 while (retries-- && ret == -EAGAIN) {
434 ret = rte_intr_callback_unregister(priv->err_intr_handle,
435 mlx5_vdpa_err_interrupt_handler,
437 if (ret == -EAGAIN) {
438 DRV_LOG(DEBUG, "Try again to unregister fd %d "
439 "of error interrupt, retries = %d.",
440 rte_intr_fd_get(priv->err_intr_handle),
445 if (priv->err_chnl) {
446 #ifdef HAVE_IBV_DEVX_EVENT
448 struct mlx5dv_devx_async_event_hdr event_resp;
449 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) +
453 /* Clean all pending events. */
454 while (mlx5_glue->devx_get_event(priv->err_chnl,
455 &out.event_resp, sizeof(out.buf)) >=
456 (ssize_t)sizeof(out.event_resp.cookie))
459 mlx5_glue->devx_destroy_event_channel(priv->err_chnl);
460 priv->err_chnl = NULL;
462 rte_intr_instance_free(priv->err_intr_handle);
466 mlx5_vdpa_cqe_event_setup(struct mlx5_vdpa_priv *priv)
472 const struct sched_param sp = {
473 .sched_priority = sched_get_priority_max(SCHED_RR),
477 /* All virtqs are in poll mode. */
479 pthread_attr_init(&attr);
480 ret = pthread_attr_setschedpolicy(&attr, SCHED_RR);
482 DRV_LOG(ERR, "Failed to set thread sched policy = RR.");
485 ret = pthread_attr_setschedparam(&attr, &sp);
487 DRV_LOG(ERR, "Failed to set thread priority.");
490 ret = pthread_create(&priv->timer_tid, &attr, mlx5_vdpa_event_handle,
493 DRV_LOG(ERR, "Failed to create timer thread.");
497 if (priv->event_core != -1)
498 CPU_SET(priv->event_core, &cpuset);
500 cpuset = rte_lcore_cpuset(rte_get_main_lcore());
501 ret = pthread_setaffinity_np(priv->timer_tid, sizeof(cpuset), &cpuset);
503 DRV_LOG(ERR, "Failed to set thread affinity.");
506 snprintf(name, sizeof(name), "vDPA-mlx5-%d", priv->vid);
507 ret = rte_thread_setname(priv->timer_tid, name);
509 DRV_LOG(DEBUG, "Cannot set timer thread name.");
514 mlx5_vdpa_cqe_event_unset(struct mlx5_vdpa_priv *priv)
518 if (priv->timer_tid) {
519 pthread_cancel(priv->timer_tid);
520 pthread_join(priv->timer_tid, &status);
526 mlx5_vdpa_event_qp_destroy(struct mlx5_vdpa_event_qp *eqp)
528 mlx5_devx_qp_destroy(&eqp->sw_qp);
530 claim_zero(mlx5_devx_cmd_destroy(eqp->fw_qp));
531 mlx5_vdpa_cq_destroy(&eqp->cq);
532 memset(eqp, 0, sizeof(*eqp));
536 mlx5_vdpa_qps2rts(struct mlx5_vdpa_event_qp *eqp)
538 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RST2INIT_QP,
539 eqp->sw_qp.qp->id)) {
540 DRV_LOG(ERR, "Failed to modify FW QP to INIT state(%u).",
544 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp.qp,
545 MLX5_CMD_OP_RST2INIT_QP, eqp->fw_qp->id)) {
546 DRV_LOG(ERR, "Failed to modify SW QP to INIT state(%u).",
550 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_INIT2RTR_QP,
551 eqp->sw_qp.qp->id)) {
552 DRV_LOG(ERR, "Failed to modify FW QP to RTR state(%u).",
556 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp.qp,
557 MLX5_CMD_OP_INIT2RTR_QP, eqp->fw_qp->id)) {
558 DRV_LOG(ERR, "Failed to modify SW QP to RTR state(%u).",
562 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RTR2RTS_QP,
563 eqp->sw_qp.qp->id)) {
564 DRV_LOG(ERR, "Failed to modify FW QP to RTS state(%u).",
568 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp.qp, MLX5_CMD_OP_RTR2RTS_QP,
570 DRV_LOG(ERR, "Failed to modify SW QP to RTS state(%u).",
578 mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,
579 int callfd, struct mlx5_vdpa_event_qp *eqp)
581 struct mlx5_devx_qp_attr attr = {0};
582 uint16_t log_desc_n = rte_log2_u32(desc_n);
585 if (mlx5_vdpa_cq_create(priv, log_desc_n, callfd, &eqp->cq))
587 attr.pd = priv->cdev->pdn;
589 mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format);
590 eqp->fw_qp = mlx5_devx_cmd_create_qp(priv->cdev->ctx, &attr);
592 DRV_LOG(ERR, "Failed to create FW QP(%u).", rte_errno);
595 attr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar.obj);
596 attr.cqn = eqp->cq.cq_obj.cq->id;
597 attr.num_of_receive_wqes = RTE_BIT32(log_desc_n);
598 attr.log_rq_stride = rte_log2_u32(MLX5_WSEG_SIZE);
599 attr.num_of_send_wqbbs = 0; /* No need SQ. */
601 mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format);
602 ret = mlx5_devx_qp_create(priv->cdev->ctx, &(eqp->sw_qp),
603 attr.num_of_receive_wqes *
604 MLX5_WSEG_SIZE, &attr, SOCKET_ID_ANY);
606 DRV_LOG(ERR, "Failed to create SW QP(%u).", rte_errno);
609 if (mlx5_vdpa_qps2rts(eqp))
612 rte_write32(rte_cpu_to_be_32(RTE_BIT32(log_desc_n)),
613 &eqp->sw_qp.db_rec[0]);
616 mlx5_vdpa_event_qp_destroy(eqp);