8a01e4279497d77bdceca51b33b86f546ff3b74d
[dpdk.git] / drivers / vdpa / mlx5 / mlx5_vdpa_event.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright 2019 Mellanox Technologies, Ltd
3  */
4 #include <unistd.h>
5 #include <stdint.h>
6 #include <fcntl.h>
7 #include <sys/eventfd.h>
8
9 #include <rte_malloc.h>
10 #include <rte_errno.h>
11 #include <rte_lcore.h>
12 #include <rte_atomic.h>
13 #include <rte_common.h>
14 #include <rte_io.h>
15 #include <rte_alarm.h>
16
17 #include <mlx5_common.h>
18
19 #include "mlx5_vdpa_utils.h"
20 #include "mlx5_vdpa.h"
21
22
23 void
24 mlx5_vdpa_event_qp_global_release(struct mlx5_vdpa_priv *priv)
25 {
26         if (priv->uar) {
27                 mlx5_glue->devx_free_uar(priv->uar);
28                 priv->uar = NULL;
29         }
30 #ifdef HAVE_IBV_DEVX_EVENT
31         if (priv->eventc) {
32                 union {
33                         struct mlx5dv_devx_async_event_hdr event_resp;
34                         uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr)
35                                                                          + 128];
36                 } out;
37
38                 /* Clean all pending events. */
39                 while (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,
40                        sizeof(out.buf)) >=
41                        (ssize_t)sizeof(out.event_resp.cookie))
42                         ;
43                 mlx5_glue->devx_destroy_event_channel(priv->eventc);
44                 priv->eventc = NULL;
45         }
46 #endif
47         priv->eqn = 0;
48 }
49
50 /* Prepare all the global resources for all the event objects.*/
51 static int
52 mlx5_vdpa_event_qp_global_prepare(struct mlx5_vdpa_priv *priv)
53 {
54         int flags, ret;
55
56         if (priv->eventc)
57                 return 0;
58         if (mlx5_glue->devx_query_eqn(priv->ctx, 0, &priv->eqn)) {
59                 rte_errno = errno;
60                 DRV_LOG(ERR, "Failed to query EQ number %d.", rte_errno);
61                 return -1;
62         }
63         priv->eventc = mlx5_glue->devx_create_event_channel(priv->ctx,
64                            MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);
65         if (!priv->eventc) {
66                 rte_errno = errno;
67                 DRV_LOG(ERR, "Failed to create event channel %d.",
68                         rte_errno);
69                 goto error;
70         }
71         flags = fcntl(priv->eventc->fd, F_GETFL);
72         ret = fcntl(priv->eventc->fd, F_SETFL, flags | O_NONBLOCK);
73         if (ret) {
74                 DRV_LOG(ERR, "Failed to change event channel FD.");
75                 goto error;
76         }
77         priv->uar = mlx5_glue->devx_alloc_uar(priv->ctx, 0);
78         if (!priv->uar) {
79                 rte_errno = errno;
80                 DRV_LOG(ERR, "Failed to allocate UAR.");
81                 goto error;
82         }
83         return 0;
84 error:
85         mlx5_vdpa_event_qp_global_release(priv);
86         return -1;
87 }
88
89 static void
90 mlx5_vdpa_cq_destroy(struct mlx5_vdpa_cq *cq)
91 {
92         if (cq->cq)
93                 claim_zero(mlx5_devx_cmd_destroy(cq->cq));
94         if (cq->umem_obj)
95                 claim_zero(mlx5_glue->devx_umem_dereg(cq->umem_obj));
96         if (cq->umem_buf)
97                 rte_free((void *)(uintptr_t)cq->umem_buf);
98         memset(cq, 0, sizeof(*cq));
99 }
100
101 static inline void __rte_unused
102 mlx5_vdpa_cq_arm(struct mlx5_vdpa_priv *priv, struct mlx5_vdpa_cq *cq)
103 {
104         uint32_t arm_sn = cq->arm_sn << MLX5_CQ_SQN_OFFSET;
105         uint32_t cq_ci = cq->cq_ci & MLX5_CI_MASK;
106         uint32_t doorbell_hi = arm_sn | MLX5_CQ_DBR_CMD_ALL | cq_ci;
107         uint64_t doorbell = ((uint64_t)doorbell_hi << 32) | cq->cq->id;
108         uint64_t db_be = rte_cpu_to_be_64(doorbell);
109         uint32_t *addr = RTE_PTR_ADD(priv->uar->base_addr, MLX5_CQ_DOORBELL);
110
111         rte_io_wmb();
112         cq->db_rec[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
113         rte_wmb();
114 #ifdef RTE_ARCH_64
115         *(uint64_t *)addr = db_be;
116 #else
117         *(uint32_t *)addr = db_be;
118         rte_io_wmb();
119         *((uint32_t *)addr + 1) = db_be >> 32;
120 #endif
121         cq->arm_sn++;
122         cq->armed = 1;
123 }
124
125 static int
126 mlx5_vdpa_cq_create(struct mlx5_vdpa_priv *priv, uint16_t log_desc_n,
127                     int callfd, struct mlx5_vdpa_cq *cq)
128 {
129         struct mlx5_devx_cq_attr attr = {0};
130         size_t pgsize = sysconf(_SC_PAGESIZE);
131         uint32_t umem_size;
132         uint16_t event_nums[1] = {0};
133         uint16_t cq_size = 1 << log_desc_n;
134         int ret;
135
136         cq->log_desc_n = log_desc_n;
137         umem_size = sizeof(struct mlx5_cqe) * cq_size + sizeof(*cq->db_rec) * 2;
138         cq->umem_buf = rte_zmalloc(__func__, umem_size, 4096);
139         if (!cq->umem_buf) {
140                 DRV_LOG(ERR, "Failed to allocate memory for CQ.");
141                 rte_errno = ENOMEM;
142                 return -ENOMEM;
143         }
144         cq->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
145                                                 (void *)(uintptr_t)cq->umem_buf,
146                                                 umem_size,
147                                                 IBV_ACCESS_LOCAL_WRITE);
148         if (!cq->umem_obj) {
149                 DRV_LOG(ERR, "Failed to register umem for CQ.");
150                 goto error;
151         }
152         attr.q_umem_valid = 1;
153         attr.db_umem_valid = 1;
154         attr.use_first_only = 1;
155         attr.overrun_ignore = 0;
156         attr.uar_page_id = priv->uar->page_id;
157         attr.q_umem_id = cq->umem_obj->umem_id;
158         attr.q_umem_offset = 0;
159         attr.db_umem_id = cq->umem_obj->umem_id;
160         attr.db_umem_offset = sizeof(struct mlx5_cqe) * cq_size;
161         attr.eqn = priv->eqn;
162         attr.log_cq_size = log_desc_n;
163         attr.log_page_size = rte_log2_u32(pgsize);
164         cq->cq = mlx5_devx_cmd_create_cq(priv->ctx, &attr);
165         if (!cq->cq)
166                 goto error;
167         cq->db_rec = RTE_PTR_ADD(cq->umem_buf, (uintptr_t)attr.db_umem_offset);
168         cq->cq_ci = 0;
169         rte_spinlock_init(&cq->sl);
170         /* Subscribe CQ event to the event channel controlled by the driver. */
171         ret = mlx5_glue->devx_subscribe_devx_event(priv->eventc, cq->cq->obj,
172                                                    sizeof(event_nums),
173                                                    event_nums,
174                                                    (uint64_t)(uintptr_t)cq);
175         if (ret) {
176                 DRV_LOG(ERR, "Failed to subscribe CQE event.");
177                 rte_errno = errno;
178                 goto error;
179         }
180         cq->callfd = callfd;
181         /* Init CQ to ones to be in HW owner in the start. */
182         cq->cqes[0].op_own = MLX5_CQE_OWNER_MASK;
183         cq->cqes[0].wqe_counter = rte_cpu_to_be_16(UINT16_MAX);
184         /* First arming. */
185         mlx5_vdpa_cq_arm(priv, cq);
186         return 0;
187 error:
188         mlx5_vdpa_cq_destroy(cq);
189         return -1;
190 }
191
192 static inline uint32_t
193 mlx5_vdpa_cq_poll(struct mlx5_vdpa_cq *cq)
194 {
195         struct mlx5_vdpa_event_qp *eqp =
196                                 container_of(cq, struct mlx5_vdpa_event_qp, cq);
197         const unsigned int cq_size = 1 << cq->log_desc_n;
198         union {
199                 struct {
200                         uint16_t wqe_counter;
201                         uint8_t rsvd5;
202                         uint8_t op_own;
203                 };
204                 uint32_t word;
205         } last_word;
206         uint16_t next_wqe_counter = cq->cq_ci;
207         uint16_t cur_wqe_counter;
208         uint16_t comp;
209
210         last_word.word = rte_read32(&cq->cqes[0].wqe_counter);
211         cur_wqe_counter = rte_be_to_cpu_16(last_word.wqe_counter);
212         comp = cur_wqe_counter + (uint16_t)1 - next_wqe_counter;
213         if (comp) {
214                 cq->cq_ci += comp;
215                 MLX5_ASSERT(MLX5_CQE_OPCODE(last_word.op_own) !=
216                             MLX5_CQE_INVALID);
217                 if (unlikely(!(MLX5_CQE_OPCODE(last_word.op_own) ==
218                                MLX5_CQE_RESP_ERR ||
219                                MLX5_CQE_OPCODE(last_word.op_own) ==
220                                MLX5_CQE_REQ_ERR)))
221                         cq->errors++;
222                 rte_io_wmb();
223                 /* Ring CQ doorbell record. */
224                 cq->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
225                 rte_io_wmb();
226                 /* Ring SW QP doorbell record. */
227                 eqp->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci + cq_size);
228         }
229         return comp;
230 }
231
232 static void
233 mlx5_vdpa_arm_all_cqs(struct mlx5_vdpa_priv *priv)
234 {
235         struct mlx5_vdpa_cq *cq;
236         int i;
237
238         for (i = 0; i < priv->nr_virtqs; i++) {
239                 cq = &priv->virtqs[i].eqp.cq;
240                 if (cq->cq && !cq->armed)
241                         mlx5_vdpa_cq_arm(priv, cq);
242         }
243 }
244
245 static void
246 mlx5_vdpa_timer_sleep(struct mlx5_vdpa_priv *priv, uint32_t max)
247 {
248         if (priv->event_mode == MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER) {
249                 switch (max) {
250                 case 0:
251                         priv->timer_delay_us += priv->event_us;
252                         break;
253                 case 1:
254                         break;
255                 default:
256                         priv->timer_delay_us /= max;
257                         break;
258                 }
259         }
260         usleep(priv->timer_delay_us);
261 }
262
263 static void *
264 mlx5_vdpa_poll_handle(void *arg)
265 {
266         struct mlx5_vdpa_priv *priv = arg;
267         int i;
268         struct mlx5_vdpa_cq *cq;
269         uint32_t max;
270         uint64_t current_tic;
271
272         pthread_mutex_lock(&priv->timer_lock);
273         while (!priv->timer_on)
274                 pthread_cond_wait(&priv->timer_cond, &priv->timer_lock);
275         pthread_mutex_unlock(&priv->timer_lock);
276         priv->timer_delay_us = priv->event_mode ==
277                                             MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER ?
278                                               MLX5_VDPA_DEFAULT_TIMER_DELAY_US :
279                                                                  priv->event_us;
280         while (1) {
281                 max = 0;
282                 pthread_mutex_lock(&priv->vq_config_lock);
283                 for (i = 0; i < priv->nr_virtqs; i++) {
284                         cq = &priv->virtqs[i].eqp.cq;
285                         if (cq->cq && !cq->armed) {
286                                 uint32_t comp = mlx5_vdpa_cq_poll(cq);
287
288                                 if (comp) {
289                                         /* Notify guest for descs consuming. */
290                                         if (cq->callfd != -1)
291                                                 eventfd_write(cq->callfd,
292                                                               (eventfd_t)1);
293                                         if (comp > max)
294                                                 max = comp;
295                                 }
296                         }
297                 }
298                 current_tic = rte_rdtsc();
299                 if (!max) {
300                         /* No traffic ? stop timer and load interrupts. */
301                         if (current_tic - priv->last_traffic_tic >=
302                             rte_get_timer_hz() * priv->no_traffic_time_s) {
303                                 DRV_LOG(DEBUG, "Device %s traffic was stopped.",
304                                         priv->vdev->device->name);
305                                 mlx5_vdpa_arm_all_cqs(priv);
306                                 pthread_mutex_unlock(&priv->vq_config_lock);
307                                 pthread_mutex_lock(&priv->timer_lock);
308                                 priv->timer_on = 0;
309                                 while (!priv->timer_on)
310                                         pthread_cond_wait(&priv->timer_cond,
311                                                           &priv->timer_lock);
312                                 pthread_mutex_unlock(&priv->timer_lock);
313                                 priv->timer_delay_us = priv->event_mode ==
314                                             MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER ?
315                                               MLX5_VDPA_DEFAULT_TIMER_DELAY_US :
316                                                                  priv->event_us;
317                                 continue;
318                         }
319                 } else {
320                         priv->last_traffic_tic = current_tic;
321                 }
322                 pthread_mutex_unlock(&priv->vq_config_lock);
323                 mlx5_vdpa_timer_sleep(priv, max);
324         }
325         return NULL;
326 }
327
328 static void
329 mlx5_vdpa_interrupt_handler(void *cb_arg)
330 {
331         struct mlx5_vdpa_priv *priv = cb_arg;
332 #ifdef HAVE_IBV_DEVX_EVENT
333         union {
334                 struct mlx5dv_devx_async_event_hdr event_resp;
335                 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
336         } out;
337
338         pthread_mutex_lock(&priv->vq_config_lock);
339         while (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,
340                                          sizeof(out.buf)) >=
341                                        (ssize_t)sizeof(out.event_resp.cookie)) {
342                 struct mlx5_vdpa_cq *cq = (struct mlx5_vdpa_cq *)
343                                                (uintptr_t)out.event_resp.cookie;
344                 struct mlx5_vdpa_event_qp *eqp = container_of(cq,
345                                                  struct mlx5_vdpa_event_qp, cq);
346                 struct mlx5_vdpa_virtq *virtq = container_of(eqp,
347                                                    struct mlx5_vdpa_virtq, eqp);
348
349                 if (!virtq->enable)
350                         continue;
351                 mlx5_vdpa_cq_poll(cq);
352                 /* Notify guest for descs consuming. */
353                 if (cq->callfd != -1)
354                         eventfd_write(cq->callfd, (eventfd_t)1);
355                 if (priv->event_mode == MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT) {
356                         mlx5_vdpa_cq_arm(priv, cq);
357                         pthread_mutex_unlock(&priv->vq_config_lock);
358                         return;
359                 }
360                 /* Don't arm again - timer will take control. */
361                 DRV_LOG(DEBUG, "Device %s virtq %d cq %d event was captured."
362                         " Timer is %s, cq ci is %u.\n",
363                         priv->vdev->device->name,
364                         (int)virtq->index, cq->cq->id,
365                         priv->timer_on ? "on" : "off", cq->cq_ci);
366                 cq->armed = 0;
367         }
368 #endif
369
370         /* Traffic detected: make sure timer is on. */
371         priv->last_traffic_tic = rte_rdtsc();
372         pthread_mutex_lock(&priv->timer_lock);
373         if (!priv->timer_on) {
374                 priv->timer_on = 1;
375                 pthread_cond_signal(&priv->timer_cond);
376         }
377         pthread_mutex_unlock(&priv->timer_lock);
378         pthread_mutex_unlock(&priv->vq_config_lock);
379 }
380
381 int
382 mlx5_vdpa_cqe_event_setup(struct mlx5_vdpa_priv *priv)
383 {
384         int ret;
385
386         if (!priv->eventc)
387                 /* All virtqs are in poll mode. */
388                 return 0;
389         if (priv->event_mode != MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT) {
390                 pthread_mutex_init(&priv->timer_lock, NULL);
391                 pthread_cond_init(&priv->timer_cond, NULL);
392                 priv->timer_on = 0;
393                 ret = pthread_create(&priv->timer_tid, NULL,
394                                      mlx5_vdpa_poll_handle, (void *)priv);
395                 if (ret) {
396                         DRV_LOG(ERR, "Failed to create timer thread.");
397                         return -1;
398                 }
399         }
400         priv->intr_handle.fd = priv->eventc->fd;
401         priv->intr_handle.type = RTE_INTR_HANDLE_EXT;
402         if (rte_intr_callback_register(&priv->intr_handle,
403                                        mlx5_vdpa_interrupt_handler, priv)) {
404                 priv->intr_handle.fd = 0;
405                 DRV_LOG(ERR, "Failed to register CQE interrupt %d.", rte_errno);
406                 goto error;
407         }
408         return 0;
409 error:
410         mlx5_vdpa_cqe_event_unset(priv);
411         return -1;
412 }
413
414 void
415 mlx5_vdpa_cqe_event_unset(struct mlx5_vdpa_priv *priv)
416 {
417         int retries = MLX5_VDPA_INTR_RETRIES;
418         int ret = -EAGAIN;
419         void *status;
420
421         if (priv->intr_handle.fd) {
422                 while (retries-- && ret == -EAGAIN) {
423                         ret = rte_intr_callback_unregister(&priv->intr_handle,
424                                                     mlx5_vdpa_interrupt_handler,
425                                                     priv);
426                         if (ret == -EAGAIN) {
427                                 DRV_LOG(DEBUG, "Try again to unregister fd %d "
428                                         "of CQ interrupt, retries = %d.",
429                                         priv->intr_handle.fd, retries);
430                                 rte_pause();
431                         }
432                 }
433                 memset(&priv->intr_handle, 0, sizeof(priv->intr_handle));
434         }
435         if (priv->timer_tid) {
436                 pthread_cancel(priv->timer_tid);
437                 pthread_join(priv->timer_tid, &status);
438         }
439         priv->timer_tid = 0;
440 }
441
442 void
443 mlx5_vdpa_event_qp_destroy(struct mlx5_vdpa_event_qp *eqp)
444 {
445         if (eqp->sw_qp)
446                 claim_zero(mlx5_devx_cmd_destroy(eqp->sw_qp));
447         if (eqp->umem_obj)
448                 claim_zero(mlx5_glue->devx_umem_dereg(eqp->umem_obj));
449         if (eqp->umem_buf)
450                 rte_free(eqp->umem_buf);
451         if (eqp->fw_qp)
452                 claim_zero(mlx5_devx_cmd_destroy(eqp->fw_qp));
453         mlx5_vdpa_cq_destroy(&eqp->cq);
454         memset(eqp, 0, sizeof(*eqp));
455 }
456
457 static int
458 mlx5_vdpa_qps2rts(struct mlx5_vdpa_event_qp *eqp)
459 {
460         if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RST2INIT_QP,
461                                           eqp->sw_qp->id)) {
462                 DRV_LOG(ERR, "Failed to modify FW QP to INIT state(%u).",
463                         rte_errno);
464                 return -1;
465         }
466         if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RST2INIT_QP,
467                                           eqp->fw_qp->id)) {
468                 DRV_LOG(ERR, "Failed to modify SW QP to INIT state(%u).",
469                         rte_errno);
470                 return -1;
471         }
472         if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_INIT2RTR_QP,
473                                           eqp->sw_qp->id)) {
474                 DRV_LOG(ERR, "Failed to modify FW QP to RTR state(%u).",
475                         rte_errno);
476                 return -1;
477         }
478         if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_INIT2RTR_QP,
479                                           eqp->fw_qp->id)) {
480                 DRV_LOG(ERR, "Failed to modify SW QP to RTR state(%u).",
481                         rte_errno);
482                 return -1;
483         }
484         if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RTR2RTS_QP,
485                                           eqp->sw_qp->id)) {
486                 DRV_LOG(ERR, "Failed to modify FW QP to RTS state(%u).",
487                         rte_errno);
488                 return -1;
489         }
490         if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RTR2RTS_QP,
491                                           eqp->fw_qp->id)) {
492                 DRV_LOG(ERR, "Failed to modify SW QP to RTS state(%u).",
493                         rte_errno);
494                 return -1;
495         }
496         return 0;
497 }
498
499 int
500 mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,
501                           int callfd, struct mlx5_vdpa_event_qp *eqp)
502 {
503         struct mlx5_devx_qp_attr attr = {0};
504         uint16_t log_desc_n = rte_log2_u32(desc_n);
505         uint32_t umem_size = (1 << log_desc_n) * MLX5_WSEG_SIZE +
506                                                        sizeof(*eqp->db_rec) * 2;
507
508         if (mlx5_vdpa_event_qp_global_prepare(priv))
509                 return -1;
510         if (mlx5_vdpa_cq_create(priv, log_desc_n, callfd, &eqp->cq))
511                 return -1;
512         attr.pd = priv->pdn;
513         eqp->fw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
514         if (!eqp->fw_qp) {
515                 DRV_LOG(ERR, "Failed to create FW QP(%u).", rte_errno);
516                 goto error;
517         }
518         eqp->umem_buf = rte_zmalloc(__func__, umem_size, 4096);
519         if (!eqp->umem_buf) {
520                 DRV_LOG(ERR, "Failed to allocate memory for SW QP.");
521                 rte_errno = ENOMEM;
522                 goto error;
523         }
524         eqp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
525                                                (void *)(uintptr_t)eqp->umem_buf,
526                                                umem_size,
527                                                IBV_ACCESS_LOCAL_WRITE);
528         if (!eqp->umem_obj) {
529                 DRV_LOG(ERR, "Failed to register umem for SW QP.");
530                 goto error;
531         }
532         attr.uar_index = priv->uar->page_id;
533         attr.cqn = eqp->cq.cq->id;
534         attr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE));
535         attr.rq_size = 1 << log_desc_n;
536         attr.log_rq_stride = rte_log2_u32(MLX5_WSEG_SIZE);
537         attr.sq_size = 0; /* No need SQ. */
538         attr.dbr_umem_valid = 1;
539         attr.wq_umem_id = eqp->umem_obj->umem_id;
540         attr.wq_umem_offset = 0;
541         attr.dbr_umem_id = eqp->umem_obj->umem_id;
542         attr.dbr_address = (1 << log_desc_n) * MLX5_WSEG_SIZE;
543         eqp->sw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
544         if (!eqp->sw_qp) {
545                 DRV_LOG(ERR, "Failed to create SW QP(%u).", rte_errno);
546                 goto error;
547         }
548         eqp->db_rec = RTE_PTR_ADD(eqp->umem_buf, (uintptr_t)attr.dbr_address);
549         if (mlx5_vdpa_qps2rts(eqp))
550                 goto error;
551         /* First ringing. */
552         rte_write32(rte_cpu_to_be_32(1 << log_desc_n), &eqp->db_rec[0]);
553         return 0;
554 error:
555         mlx5_vdpa_event_qp_destroy(eqp);
556         return -1;
557 }