1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
7 #include <sys/eventfd.h>
9 #include <rte_malloc.h>
10 #include <rte_errno.h>
11 #include <rte_lcore.h>
12 #include <rte_atomic.h>
13 #include <rte_common.h>
15 #include <rte_alarm.h>
17 #include <mlx5_common.h>
19 #include "mlx5_vdpa_utils.h"
20 #include "mlx5_vdpa.h"
24 mlx5_vdpa_event_qp_global_release(struct mlx5_vdpa_priv *priv)
27 mlx5_glue->devx_free_uar(priv->uar);
30 #ifdef HAVE_IBV_DEVX_EVENT
33 struct mlx5dv_devx_async_event_hdr event_resp;
34 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr)
38 /* Clean all pending events. */
39 while (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,
41 (ssize_t)sizeof(out.event_resp.cookie))
43 mlx5_glue->devx_destroy_event_channel(priv->eventc);
50 /* Prepare all the global resources for all the event objects.*/
52 mlx5_vdpa_event_qp_global_prepare(struct mlx5_vdpa_priv *priv)
58 lcore = (uint32_t)rte_lcore_to_cpu_id(-1);
59 if (mlx5_glue->devx_query_eqn(priv->ctx, lcore, &priv->eqn)) {
61 DRV_LOG(ERR, "Failed to query EQ number %d.", rte_errno);
64 priv->eventc = mlx5_glue->devx_create_event_channel(priv->ctx,
65 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);
68 DRV_LOG(ERR, "Failed to create event channel %d.",
72 priv->uar = mlx5_glue->devx_alloc_uar(priv->ctx, 0);
75 DRV_LOG(ERR, "Failed to allocate UAR.");
80 mlx5_vdpa_event_qp_global_release(priv);
85 mlx5_vdpa_cq_destroy(struct mlx5_vdpa_cq *cq)
88 claim_zero(mlx5_devx_cmd_destroy(cq->cq));
90 claim_zero(mlx5_glue->devx_umem_dereg(cq->umem_obj));
92 rte_free((void *)(uintptr_t)cq->umem_buf);
93 memset(cq, 0, sizeof(*cq));
96 static inline void __rte_unused
97 mlx5_vdpa_cq_arm(struct mlx5_vdpa_priv *priv, struct mlx5_vdpa_cq *cq)
99 uint32_t arm_sn = cq->arm_sn << MLX5_CQ_SQN_OFFSET;
100 uint32_t cq_ci = cq->cq_ci & MLX5_CI_MASK;
101 uint32_t doorbell_hi = arm_sn | MLX5_CQ_DBR_CMD_ALL | cq_ci;
102 uint64_t doorbell = ((uint64_t)doorbell_hi << 32) | cq->cq->id;
103 uint64_t db_be = rte_cpu_to_be_64(doorbell);
104 uint32_t *addr = RTE_PTR_ADD(priv->uar->base_addr, MLX5_CQ_DOORBELL);
107 cq->db_rec[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
110 *(uint64_t *)addr = db_be;
112 *(uint32_t *)addr = db_be;
114 *((uint32_t *)addr + 1) = db_be >> 32;
121 mlx5_vdpa_cq_create(struct mlx5_vdpa_priv *priv, uint16_t log_desc_n,
122 int callfd, struct mlx5_vdpa_cq *cq)
124 struct mlx5_devx_cq_attr attr;
125 size_t pgsize = sysconf(_SC_PAGESIZE);
127 uint16_t event_nums[1] = {0};
128 uint16_t cq_size = 1 << log_desc_n;
131 cq->log_desc_n = log_desc_n;
132 umem_size = sizeof(struct mlx5_cqe) * cq_size + sizeof(*cq->db_rec) * 2;
133 cq->umem_buf = rte_zmalloc(__func__, umem_size, 4096);
135 DRV_LOG(ERR, "Failed to allocate memory for CQ.");
139 cq->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
140 (void *)(uintptr_t)cq->umem_buf,
142 IBV_ACCESS_LOCAL_WRITE);
144 DRV_LOG(ERR, "Failed to register umem for CQ.");
147 attr.q_umem_valid = 1;
148 attr.db_umem_valid = 1;
149 attr.use_first_only = 1;
150 attr.overrun_ignore = 0;
151 attr.uar_page_id = priv->uar->page_id;
152 attr.q_umem_id = cq->umem_obj->umem_id;
153 attr.q_umem_offset = 0;
154 attr.db_umem_id = cq->umem_obj->umem_id;
155 attr.db_umem_offset = sizeof(struct mlx5_cqe) * cq_size;
156 attr.eqn = priv->eqn;
157 attr.log_cq_size = log_desc_n;
158 attr.log_page_size = rte_log2_u32(pgsize);
159 cq->cq = mlx5_devx_cmd_create_cq(priv->ctx, &attr);
162 cq->db_rec = RTE_PTR_ADD(cq->umem_buf, (uintptr_t)attr.db_umem_offset);
164 rte_spinlock_init(&cq->sl);
165 /* Subscribe CQ event to the event channel controlled by the driver. */
166 ret = mlx5_glue->devx_subscribe_devx_event(priv->eventc, cq->cq->obj,
169 (uint64_t)(uintptr_t)cq);
171 DRV_LOG(ERR, "Failed to subscribe CQE event.");
176 priv->event_mode != MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT) {
177 ret = mlx5_glue->devx_subscribe_devx_event_fd(priv->eventc,
181 DRV_LOG(ERR, "Failed to subscribe CQE event fd.");
187 /* Init CQ to ones to be in HW owner in the start. */
188 cq->cqes[0].op_own = MLX5_CQE_OWNER_MASK;
189 cq->cqes[0].wqe_counter = rte_cpu_to_be_16(cq_size - 1);
191 mlx5_vdpa_cq_arm(priv, cq);
194 mlx5_vdpa_cq_destroy(cq);
198 static inline uint32_t
199 mlx5_vdpa_cq_poll(struct mlx5_vdpa_cq *cq)
201 struct mlx5_vdpa_event_qp *eqp =
202 container_of(cq, struct mlx5_vdpa_event_qp, cq);
203 const unsigned int cq_size = 1 << cq->log_desc_n;
204 const unsigned int cq_mask = cq_size - 1;
207 uint16_t wqe_counter;
213 uint16_t next_wqe_counter = cq->cq_ci & cq_mask;
214 uint16_t cur_wqe_counter;
217 last_word.word = rte_read32(&cq->cqes[0].wqe_counter);
218 cur_wqe_counter = rte_be_to_cpu_16(last_word.wqe_counter);
219 comp = (cur_wqe_counter + 1u - next_wqe_counter) & cq_mask;
222 MLX5_ASSERT(!!(cq->cq_ci & cq_size) ==
223 MLX5_CQE_OWNER(last_word.op_own));
224 MLX5_ASSERT(MLX5_CQE_OPCODE(last_word.op_own) !=
226 if (unlikely(!(MLX5_CQE_OPCODE(last_word.op_own) ==
228 MLX5_CQE_OPCODE(last_word.op_own) ==
232 /* Ring CQ doorbell record. */
233 cq->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
235 /* Ring SW QP doorbell record. */
236 eqp->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci + cq_size);
242 mlx5_vdpa_arm_all_cqs(struct mlx5_vdpa_priv *priv)
244 struct mlx5_vdpa_cq *cq;
247 for (i = 0; i < priv->nr_virtqs; i++) {
248 cq = &priv->virtqs[i].eqp.cq;
249 if (cq->cq && !cq->armed)
250 mlx5_vdpa_cq_arm(priv, cq);
255 mlx5_vdpa_timer_sleep(struct mlx5_vdpa_priv *priv, uint32_t max)
257 if (priv->event_mode == MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER) {
260 priv->timer_delay_us += priv->event_us;
265 priv->timer_delay_us /= max;
269 usleep(priv->timer_delay_us);
273 mlx5_vdpa_poll_handle(void *arg)
275 struct mlx5_vdpa_priv *priv = arg;
277 struct mlx5_vdpa_cq *cq;
279 uint64_t current_tic;
281 pthread_mutex_lock(&priv->timer_lock);
282 while (!priv->timer_on)
283 pthread_cond_wait(&priv->timer_cond, &priv->timer_lock);
284 pthread_mutex_unlock(&priv->timer_lock);
285 priv->timer_delay_us = priv->event_mode ==
286 MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER ?
287 MLX5_VDPA_DEFAULT_TIMER_DELAY_US :
291 for (i = 0; i < priv->nr_virtqs; i++) {
292 cq = &priv->virtqs[i].eqp.cq;
293 if (cq->cq && !cq->armed) {
294 uint32_t comp = mlx5_vdpa_cq_poll(cq);
297 /* Notify guest for descs consuming. */
298 if (cq->callfd != -1)
299 eventfd_write(cq->callfd,
306 current_tic = rte_rdtsc();
308 /* No traffic ? stop timer and load interrupts. */
309 if (current_tic - priv->last_traffic_tic >=
310 rte_get_timer_hz() * priv->no_traffic_time_s) {
311 DRV_LOG(DEBUG, "Device %s traffic was stopped.",
312 priv->vdev->device->name);
313 mlx5_vdpa_arm_all_cqs(priv);
314 pthread_mutex_lock(&priv->timer_lock);
316 while (!priv->timer_on)
317 pthread_cond_wait(&priv->timer_cond,
319 pthread_mutex_unlock(&priv->timer_lock);
320 priv->timer_delay_us = priv->event_mode ==
321 MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER ?
322 MLX5_VDPA_DEFAULT_TIMER_DELAY_US :
327 priv->last_traffic_tic = current_tic;
329 mlx5_vdpa_timer_sleep(priv, max);
335 mlx5_vdpa_interrupt_handler(void *cb_arg)
337 struct mlx5_vdpa_priv *priv = cb_arg;
338 #ifdef HAVE_IBV_DEVX_EVENT
340 struct mlx5dv_devx_async_event_hdr event_resp;
341 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
344 while (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,
346 (ssize_t)sizeof(out.event_resp.cookie)) {
347 struct mlx5_vdpa_cq *cq = (struct mlx5_vdpa_cq *)
348 (uintptr_t)out.event_resp.cookie;
349 struct mlx5_vdpa_event_qp *eqp = container_of(cq,
350 struct mlx5_vdpa_event_qp, cq);
351 struct mlx5_vdpa_virtq *virtq = container_of(eqp,
352 struct mlx5_vdpa_virtq, eqp);
354 mlx5_vdpa_cq_poll(cq);
355 if (priv->event_mode == MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT) {
356 mlx5_vdpa_cq_arm(priv, cq);
357 /* Notify guest for descs consuming. */
358 if (cq->callfd != -1)
359 eventfd_write(cq->callfd, (eventfd_t)1);
362 /* Don't arm again - timer will take control. */
363 DRV_LOG(DEBUG, "Device %s virtq %d cq %d event was captured."
364 " Timer is %s, cq ci is %u.\n",
365 priv->vdev->device->name,
366 (int)virtq->index, cq->cq->id,
367 priv->timer_on ? "on" : "off", cq->cq_ci);
372 /* Traffic detected: make sure timer is on. */
373 priv->last_traffic_tic = rte_rdtsc();
374 pthread_mutex_lock(&priv->timer_lock);
375 if (!priv->timer_on) {
377 pthread_cond_signal(&priv->timer_cond);
379 pthread_mutex_unlock(&priv->timer_lock);
383 mlx5_vdpa_cqe_event_setup(struct mlx5_vdpa_priv *priv)
389 /* All virtqs are in poll mode. */
391 if (priv->event_mode != MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT) {
392 pthread_mutex_init(&priv->timer_lock, NULL);
393 pthread_cond_init(&priv->timer_cond, NULL);
395 ret = pthread_create(&priv->timer_tid, NULL,
396 mlx5_vdpa_poll_handle, (void *)priv);
398 DRV_LOG(ERR, "Failed to create timer thread.");
402 flags = fcntl(priv->eventc->fd, F_GETFL);
403 ret = fcntl(priv->eventc->fd, F_SETFL, flags | O_NONBLOCK);
405 DRV_LOG(ERR, "Failed to change event channel FD.");
408 priv->intr_handle.fd = priv->eventc->fd;
409 priv->intr_handle.type = RTE_INTR_HANDLE_EXT;
410 if (rte_intr_callback_register(&priv->intr_handle,
411 mlx5_vdpa_interrupt_handler, priv)) {
412 priv->intr_handle.fd = 0;
413 DRV_LOG(ERR, "Failed to register CQE interrupt %d.", rte_errno);
418 mlx5_vdpa_cqe_event_unset(priv);
423 mlx5_vdpa_cqe_event_unset(struct mlx5_vdpa_priv *priv)
425 int retries = MLX5_VDPA_INTR_RETRIES;
429 if (priv->intr_handle.fd) {
430 while (retries-- && ret == -EAGAIN) {
431 ret = rte_intr_callback_unregister(&priv->intr_handle,
432 mlx5_vdpa_interrupt_handler,
434 if (ret == -EAGAIN) {
435 DRV_LOG(DEBUG, "Try again to unregister fd %d "
436 "of CQ interrupt, retries = %d.",
437 priv->intr_handle.fd, retries);
441 memset(&priv->intr_handle, 0, sizeof(priv->intr_handle));
443 if (priv->timer_tid) {
444 pthread_cancel(priv->timer_tid);
445 pthread_join(priv->timer_tid, &status);
451 mlx5_vdpa_event_qp_destroy(struct mlx5_vdpa_event_qp *eqp)
454 claim_zero(mlx5_devx_cmd_destroy(eqp->sw_qp));
456 claim_zero(mlx5_glue->devx_umem_dereg(eqp->umem_obj));
458 rte_free(eqp->umem_buf);
460 claim_zero(mlx5_devx_cmd_destroy(eqp->fw_qp));
461 mlx5_vdpa_cq_destroy(&eqp->cq);
462 memset(eqp, 0, sizeof(*eqp));
466 mlx5_vdpa_qps2rts(struct mlx5_vdpa_event_qp *eqp)
468 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RST2INIT_QP,
470 DRV_LOG(ERR, "Failed to modify FW QP to INIT state(%u).",
474 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RST2INIT_QP,
476 DRV_LOG(ERR, "Failed to modify SW QP to INIT state(%u).",
480 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_INIT2RTR_QP,
482 DRV_LOG(ERR, "Failed to modify FW QP to RTR state(%u).",
486 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_INIT2RTR_QP,
488 DRV_LOG(ERR, "Failed to modify SW QP to RTR state(%u).",
492 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RTR2RTS_QP,
494 DRV_LOG(ERR, "Failed to modify FW QP to RTS state(%u).",
498 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RTR2RTS_QP,
500 DRV_LOG(ERR, "Failed to modify SW QP to RTS state(%u).",
508 mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,
509 int callfd, struct mlx5_vdpa_event_qp *eqp)
511 struct mlx5_devx_qp_attr attr = {0};
512 uint16_t log_desc_n = rte_log2_u32(desc_n);
513 uint32_t umem_size = (1 << log_desc_n) * MLX5_WSEG_SIZE +
514 sizeof(*eqp->db_rec) * 2;
516 if (mlx5_vdpa_event_qp_global_prepare(priv))
518 if (mlx5_vdpa_cq_create(priv, log_desc_n, callfd, &eqp->cq))
521 eqp->fw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
523 DRV_LOG(ERR, "Failed to create FW QP(%u).", rte_errno);
526 eqp->umem_buf = rte_zmalloc(__func__, umem_size, 4096);
527 if (!eqp->umem_buf) {
528 DRV_LOG(ERR, "Failed to allocate memory for SW QP.");
532 eqp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
533 (void *)(uintptr_t)eqp->umem_buf,
535 IBV_ACCESS_LOCAL_WRITE);
536 if (!eqp->umem_obj) {
537 DRV_LOG(ERR, "Failed to register umem for SW QP.");
540 attr.uar_index = priv->uar->page_id;
541 attr.cqn = eqp->cq.cq->id;
542 attr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE));
543 attr.rq_size = 1 << log_desc_n;
544 attr.log_rq_stride = rte_log2_u32(MLX5_WSEG_SIZE);
545 attr.sq_size = 0; /* No need SQ. */
546 attr.dbr_umem_valid = 1;
547 attr.wq_umem_id = eqp->umem_obj->umem_id;
548 attr.wq_umem_offset = 0;
549 attr.dbr_umem_id = eqp->umem_obj->umem_id;
550 attr.dbr_address = (1 << log_desc_n) * MLX5_WSEG_SIZE;
551 eqp->sw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
553 DRV_LOG(ERR, "Failed to create SW QP(%u).", rte_errno);
556 eqp->db_rec = RTE_PTR_ADD(eqp->umem_buf, (uintptr_t)attr.dbr_address);
557 if (mlx5_vdpa_qps2rts(eqp))
560 rte_write32(rte_cpu_to_be_32(1 << log_desc_n), &eqp->db_rec[0]);
563 mlx5_vdpa_event_qp_destroy(eqp);