1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
7 #include <sys/eventfd.h>
9 #include <rte_malloc.h>
10 #include <rte_errno.h>
11 #include <rte_lcore.h>
12 #include <rte_atomic.h>
13 #include <rte_common.h>
15 #include <rte_alarm.h>
17 #include <mlx5_common.h>
18 #include <mlx5_common_os.h>
19 #include <mlx5_glue.h>
21 #include "mlx5_vdpa_utils.h"
22 #include "mlx5_vdpa.h"
25 #define MLX5_VDPA_ERROR_TIME_SEC 3u
28 mlx5_vdpa_event_qp_global_release(struct mlx5_vdpa_priv *priv)
31 mlx5_glue->devx_free_uar(priv->uar);
34 #ifdef HAVE_IBV_DEVX_EVENT
37 struct mlx5dv_devx_async_event_hdr event_resp;
38 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr)
42 /* Clean all pending events. */
43 while (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,
45 (ssize_t)sizeof(out.event_resp.cookie))
47 mlx5_os_devx_destroy_event_channel(priv->eventc);
54 /* Prepare all the global resources for all the event objects.*/
56 mlx5_vdpa_event_qp_global_prepare(struct mlx5_vdpa_priv *priv)
62 if (mlx5_glue->devx_query_eqn(priv->ctx, 0, &priv->eqn)) {
64 DRV_LOG(ERR, "Failed to query EQ number %d.", rte_errno);
67 priv->eventc = mlx5_os_devx_create_event_channel(priv->ctx,
68 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);
71 DRV_LOG(ERR, "Failed to create event channel %d.",
75 flags = fcntl(priv->eventc->fd, F_GETFL);
76 ret = fcntl(priv->eventc->fd, F_SETFL, flags | O_NONBLOCK);
78 DRV_LOG(ERR, "Failed to change event channel FD.");
82 * This PMD always claims the write memory barrier on UAR
83 * registers writings, it is safe to allocate UAR with any
84 * memory mapping type.
86 priv->uar = mlx5_devx_alloc_uar(priv->ctx, -1);
89 DRV_LOG(ERR, "Failed to allocate UAR.");
94 mlx5_vdpa_event_qp_global_release(priv);
99 mlx5_vdpa_cq_destroy(struct mlx5_vdpa_cq *cq)
102 claim_zero(mlx5_devx_cmd_destroy(cq->cq));
104 claim_zero(mlx5_glue->devx_umem_dereg(cq->umem_obj));
106 rte_free((void *)(uintptr_t)cq->umem_buf);
107 memset(cq, 0, sizeof(*cq));
110 static inline void __rte_unused
111 mlx5_vdpa_cq_arm(struct mlx5_vdpa_priv *priv, struct mlx5_vdpa_cq *cq)
113 uint32_t arm_sn = cq->arm_sn << MLX5_CQ_SQN_OFFSET;
114 uint32_t cq_ci = cq->cq_ci & MLX5_CI_MASK;
115 uint32_t doorbell_hi = arm_sn | MLX5_CQ_DBR_CMD_ALL | cq_ci;
116 uint64_t doorbell = ((uint64_t)doorbell_hi << 32) | cq->cq->id;
117 uint64_t db_be = rte_cpu_to_be_64(doorbell);
118 uint32_t *addr = RTE_PTR_ADD(priv->uar->base_addr, MLX5_CQ_DOORBELL);
121 cq->db_rec[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
124 *(uint64_t *)addr = db_be;
126 *(uint32_t *)addr = db_be;
128 *((uint32_t *)addr + 1) = db_be >> 32;
135 mlx5_vdpa_cq_create(struct mlx5_vdpa_priv *priv, uint16_t log_desc_n,
136 int callfd, struct mlx5_vdpa_cq *cq)
138 struct mlx5_devx_cq_attr attr = {0};
139 size_t pgsize = sysconf(_SC_PAGESIZE);
141 uint16_t event_nums[1] = {0};
142 uint16_t cq_size = 1 << log_desc_n;
145 cq->log_desc_n = log_desc_n;
146 umem_size = sizeof(struct mlx5_cqe) * cq_size + sizeof(*cq->db_rec) * 2;
147 cq->umem_buf = rte_zmalloc(__func__, umem_size, 4096);
149 DRV_LOG(ERR, "Failed to allocate memory for CQ.");
153 cq->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
154 (void *)(uintptr_t)cq->umem_buf,
156 IBV_ACCESS_LOCAL_WRITE);
158 DRV_LOG(ERR, "Failed to register umem for CQ.");
161 attr.q_umem_valid = 1;
162 attr.db_umem_valid = 1;
163 attr.use_first_only = 1;
164 attr.overrun_ignore = 0;
165 attr.uar_page_id = priv->uar->page_id;
166 attr.q_umem_id = cq->umem_obj->umem_id;
167 attr.q_umem_offset = 0;
168 attr.db_umem_id = cq->umem_obj->umem_id;
169 attr.db_umem_offset = sizeof(struct mlx5_cqe) * cq_size;
170 attr.eqn = priv->eqn;
171 attr.log_cq_size = log_desc_n;
172 attr.log_page_size = rte_log2_u32(pgsize);
173 cq->cq = mlx5_devx_cmd_create_cq(priv->ctx, &attr);
176 cq->db_rec = RTE_PTR_ADD(cq->umem_buf, (uintptr_t)attr.db_umem_offset);
178 rte_spinlock_init(&cq->sl);
179 /* Subscribe CQ event to the event channel controlled by the driver. */
180 ret = mlx5_os_devx_subscribe_devx_event(priv->eventc, cq->cq->obj,
183 (uint64_t)(uintptr_t)cq);
185 DRV_LOG(ERR, "Failed to subscribe CQE event.");
190 /* Init CQ to ones to be in HW owner in the start. */
191 cq->cqes[0].op_own = MLX5_CQE_OWNER_MASK;
192 cq->cqes[0].wqe_counter = rte_cpu_to_be_16(UINT16_MAX);
194 mlx5_vdpa_cq_arm(priv, cq);
197 mlx5_vdpa_cq_destroy(cq);
201 static inline uint32_t
202 mlx5_vdpa_cq_poll(struct mlx5_vdpa_cq *cq)
204 struct mlx5_vdpa_event_qp *eqp =
205 container_of(cq, struct mlx5_vdpa_event_qp, cq);
206 const unsigned int cq_size = 1 << cq->log_desc_n;
209 uint16_t wqe_counter;
215 uint16_t next_wqe_counter = cq->cq_ci;
216 uint16_t cur_wqe_counter;
219 last_word.word = rte_read32(&cq->cqes[0].wqe_counter);
220 cur_wqe_counter = rte_be_to_cpu_16(last_word.wqe_counter);
221 comp = cur_wqe_counter + (uint16_t)1 - next_wqe_counter;
224 MLX5_ASSERT(MLX5_CQE_OPCODE(last_word.op_own) !=
226 if (unlikely(!(MLX5_CQE_OPCODE(last_word.op_own) ==
228 MLX5_CQE_OPCODE(last_word.op_own) ==
232 /* Ring CQ doorbell record. */
233 cq->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
235 /* Ring SW QP doorbell record. */
236 eqp->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci + cq_size);
242 mlx5_vdpa_arm_all_cqs(struct mlx5_vdpa_priv *priv)
244 struct mlx5_vdpa_cq *cq;
247 for (i = 0; i < priv->nr_virtqs; i++) {
248 cq = &priv->virtqs[i].eqp.cq;
249 if (cq->cq && !cq->armed)
250 mlx5_vdpa_cq_arm(priv, cq);
255 mlx5_vdpa_timer_sleep(struct mlx5_vdpa_priv *priv, uint32_t max)
257 if (priv->event_mode == MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER) {
260 priv->timer_delay_us += priv->event_us;
265 priv->timer_delay_us /= max;
269 usleep(priv->timer_delay_us);
273 mlx5_vdpa_poll_handle(void *arg)
275 struct mlx5_vdpa_priv *priv = arg;
277 struct mlx5_vdpa_cq *cq;
279 uint64_t current_tic;
281 pthread_mutex_lock(&priv->timer_lock);
282 while (!priv->timer_on)
283 pthread_cond_wait(&priv->timer_cond, &priv->timer_lock);
284 pthread_mutex_unlock(&priv->timer_lock);
285 priv->timer_delay_us = priv->event_mode ==
286 MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER ?
287 MLX5_VDPA_DEFAULT_TIMER_DELAY_US :
291 pthread_mutex_lock(&priv->vq_config_lock);
292 for (i = 0; i < priv->nr_virtqs; i++) {
293 cq = &priv->virtqs[i].eqp.cq;
294 if (cq->cq && !cq->armed) {
295 uint32_t comp = mlx5_vdpa_cq_poll(cq);
298 /* Notify guest for descs consuming. */
299 if (cq->callfd != -1)
300 eventfd_write(cq->callfd,
307 current_tic = rte_rdtsc();
309 /* No traffic ? stop timer and load interrupts. */
310 if (current_tic - priv->last_traffic_tic >=
311 rte_get_timer_hz() * priv->no_traffic_time_s) {
312 DRV_LOG(DEBUG, "Device %s traffic was stopped.",
313 priv->vdev->device->name);
314 mlx5_vdpa_arm_all_cqs(priv);
315 pthread_mutex_unlock(&priv->vq_config_lock);
316 pthread_mutex_lock(&priv->timer_lock);
318 while (!priv->timer_on)
319 pthread_cond_wait(&priv->timer_cond,
321 pthread_mutex_unlock(&priv->timer_lock);
322 priv->timer_delay_us = priv->event_mode ==
323 MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER ?
324 MLX5_VDPA_DEFAULT_TIMER_DELAY_US :
329 priv->last_traffic_tic = current_tic;
331 pthread_mutex_unlock(&priv->vq_config_lock);
332 mlx5_vdpa_timer_sleep(priv, max);
338 mlx5_vdpa_interrupt_handler(void *cb_arg)
340 struct mlx5_vdpa_priv *priv = cb_arg;
341 #ifdef HAVE_IBV_DEVX_EVENT
343 struct mlx5dv_devx_async_event_hdr event_resp;
344 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
347 pthread_mutex_lock(&priv->vq_config_lock);
348 while (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,
350 (ssize_t)sizeof(out.event_resp.cookie)) {
351 struct mlx5_vdpa_cq *cq = (struct mlx5_vdpa_cq *)
352 (uintptr_t)out.event_resp.cookie;
353 struct mlx5_vdpa_event_qp *eqp = container_of(cq,
354 struct mlx5_vdpa_event_qp, cq);
355 struct mlx5_vdpa_virtq *virtq = container_of(eqp,
356 struct mlx5_vdpa_virtq, eqp);
360 mlx5_vdpa_cq_poll(cq);
361 /* Notify guest for descs consuming. */
362 if (cq->callfd != -1)
363 eventfd_write(cq->callfd, (eventfd_t)1);
364 if (priv->event_mode == MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT) {
365 mlx5_vdpa_cq_arm(priv, cq);
366 pthread_mutex_unlock(&priv->vq_config_lock);
369 /* Don't arm again - timer will take control. */
370 DRV_LOG(DEBUG, "Device %s virtq %d cq %d event was captured."
371 " Timer is %s, cq ci is %u.\n",
372 priv->vdev->device->name,
373 (int)virtq->index, cq->cq->id,
374 priv->timer_on ? "on" : "off", cq->cq_ci);
379 /* Traffic detected: make sure timer is on. */
380 priv->last_traffic_tic = rte_rdtsc();
381 pthread_mutex_lock(&priv->timer_lock);
382 if (!priv->timer_on) {
384 pthread_cond_signal(&priv->timer_cond);
386 pthread_mutex_unlock(&priv->timer_lock);
387 pthread_mutex_unlock(&priv->vq_config_lock);
391 mlx5_vdpa_err_interrupt_handler(void *cb_arg __rte_unused)
393 #ifdef HAVE_IBV_DEVX_EVENT
394 struct mlx5_vdpa_priv *priv = cb_arg;
396 struct mlx5dv_devx_async_event_hdr event_resp;
397 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
399 uint32_t vq_index, i, version;
400 struct mlx5_vdpa_virtq *virtq;
403 pthread_mutex_lock(&priv->vq_config_lock);
404 while (mlx5_glue->devx_get_event(priv->err_chnl, &out.event_resp,
406 (ssize_t)sizeof(out.event_resp.cookie)) {
407 vq_index = out.event_resp.cookie & UINT32_MAX;
408 version = out.event_resp.cookie >> 32;
409 if (vq_index >= priv->nr_virtqs) {
410 DRV_LOG(ERR, "Invalid device %s error event virtq %d.",
411 priv->vdev->device->name, vq_index);
414 virtq = &priv->virtqs[vq_index];
415 if (!virtq->enable || virtq->version != version)
417 if (rte_rdtsc() / rte_get_tsc_hz() < MLX5_VDPA_ERROR_TIME_SEC)
419 virtq->stopped = true;
420 /* Query error info. */
421 if (mlx5_vdpa_virtq_query(priv, vq_index))
424 if (mlx5_vdpa_virtq_enable(priv, vq_index, 0)) {
425 DRV_LOG(ERR, "Failed to disable virtq %d.", vq_index);
428 /* Retry if error happens less than N times in 3 seconds. */
429 sec = (rte_rdtsc() - virtq->err_time[0]) / rte_get_tsc_hz();
430 if (sec > MLX5_VDPA_ERROR_TIME_SEC) {
432 if (mlx5_vdpa_virtq_enable(priv, vq_index, 1))
433 DRV_LOG(ERR, "Failed to enable virtq %d.",
436 DRV_LOG(WARNING, "Recover virtq %d: %u.",
437 vq_index, ++virtq->n_retry);
439 /* Retry timeout, give up. */
440 DRV_LOG(ERR, "Device %s virtq %d failed to recover.",
441 priv->vdev->device->name, vq_index);
444 /* Shift in current time to error time log end. */
445 for (i = 1; i < RTE_DIM(virtq->err_time); i++)
446 virtq->err_time[i - 1] = virtq->err_time[i];
447 virtq->err_time[RTE_DIM(virtq->err_time) - 1] = rte_rdtsc();
449 pthread_mutex_unlock(&priv->vq_config_lock);
454 mlx5_vdpa_err_event_setup(struct mlx5_vdpa_priv *priv)
459 /* Setup device event channel. */
460 priv->err_chnl = mlx5_glue->devx_create_event_channel(priv->ctx, 0);
461 if (!priv->err_chnl) {
463 DRV_LOG(ERR, "Failed to create device event channel %d.",
467 flags = fcntl(priv->err_chnl->fd, F_GETFL);
468 ret = fcntl(priv->err_chnl->fd, F_SETFL, flags | O_NONBLOCK);
470 DRV_LOG(ERR, "Failed to change device event channel FD.");
473 priv->err_intr_handle.fd = priv->err_chnl->fd;
474 priv->err_intr_handle.type = RTE_INTR_HANDLE_EXT;
475 if (rte_intr_callback_register(&priv->err_intr_handle,
476 mlx5_vdpa_err_interrupt_handler,
478 priv->err_intr_handle.fd = 0;
479 DRV_LOG(ERR, "Failed to register error interrupt for device %d.",
483 DRV_LOG(DEBUG, "Registered error interrupt for device%d.",
488 mlx5_vdpa_err_event_unset(priv);
493 mlx5_vdpa_err_event_unset(struct mlx5_vdpa_priv *priv)
495 int retries = MLX5_VDPA_INTR_RETRIES;
498 if (!priv->err_intr_handle.fd)
500 while (retries-- && ret == -EAGAIN) {
501 ret = rte_intr_callback_unregister(&priv->err_intr_handle,
502 mlx5_vdpa_err_interrupt_handler,
504 if (ret == -EAGAIN) {
505 DRV_LOG(DEBUG, "Try again to unregister fd %d "
506 "of error interrupt, retries = %d.",
507 priv->err_intr_handle.fd, retries);
511 memset(&priv->err_intr_handle, 0, sizeof(priv->err_intr_handle));
512 if (priv->err_chnl) {
513 #ifdef HAVE_IBV_DEVX_EVENT
515 struct mlx5dv_devx_async_event_hdr event_resp;
516 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) +
520 /* Clean all pending events. */
521 while (mlx5_glue->devx_get_event(priv->err_chnl,
522 &out.event_resp, sizeof(out.buf)) >=
523 (ssize_t)sizeof(out.event_resp.cookie))
526 mlx5_glue->devx_destroy_event_channel(priv->err_chnl);
527 priv->err_chnl = NULL;
532 mlx5_vdpa_cqe_event_setup(struct mlx5_vdpa_priv *priv)
537 /* All virtqs are in poll mode. */
539 if (priv->event_mode != MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT) {
540 pthread_mutex_init(&priv->timer_lock, NULL);
541 pthread_cond_init(&priv->timer_cond, NULL);
543 ret = pthread_create(&priv->timer_tid, NULL,
544 mlx5_vdpa_poll_handle, (void *)priv);
546 DRV_LOG(ERR, "Failed to create timer thread.");
550 priv->intr_handle.fd = priv->eventc->fd;
551 priv->intr_handle.type = RTE_INTR_HANDLE_EXT;
552 if (rte_intr_callback_register(&priv->intr_handle,
553 mlx5_vdpa_interrupt_handler, priv)) {
554 priv->intr_handle.fd = 0;
555 DRV_LOG(ERR, "Failed to register CQE interrupt %d.", rte_errno);
560 mlx5_vdpa_cqe_event_unset(priv);
565 mlx5_vdpa_cqe_event_unset(struct mlx5_vdpa_priv *priv)
567 int retries = MLX5_VDPA_INTR_RETRIES;
571 if (priv->intr_handle.fd) {
572 while (retries-- && ret == -EAGAIN) {
573 ret = rte_intr_callback_unregister(&priv->intr_handle,
574 mlx5_vdpa_interrupt_handler,
576 if (ret == -EAGAIN) {
577 DRV_LOG(DEBUG, "Try again to unregister fd %d "
578 "of CQ interrupt, retries = %d.",
579 priv->intr_handle.fd, retries);
583 memset(&priv->intr_handle, 0, sizeof(priv->intr_handle));
585 if (priv->timer_tid) {
586 pthread_cancel(priv->timer_tid);
587 pthread_join(priv->timer_tid, &status);
593 mlx5_vdpa_event_qp_destroy(struct mlx5_vdpa_event_qp *eqp)
596 claim_zero(mlx5_devx_cmd_destroy(eqp->sw_qp));
598 claim_zero(mlx5_glue->devx_umem_dereg(eqp->umem_obj));
600 rte_free(eqp->umem_buf);
602 claim_zero(mlx5_devx_cmd_destroy(eqp->fw_qp));
603 mlx5_vdpa_cq_destroy(&eqp->cq);
604 memset(eqp, 0, sizeof(*eqp));
608 mlx5_vdpa_qps2rts(struct mlx5_vdpa_event_qp *eqp)
610 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RST2INIT_QP,
612 DRV_LOG(ERR, "Failed to modify FW QP to INIT state(%u).",
616 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RST2INIT_QP,
618 DRV_LOG(ERR, "Failed to modify SW QP to INIT state(%u).",
622 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_INIT2RTR_QP,
624 DRV_LOG(ERR, "Failed to modify FW QP to RTR state(%u).",
628 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_INIT2RTR_QP,
630 DRV_LOG(ERR, "Failed to modify SW QP to RTR state(%u).",
634 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RTR2RTS_QP,
636 DRV_LOG(ERR, "Failed to modify FW QP to RTS state(%u).",
640 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RTR2RTS_QP,
642 DRV_LOG(ERR, "Failed to modify SW QP to RTS state(%u).",
650 mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,
651 int callfd, struct mlx5_vdpa_event_qp *eqp)
653 struct mlx5_devx_qp_attr attr = {0};
654 uint16_t log_desc_n = rte_log2_u32(desc_n);
655 uint32_t umem_size = (1 << log_desc_n) * MLX5_WSEG_SIZE +
656 sizeof(*eqp->db_rec) * 2;
658 if (mlx5_vdpa_event_qp_global_prepare(priv))
660 if (mlx5_vdpa_cq_create(priv, log_desc_n, callfd, &eqp->cq))
663 eqp->fw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
665 DRV_LOG(ERR, "Failed to create FW QP(%u).", rte_errno);
668 eqp->umem_buf = rte_zmalloc(__func__, umem_size, 4096);
669 if (!eqp->umem_buf) {
670 DRV_LOG(ERR, "Failed to allocate memory for SW QP.");
674 eqp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
675 (void *)(uintptr_t)eqp->umem_buf,
677 IBV_ACCESS_LOCAL_WRITE);
678 if (!eqp->umem_obj) {
679 DRV_LOG(ERR, "Failed to register umem for SW QP.");
682 attr.uar_index = priv->uar->page_id;
683 attr.cqn = eqp->cq.cq->id;
684 attr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE));
685 attr.rq_size = 1 << log_desc_n;
686 attr.log_rq_stride = rte_log2_u32(MLX5_WSEG_SIZE);
687 attr.sq_size = 0; /* No need SQ. */
688 attr.dbr_umem_valid = 1;
689 attr.wq_umem_id = eqp->umem_obj->umem_id;
690 attr.wq_umem_offset = 0;
691 attr.dbr_umem_id = eqp->umem_obj->umem_id;
692 attr.dbr_address = (1 << log_desc_n) * MLX5_WSEG_SIZE;
693 eqp->sw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
695 DRV_LOG(ERR, "Failed to create SW QP(%u).", rte_errno);
698 eqp->db_rec = RTE_PTR_ADD(eqp->umem_buf, (uintptr_t)attr.dbr_address);
699 if (mlx5_vdpa_qps2rts(eqp))
702 rte_write32(rte_cpu_to_be_32(1 << log_desc_n), &eqp->db_rec[0]);
705 mlx5_vdpa_event_qp_destroy(eqp);