1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
8 #include <sys/eventfd.h>
10 #include <rte_malloc.h>
11 #include <rte_memory.h>
12 #include <rte_errno.h>
13 #include <rte_lcore.h>
14 #include <rte_atomic.h>
15 #include <rte_common.h>
17 #include <rte_alarm.h>
19 #include <mlx5_common.h>
20 #include <mlx5_common_os.h>
21 #include <mlx5_common_devx.h>
22 #include <mlx5_glue.h>
24 #include "mlx5_vdpa_utils.h"
25 #include "mlx5_vdpa.h"
28 #define MLX5_VDPA_ERROR_TIME_SEC 3u
31 mlx5_vdpa_event_qp_global_release(struct mlx5_vdpa_priv *priv)
34 mlx5_glue->devx_free_uar(priv->uar);
37 #ifdef HAVE_IBV_DEVX_EVENT
40 struct mlx5dv_devx_async_event_hdr event_resp;
41 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr)
45 /* Clean all pending events. */
46 while (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,
48 (ssize_t)sizeof(out.event_resp.cookie))
50 mlx5_os_devx_destroy_event_channel(priv->eventc);
56 /* Prepare all the global resources for all the event objects.*/
58 mlx5_vdpa_event_qp_global_prepare(struct mlx5_vdpa_priv *priv)
64 priv->eventc = mlx5_os_devx_create_event_channel(priv->ctx,
65 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);
68 DRV_LOG(ERR, "Failed to create event channel %d.",
72 flags = fcntl(priv->eventc->fd, F_GETFL);
73 ret = fcntl(priv->eventc->fd, F_SETFL, flags | O_NONBLOCK);
75 DRV_LOG(ERR, "Failed to change event channel FD.");
79 * This PMD always claims the write memory barrier on UAR
80 * registers writings, it is safe to allocate UAR with any
81 * memory mapping type.
83 priv->uar = mlx5_devx_alloc_uar(priv->ctx, -1);
86 DRV_LOG(ERR, "Failed to allocate UAR.");
91 mlx5_vdpa_event_qp_global_release(priv);
96 mlx5_vdpa_cq_destroy(struct mlx5_vdpa_cq *cq)
98 mlx5_devx_cq_destroy(&cq->cq_obj);
99 memset(cq, 0, sizeof(*cq));
102 static inline void __rte_unused
103 mlx5_vdpa_cq_arm(struct mlx5_vdpa_priv *priv, struct mlx5_vdpa_cq *cq)
105 uint32_t arm_sn = cq->arm_sn << MLX5_CQ_SQN_OFFSET;
106 uint32_t cq_ci = cq->cq_ci & MLX5_CI_MASK;
107 uint32_t doorbell_hi = arm_sn | MLX5_CQ_DBR_CMD_ALL | cq_ci;
108 uint64_t doorbell = ((uint64_t)doorbell_hi << 32) | cq->cq_obj.cq->id;
109 uint64_t db_be = rte_cpu_to_be_64(doorbell);
110 uint32_t *addr = RTE_PTR_ADD(priv->uar->base_addr, MLX5_CQ_DOORBELL);
113 cq->cq_obj.db_rec[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
116 *(uint64_t *)addr = db_be;
118 *(uint32_t *)addr = db_be;
120 *((uint32_t *)addr + 1) = db_be >> 32;
127 mlx5_vdpa_cq_create(struct mlx5_vdpa_priv *priv, uint16_t log_desc_n,
128 int callfd, struct mlx5_vdpa_cq *cq)
130 struct mlx5_devx_cq_attr attr = {
132 .uar_page_id = priv->uar->page_id,
134 uint16_t event_nums[1] = {0};
137 ret = mlx5_devx_cq_create(priv->ctx, &cq->cq_obj, log_desc_n, &attr,
142 cq->log_desc_n = log_desc_n;
143 rte_spinlock_init(&cq->sl);
144 /* Subscribe CQ event to the event channel controlled by the driver. */
145 ret = mlx5_os_devx_subscribe_devx_event(priv->eventc,
147 sizeof(event_nums), event_nums,
148 (uint64_t)(uintptr_t)cq);
150 DRV_LOG(ERR, "Failed to subscribe CQE event.");
155 /* Init CQ to ones to be in HW owner in the start. */
156 cq->cq_obj.cqes[0].op_own = MLX5_CQE_OWNER_MASK;
157 cq->cq_obj.cqes[0].wqe_counter = rte_cpu_to_be_16(UINT16_MAX);
159 mlx5_vdpa_cq_arm(priv, cq);
162 mlx5_vdpa_cq_destroy(cq);
166 static inline uint32_t
167 mlx5_vdpa_cq_poll(struct mlx5_vdpa_cq *cq)
169 struct mlx5_vdpa_event_qp *eqp =
170 container_of(cq, struct mlx5_vdpa_event_qp, cq);
171 const unsigned int cq_size = 1 << cq->log_desc_n;
174 uint16_t wqe_counter;
180 uint16_t next_wqe_counter = cq->cq_ci;
181 uint16_t cur_wqe_counter;
184 last_word.word = rte_read32(&cq->cq_obj.cqes[0].wqe_counter);
185 cur_wqe_counter = rte_be_to_cpu_16(last_word.wqe_counter);
186 comp = cur_wqe_counter + (uint16_t)1 - next_wqe_counter;
189 MLX5_ASSERT(MLX5_CQE_OPCODE(last_word.op_own) !=
191 if (unlikely(!(MLX5_CQE_OPCODE(last_word.op_own) ==
193 MLX5_CQE_OPCODE(last_word.op_own) ==
197 /* Ring CQ doorbell record. */
198 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
200 /* Ring SW QP doorbell record. */
201 eqp->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci + cq_size);
207 mlx5_vdpa_arm_all_cqs(struct mlx5_vdpa_priv *priv)
209 struct mlx5_vdpa_cq *cq;
212 for (i = 0; i < priv->nr_virtqs; i++) {
213 cq = &priv->virtqs[i].eqp.cq;
214 if (cq->cq_obj.cq && !cq->armed)
215 mlx5_vdpa_cq_arm(priv, cq);
220 mlx5_vdpa_timer_sleep(struct mlx5_vdpa_priv *priv, uint32_t max)
222 if (priv->event_mode == MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER) {
225 priv->timer_delay_us += priv->event_us;
230 priv->timer_delay_us /= max;
234 if (priv->timer_delay_us)
235 usleep(priv->timer_delay_us);
237 /* Give-up CPU to improve polling threads scheduling. */
242 mlx5_vdpa_poll_handle(void *arg)
244 struct mlx5_vdpa_priv *priv = arg;
246 struct mlx5_vdpa_cq *cq;
248 uint64_t current_tic;
250 pthread_mutex_lock(&priv->timer_lock);
251 while (!priv->timer_on)
252 pthread_cond_wait(&priv->timer_cond, &priv->timer_lock);
253 pthread_mutex_unlock(&priv->timer_lock);
254 priv->timer_delay_us = priv->event_mode ==
255 MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER ?
256 MLX5_VDPA_DEFAULT_TIMER_DELAY_US :
260 pthread_mutex_lock(&priv->vq_config_lock);
261 for (i = 0; i < priv->nr_virtqs; i++) {
262 cq = &priv->virtqs[i].eqp.cq;
263 if (cq->cq_obj.cq && !cq->armed) {
264 uint32_t comp = mlx5_vdpa_cq_poll(cq);
267 /* Notify guest for descs consuming. */
268 if (cq->callfd != -1)
269 eventfd_write(cq->callfd,
276 current_tic = rte_rdtsc();
278 /* No traffic ? stop timer and load interrupts. */
279 if (current_tic - priv->last_traffic_tic >=
280 rte_get_timer_hz() * priv->no_traffic_time_s) {
281 DRV_LOG(DEBUG, "Device %s traffic was stopped.",
282 priv->vdev->device->name);
283 mlx5_vdpa_arm_all_cqs(priv);
284 pthread_mutex_unlock(&priv->vq_config_lock);
285 pthread_mutex_lock(&priv->timer_lock);
287 while (!priv->timer_on)
288 pthread_cond_wait(&priv->timer_cond,
290 pthread_mutex_unlock(&priv->timer_lock);
291 priv->timer_delay_us = priv->event_mode ==
292 MLX5_VDPA_EVENT_MODE_DYNAMIC_TIMER ?
293 MLX5_VDPA_DEFAULT_TIMER_DELAY_US :
298 priv->last_traffic_tic = current_tic;
300 pthread_mutex_unlock(&priv->vq_config_lock);
301 mlx5_vdpa_timer_sleep(priv, max);
307 mlx5_vdpa_interrupt_handler(void *cb_arg)
309 struct mlx5_vdpa_priv *priv = cb_arg;
310 #ifdef HAVE_IBV_DEVX_EVENT
312 struct mlx5dv_devx_async_event_hdr event_resp;
313 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
316 pthread_mutex_lock(&priv->vq_config_lock);
317 while (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,
319 (ssize_t)sizeof(out.event_resp.cookie)) {
320 struct mlx5_vdpa_cq *cq = (struct mlx5_vdpa_cq *)
321 (uintptr_t)out.event_resp.cookie;
322 struct mlx5_vdpa_event_qp *eqp = container_of(cq,
323 struct mlx5_vdpa_event_qp, cq);
324 struct mlx5_vdpa_virtq *virtq = container_of(eqp,
325 struct mlx5_vdpa_virtq, eqp);
329 mlx5_vdpa_cq_poll(cq);
330 /* Notify guest for descs consuming. */
331 if (cq->callfd != -1)
332 eventfd_write(cq->callfd, (eventfd_t)1);
333 if (priv->event_mode == MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT) {
334 mlx5_vdpa_cq_arm(priv, cq);
335 pthread_mutex_unlock(&priv->vq_config_lock);
338 /* Don't arm again - timer will take control. */
339 DRV_LOG(DEBUG, "Device %s virtq %d cq %d event was captured."
340 " Timer is %s, cq ci is %u.\n",
341 priv->vdev->device->name,
342 (int)virtq->index, cq->cq_obj.cq->id,
343 priv->timer_on ? "on" : "off", cq->cq_ci);
348 /* Traffic detected: make sure timer is on. */
349 priv->last_traffic_tic = rte_rdtsc();
350 pthread_mutex_lock(&priv->timer_lock);
351 if (!priv->timer_on) {
353 pthread_cond_signal(&priv->timer_cond);
355 pthread_mutex_unlock(&priv->timer_lock);
356 pthread_mutex_unlock(&priv->vq_config_lock);
360 mlx5_vdpa_err_interrupt_handler(void *cb_arg __rte_unused)
362 #ifdef HAVE_IBV_DEVX_EVENT
363 struct mlx5_vdpa_priv *priv = cb_arg;
365 struct mlx5dv_devx_async_event_hdr event_resp;
366 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
368 uint32_t vq_index, i, version;
369 struct mlx5_vdpa_virtq *virtq;
372 pthread_mutex_lock(&priv->vq_config_lock);
373 while (mlx5_glue->devx_get_event(priv->err_chnl, &out.event_resp,
375 (ssize_t)sizeof(out.event_resp.cookie)) {
376 vq_index = out.event_resp.cookie & UINT32_MAX;
377 version = out.event_resp.cookie >> 32;
378 if (vq_index >= priv->nr_virtqs) {
379 DRV_LOG(ERR, "Invalid device %s error event virtq %d.",
380 priv->vdev->device->name, vq_index);
383 virtq = &priv->virtqs[vq_index];
384 if (!virtq->enable || virtq->version != version)
386 if (rte_rdtsc() / rte_get_tsc_hz() < MLX5_VDPA_ERROR_TIME_SEC)
388 virtq->stopped = true;
389 /* Query error info. */
390 if (mlx5_vdpa_virtq_query(priv, vq_index))
393 if (mlx5_vdpa_virtq_enable(priv, vq_index, 0)) {
394 DRV_LOG(ERR, "Failed to disable virtq %d.", vq_index);
397 /* Retry if error happens less than N times in 3 seconds. */
398 sec = (rte_rdtsc() - virtq->err_time[0]) / rte_get_tsc_hz();
399 if (sec > MLX5_VDPA_ERROR_TIME_SEC) {
401 if (mlx5_vdpa_virtq_enable(priv, vq_index, 1))
402 DRV_LOG(ERR, "Failed to enable virtq %d.",
405 DRV_LOG(WARNING, "Recover virtq %d: %u.",
406 vq_index, ++virtq->n_retry);
408 /* Retry timeout, give up. */
409 DRV_LOG(ERR, "Device %s virtq %d failed to recover.",
410 priv->vdev->device->name, vq_index);
413 /* Shift in current time to error time log end. */
414 for (i = 1; i < RTE_DIM(virtq->err_time); i++)
415 virtq->err_time[i - 1] = virtq->err_time[i];
416 virtq->err_time[RTE_DIM(virtq->err_time) - 1] = rte_rdtsc();
418 pthread_mutex_unlock(&priv->vq_config_lock);
423 mlx5_vdpa_err_event_setup(struct mlx5_vdpa_priv *priv)
428 /* Setup device event channel. */
429 priv->err_chnl = mlx5_glue->devx_create_event_channel(priv->ctx, 0);
430 if (!priv->err_chnl) {
432 DRV_LOG(ERR, "Failed to create device event channel %d.",
436 flags = fcntl(priv->err_chnl->fd, F_GETFL);
437 ret = fcntl(priv->err_chnl->fd, F_SETFL, flags | O_NONBLOCK);
439 DRV_LOG(ERR, "Failed to change device event channel FD.");
442 priv->err_intr_handle.fd = priv->err_chnl->fd;
443 priv->err_intr_handle.type = RTE_INTR_HANDLE_EXT;
444 if (rte_intr_callback_register(&priv->err_intr_handle,
445 mlx5_vdpa_err_interrupt_handler,
447 priv->err_intr_handle.fd = 0;
448 DRV_LOG(ERR, "Failed to register error interrupt for device %d.",
452 DRV_LOG(DEBUG, "Registered error interrupt for device%d.",
457 mlx5_vdpa_err_event_unset(priv);
462 mlx5_vdpa_err_event_unset(struct mlx5_vdpa_priv *priv)
464 int retries = MLX5_VDPA_INTR_RETRIES;
467 if (!priv->err_intr_handle.fd)
469 while (retries-- && ret == -EAGAIN) {
470 ret = rte_intr_callback_unregister(&priv->err_intr_handle,
471 mlx5_vdpa_err_interrupt_handler,
473 if (ret == -EAGAIN) {
474 DRV_LOG(DEBUG, "Try again to unregister fd %d "
475 "of error interrupt, retries = %d.",
476 priv->err_intr_handle.fd, retries);
480 memset(&priv->err_intr_handle, 0, sizeof(priv->err_intr_handle));
481 if (priv->err_chnl) {
482 #ifdef HAVE_IBV_DEVX_EVENT
484 struct mlx5dv_devx_async_event_hdr event_resp;
485 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) +
489 /* Clean all pending events. */
490 while (mlx5_glue->devx_get_event(priv->err_chnl,
491 &out.event_resp, sizeof(out.buf)) >=
492 (ssize_t)sizeof(out.event_resp.cookie))
495 mlx5_glue->devx_destroy_event_channel(priv->err_chnl);
496 priv->err_chnl = NULL;
501 mlx5_vdpa_cqe_event_setup(struct mlx5_vdpa_priv *priv)
507 const struct sched_param sp = {
508 .sched_priority = sched_get_priority_max(SCHED_RR),
512 /* All virtqs are in poll mode. */
514 if (priv->event_mode != MLX5_VDPA_EVENT_MODE_ONLY_INTERRUPT) {
515 pthread_mutex_init(&priv->timer_lock, NULL);
516 pthread_cond_init(&priv->timer_cond, NULL);
518 pthread_attr_init(&attr);
519 ret = pthread_attr_setschedpolicy(&attr, SCHED_RR);
521 DRV_LOG(ERR, "Failed to set thread sched policy = RR.");
524 ret = pthread_attr_setschedparam(&attr, &sp);
526 DRV_LOG(ERR, "Failed to set thread priority.");
529 ret = pthread_create(&priv->timer_tid, &attr,
530 mlx5_vdpa_poll_handle, (void *)priv);
532 DRV_LOG(ERR, "Failed to create timer thread.");
536 if (priv->event_core != -1)
537 CPU_SET(priv->event_core, &cpuset);
539 cpuset = rte_lcore_cpuset(rte_get_main_lcore());
540 ret = pthread_setaffinity_np(priv->timer_tid,
541 sizeof(cpuset), &cpuset);
543 DRV_LOG(ERR, "Failed to set thread affinity.");
546 snprintf(name, sizeof(name), "vDPA-mlx5-%d", priv->vid);
547 ret = pthread_setname_np(priv->timer_tid, name);
549 DRV_LOG(ERR, "Failed to set timer thread name.");
553 priv->intr_handle.fd = priv->eventc->fd;
554 priv->intr_handle.type = RTE_INTR_HANDLE_EXT;
555 if (rte_intr_callback_register(&priv->intr_handle,
556 mlx5_vdpa_interrupt_handler, priv)) {
557 priv->intr_handle.fd = 0;
558 DRV_LOG(ERR, "Failed to register CQE interrupt %d.", rte_errno);
563 mlx5_vdpa_cqe_event_unset(priv);
568 mlx5_vdpa_cqe_event_unset(struct mlx5_vdpa_priv *priv)
570 int retries = MLX5_VDPA_INTR_RETRIES;
574 if (priv->intr_handle.fd) {
575 while (retries-- && ret == -EAGAIN) {
576 ret = rte_intr_callback_unregister(&priv->intr_handle,
577 mlx5_vdpa_interrupt_handler,
579 if (ret == -EAGAIN) {
580 DRV_LOG(DEBUG, "Try again to unregister fd %d "
581 "of CQ interrupt, retries = %d.",
582 priv->intr_handle.fd, retries);
586 memset(&priv->intr_handle, 0, sizeof(priv->intr_handle));
588 if (priv->timer_tid) {
589 pthread_cancel(priv->timer_tid);
590 pthread_join(priv->timer_tid, &status);
596 mlx5_vdpa_event_qp_destroy(struct mlx5_vdpa_event_qp *eqp)
599 claim_zero(mlx5_devx_cmd_destroy(eqp->sw_qp));
601 claim_zero(mlx5_glue->devx_umem_dereg(eqp->umem_obj));
603 rte_free(eqp->umem_buf);
605 claim_zero(mlx5_devx_cmd_destroy(eqp->fw_qp));
606 mlx5_vdpa_cq_destroy(&eqp->cq);
607 memset(eqp, 0, sizeof(*eqp));
611 mlx5_vdpa_qps2rts(struct mlx5_vdpa_event_qp *eqp)
613 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RST2INIT_QP,
615 DRV_LOG(ERR, "Failed to modify FW QP to INIT state(%u).",
619 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RST2INIT_QP,
621 DRV_LOG(ERR, "Failed to modify SW QP to INIT state(%u).",
625 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_INIT2RTR_QP,
627 DRV_LOG(ERR, "Failed to modify FW QP to RTR state(%u).",
631 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_INIT2RTR_QP,
633 DRV_LOG(ERR, "Failed to modify SW QP to RTR state(%u).",
637 if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RTR2RTS_QP,
639 DRV_LOG(ERR, "Failed to modify FW QP to RTS state(%u).",
643 if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RTR2RTS_QP,
645 DRV_LOG(ERR, "Failed to modify SW QP to RTS state(%u).",
653 mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,
654 int callfd, struct mlx5_vdpa_event_qp *eqp)
656 struct mlx5_devx_qp_attr attr = {0};
657 uint16_t log_desc_n = rte_log2_u32(desc_n);
658 uint32_t umem_size = (1 << log_desc_n) * MLX5_WSEG_SIZE +
659 sizeof(*eqp->db_rec) * 2;
661 if (mlx5_vdpa_event_qp_global_prepare(priv))
663 if (mlx5_vdpa_cq_create(priv, log_desc_n, callfd, &eqp->cq))
666 attr.ts_format = mlx5_ts_format_conv(priv->qp_ts_format);
667 eqp->fw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
669 DRV_LOG(ERR, "Failed to create FW QP(%u).", rte_errno);
672 eqp->umem_buf = rte_zmalloc(__func__, umem_size, 4096);
673 if (!eqp->umem_buf) {
674 DRV_LOG(ERR, "Failed to allocate memory for SW QP.");
678 eqp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
679 (void *)(uintptr_t)eqp->umem_buf,
681 IBV_ACCESS_LOCAL_WRITE);
682 if (!eqp->umem_obj) {
683 DRV_LOG(ERR, "Failed to register umem for SW QP.");
686 attr.uar_index = priv->uar->page_id;
687 attr.cqn = eqp->cq.cq_obj.cq->id;
688 attr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE));
689 attr.rq_size = 1 << log_desc_n;
690 attr.log_rq_stride = rte_log2_u32(MLX5_WSEG_SIZE);
691 attr.sq_size = 0; /* No need SQ. */
692 attr.dbr_umem_valid = 1;
693 attr.wq_umem_id = eqp->umem_obj->umem_id;
694 attr.wq_umem_offset = 0;
695 attr.dbr_umem_id = eqp->umem_obj->umem_id;
696 attr.dbr_address = (1 << log_desc_n) * MLX5_WSEG_SIZE;
697 attr.ts_format = mlx5_ts_format_conv(priv->qp_ts_format);
698 eqp->sw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
700 DRV_LOG(ERR, "Failed to create SW QP(%u).", rte_errno);
703 eqp->db_rec = RTE_PTR_ADD(eqp->umem_buf, (uintptr_t)attr.dbr_address);
704 if (mlx5_vdpa_qps2rts(eqp))
707 rte_write32(rte_cpu_to_be_32(1 << log_desc_n), &eqp->db_rec[0]);
710 mlx5_vdpa_event_qp_destroy(eqp);