1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
8 #include <rte_malloc.h>
12 #include <mlx5_common.h>
14 #include "mlx5_vdpa_utils.h"
15 #include "mlx5_vdpa.h"
19 mlx5_vdpa_virtq_handler(void *cb_arg)
21 struct mlx5_vdpa_virtq *virtq = cb_arg;
22 struct mlx5_vdpa_priv *priv = virtq->priv;
27 nbytes = read(virtq->intr_handle.fd, &buf, 8);
30 errno == EWOULDBLOCK ||
33 DRV_LOG(ERR, "Failed to read kickfd of virtq %d: %s",
34 virtq->index, strerror(errno));
38 rte_write32(virtq->index, priv->virtq_db_addr);
39 DRV_LOG(DEBUG, "Ring virtq %u doorbell.", virtq->index);
43 mlx5_vdpa_virtq_unset(struct mlx5_vdpa_virtq *virtq)
46 int retries = MLX5_VDPA_INTR_RETRIES;
49 if (virtq->intr_handle.fd != -1) {
50 while (retries-- && ret == -EAGAIN) {
51 ret = rte_intr_callback_unregister(&virtq->intr_handle,
52 mlx5_vdpa_virtq_handler,
55 DRV_LOG(DEBUG, "Try again to unregister fd %d "
56 "of virtq %d interrupt, retries = %d.",
57 virtq->intr_handle.fd,
58 (int)virtq->index, retries);
59 usleep(MLX5_VDPA_INTR_RETRIES_USEC);
62 virtq->intr_handle.fd = -1;
65 claim_zero(mlx5_devx_cmd_destroy(virtq->virtq));
67 for (i = 0; i < RTE_DIM(virtq->umems); ++i) {
68 if (virtq->umems[i].obj)
69 claim_zero(mlx5_glue->devx_umem_dereg
70 (virtq->umems[i].obj));
71 if (virtq->umems[i].buf)
72 rte_free(virtq->umems[i].buf);
74 memset(&virtq->umems, 0, sizeof(virtq->umems));
75 if (virtq->counters) {
76 claim_zero(mlx5_devx_cmd_destroy(virtq->counters));
77 virtq->counters = NULL;
79 memset(&virtq->reset, 0, sizeof(virtq->reset));
81 mlx5_vdpa_event_qp_destroy(&virtq->eqp);
86 mlx5_vdpa_virtqs_release(struct mlx5_vdpa_priv *priv)
90 for (i = 0; i < priv->nr_virtqs; i++) {
91 mlx5_vdpa_virtq_unset(&priv->virtqs[i]);
92 priv->virtqs[i].enable = 0;
95 claim_zero(mlx5_devx_cmd_destroy(priv->tis));
99 claim_zero(mlx5_devx_cmd_destroy(priv->td));
102 if (priv->virtq_db_addr) {
103 claim_zero(munmap(priv->virtq_db_addr, priv->var->length));
104 priv->virtq_db_addr = NULL;
111 mlx5_vdpa_virtq_modify(struct mlx5_vdpa_virtq *virtq, int state)
113 struct mlx5_devx_virtq_attr attr = {
114 .type = MLX5_VIRTQ_MODIFY_TYPE_STATE,
115 .state = state ? MLX5_VIRTQ_STATE_RDY :
116 MLX5_VIRTQ_STATE_SUSPEND,
117 .queue_index = virtq->index,
120 return mlx5_devx_cmd_modify_virtq(virtq->virtq, &attr);
124 mlx5_vdpa_virtq_stop(struct mlx5_vdpa_priv *priv, int index)
126 struct mlx5_devx_virtq_attr attr = {0};
127 struct mlx5_vdpa_virtq *virtq = &priv->virtqs[index];
128 int ret = mlx5_vdpa_virtq_modify(virtq, 0);
132 if (mlx5_devx_cmd_query_virtq(virtq->virtq, &attr)) {
133 DRV_LOG(ERR, "Failed to query virtq %d.", index);
136 DRV_LOG(INFO, "Query vid %d vring %d: hw_available_idx=%d, "
137 "hw_used_index=%d", priv->vid, index,
138 attr.hw_available_index, attr.hw_used_index);
139 ret = rte_vhost_set_vring_base(priv->vid, index,
140 attr.hw_available_index,
143 DRV_LOG(ERR, "Failed to set virtq %d base.", index);
150 mlx5_vdpa_hva_to_gpa(struct rte_vhost_memory *mem, uint64_t hva)
152 struct rte_vhost_mem_region *reg;
156 for (i = 0; i < mem->nregions; i++) {
157 reg = &mem->regions[i];
158 if (hva >= reg->host_user_addr &&
159 hva < reg->host_user_addr + reg->size) {
160 gpa = hva - reg->host_user_addr + reg->guest_phys_addr;
168 mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index)
170 struct mlx5_vdpa_virtq *virtq = &priv->virtqs[index];
171 struct rte_vhost_vring vq;
172 struct mlx5_devx_virtq_attr attr = {0};
176 uint16_t last_avail_idx;
177 uint16_t last_used_idx;
179 ret = rte_vhost_get_vhost_vring(priv->vid, index, &vq);
182 virtq->index = index;
183 virtq->vq_size = vq.size;
184 attr.tso_ipv4 = !!(priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO4));
185 attr.tso_ipv6 = !!(priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO6));
186 attr.tx_csum = !!(priv->features & (1ULL << VIRTIO_NET_F_CSUM));
187 attr.rx_csum = !!(priv->features & (1ULL << VIRTIO_NET_F_GUEST_CSUM));
188 attr.virtio_version_1_0 = !!(priv->features & (1ULL <<
189 VIRTIO_F_VERSION_1));
190 attr.type = (priv->features & (1ULL << VIRTIO_F_RING_PACKED)) ?
191 MLX5_VIRTQ_TYPE_PACKED : MLX5_VIRTQ_TYPE_SPLIT;
193 * No need event QPs creation when the guest in poll mode or when the
194 * capability allows it.
196 attr.event_mode = vq.callfd != -1 || !(priv->caps.event_mode & (1 <<
197 MLX5_VIRTQ_EVENT_MODE_NO_MSIX)) ?
198 MLX5_VIRTQ_EVENT_MODE_QP :
199 MLX5_VIRTQ_EVENT_MODE_NO_MSIX;
200 if (attr.event_mode == MLX5_VIRTQ_EVENT_MODE_QP) {
201 ret = mlx5_vdpa_event_qp_create(priv, vq.size, vq.callfd,
204 DRV_LOG(ERR, "Failed to create event QPs for virtq %d.",
208 attr.qp_id = virtq->eqp.fw_qp->id;
210 DRV_LOG(INFO, "Virtq %d is, for sure, working by poll mode, no"
211 " need event QPs and event mechanism.", index);
213 if (priv->caps.queue_counters_valid) {
214 virtq->counters = mlx5_devx_cmd_create_virtio_q_counters
216 if (!virtq->counters) {
217 DRV_LOG(ERR, "Failed to create virtq couners for virtq"
221 attr.counters_obj_id = virtq->counters->id;
223 /* Setup 3 UMEMs for each virtq. */
224 for (i = 0; i < RTE_DIM(virtq->umems); ++i) {
225 virtq->umems[i].size = priv->caps.umems[i].a * vq.size +
226 priv->caps.umems[i].b;
227 virtq->umems[i].buf = rte_zmalloc(__func__,
228 virtq->umems[i].size, 4096);
229 if (!virtq->umems[i].buf) {
230 DRV_LOG(ERR, "Cannot allocate umem %d memory for virtq"
234 virtq->umems[i].obj = mlx5_glue->devx_umem_reg(priv->ctx,
236 virtq->umems[i].size,
237 IBV_ACCESS_LOCAL_WRITE);
238 if (!virtq->umems[i].obj) {
239 DRV_LOG(ERR, "Failed to register umem %d for virtq %u.",
243 attr.umems[i].id = virtq->umems[i].obj->umem_id;
244 attr.umems[i].offset = 0;
245 attr.umems[i].size = virtq->umems[i].size;
247 if (attr.type == MLX5_VIRTQ_TYPE_SPLIT) {
248 gpa = mlx5_vdpa_hva_to_gpa(priv->vmem,
249 (uint64_t)(uintptr_t)vq.desc);
251 DRV_LOG(ERR, "Failed to get descriptor ring GPA.");
254 attr.desc_addr = gpa;
255 gpa = mlx5_vdpa_hva_to_gpa(priv->vmem,
256 (uint64_t)(uintptr_t)vq.used);
258 DRV_LOG(ERR, "Failed to get GPA for used ring.");
261 attr.used_addr = gpa;
262 gpa = mlx5_vdpa_hva_to_gpa(priv->vmem,
263 (uint64_t)(uintptr_t)vq.avail);
265 DRV_LOG(ERR, "Failed to get GPA for available ring.");
268 attr.available_addr = gpa;
270 ret = rte_vhost_get_vring_base(priv->vid, index, &last_avail_idx,
275 DRV_LOG(WARNING, "Couldn't get vring base, idx are set to 0");
277 DRV_LOG(INFO, "vid %d: Init last_avail_idx=%d, last_used_idx=%d for "
278 "virtq %d.", priv->vid, last_avail_idx,
279 last_used_idx, index);
281 attr.hw_available_index = last_avail_idx;
282 attr.hw_used_index = last_used_idx;
283 attr.q_size = vq.size;
284 attr.mkey = priv->gpa_mkey_index;
285 attr.tis_id = priv->tis->id;
286 attr.queue_index = index;
288 virtq->virtq = mlx5_devx_cmd_create_virtq(priv->ctx, &attr);
292 if (mlx5_vdpa_virtq_modify(virtq, 1))
295 rte_write32(virtq->index, priv->virtq_db_addr);
296 /* Setup doorbell mapping. */
297 virtq->intr_handle.fd = vq.kickfd;
298 if (virtq->intr_handle.fd == -1) {
299 DRV_LOG(WARNING, "Virtq %d kickfd is invalid.", index);
300 if (!priv->direct_notifier) {
301 DRV_LOG(ERR, "Virtq %d cannot be notified.", index);
305 virtq->intr_handle.type = RTE_INTR_HANDLE_EXT;
306 if (rte_intr_callback_register(&virtq->intr_handle,
307 mlx5_vdpa_virtq_handler,
309 virtq->intr_handle.fd = -1;
310 DRV_LOG(ERR, "Failed to register virtq %d interrupt.",
314 DRV_LOG(DEBUG, "Register fd %d interrupt for virtq %d.",
315 virtq->intr_handle.fd, index);
320 mlx5_vdpa_virtq_unset(virtq);
325 mlx5_vdpa_features_validate(struct mlx5_vdpa_priv *priv)
327 if (priv->features & (1ULL << VIRTIO_F_RING_PACKED)) {
328 if (!(priv->caps.virtio_queue_type & (1 <<
329 MLX5_VIRTQ_TYPE_PACKED))) {
330 DRV_LOG(ERR, "Failed to configur PACKED mode for vdev "
331 "%d - it was not reported by HW/driver"
332 " capability.", priv->vid);
336 if (priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO4)) {
337 if (!priv->caps.tso_ipv4) {
338 DRV_LOG(ERR, "Failed to enable TSO4 for vdev %d - TSO4"
339 " was not reported by HW/driver capability.",
344 if (priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO6)) {
345 if (!priv->caps.tso_ipv6) {
346 DRV_LOG(ERR, "Failed to enable TSO6 for vdev %d - TSO6"
347 " was not reported by HW/driver capability.",
352 if (priv->features & (1ULL << VIRTIO_NET_F_CSUM)) {
353 if (!priv->caps.tx_csum) {
354 DRV_LOG(ERR, "Failed to enable CSUM for vdev %d - CSUM"
355 " was not reported by HW/driver capability.",
360 if (priv->features & (1ULL << VIRTIO_NET_F_GUEST_CSUM)) {
361 if (!priv->caps.rx_csum) {
362 DRV_LOG(ERR, "Failed to enable GUEST CSUM for vdev %d"
363 " GUEST CSUM was not reported by HW/driver "
364 "capability.", priv->vid);
368 if (priv->features & (1ULL << VIRTIO_F_VERSION_1)) {
369 if (!priv->caps.virtio_version_1_0) {
370 DRV_LOG(ERR, "Failed to enable version 1 for vdev %d "
371 "version 1 was not reported by HW/driver"
372 " capability.", priv->vid);
380 mlx5_vdpa_virtqs_prepare(struct mlx5_vdpa_priv *priv)
382 struct mlx5_devx_tis_attr tis_attr = {0};
384 uint16_t nr_vring = rte_vhost_get_vring_num(priv->vid);
385 int ret = rte_vhost_get_negotiated_features(priv->vid, &priv->features);
387 if (ret || mlx5_vdpa_features_validate(priv)) {
388 DRV_LOG(ERR, "Failed to configure negotiated features.");
391 if (nr_vring > priv->caps.max_num_virtio_queues * 2) {
392 DRV_LOG(ERR, "Do not support more than %d virtqs(%d).",
393 (int)priv->caps.max_num_virtio_queues * 2,
397 /* Always map the entire page. */
398 priv->virtq_db_addr = mmap(NULL, priv->var->length, PROT_READ |
399 PROT_WRITE, MAP_SHARED, priv->ctx->cmd_fd,
400 priv->var->mmap_off);
401 if (priv->virtq_db_addr == MAP_FAILED) {
402 DRV_LOG(ERR, "Failed to map doorbell page %u.", errno);
403 priv->virtq_db_addr = NULL;
406 DRV_LOG(DEBUG, "VAR address of doorbell mapping is %p.",
407 priv->virtq_db_addr);
409 priv->td = mlx5_devx_cmd_create_td(priv->ctx);
411 DRV_LOG(ERR, "Failed to create transport domain.");
414 tis_attr.transport_domain = priv->td->id;
415 priv->tis = mlx5_devx_cmd_create_tis(priv->ctx, &tis_attr);
417 DRV_LOG(ERR, "Failed to create TIS.");
420 priv->nr_virtqs = nr_vring;
421 for (i = 0; i < nr_vring; i++) {
422 claim_zero(rte_vhost_enable_guest_notification(priv->vid, i,
424 if (mlx5_vdpa_virtq_setup(priv, i))
429 mlx5_vdpa_virtqs_release(priv);
434 mlx5_vdpa_virtq_enable(struct mlx5_vdpa_priv *priv, int index, int enable)
436 struct mlx5_vdpa_virtq *virtq = &priv->virtqs[index];
439 DRV_LOG(INFO, "Update virtq %d status %sable -> %sable.", index,
440 virtq->enable ? "en" : "dis", enable ? "en" : "dis");
441 if (virtq->enable == !!enable)
443 if (!priv->configured) {
444 virtq->enable = !!enable;
448 /* Configuration might have been updated - reconfigure virtq. */
450 ret = mlx5_vdpa_virtq_stop(priv, index);
452 DRV_LOG(WARNING, "Failed to stop virtq %d.",
454 mlx5_vdpa_virtq_unset(virtq);
456 ret = mlx5_vdpa_virtq_setup(priv, index);
458 DRV_LOG(ERR, "Failed to setup virtq %d.", index);
460 /* The only case virtq can stay invalid. */
463 virtq->enable = !!enable;
464 if (is_virtq_recvq(virtq->index, priv->nr_virtqs)) {
465 /* Need to add received virtq to the RQT table of the TIRs. */
466 ret = mlx5_vdpa_steer_update(priv);
468 virtq->enable = !enable;
476 mlx5_vdpa_virtq_stats_get(struct mlx5_vdpa_priv *priv, int qid,
477 struct rte_vdpa_stat *stats, unsigned int n)
479 struct mlx5_vdpa_virtq *virtq = &priv->virtqs[qid];
480 struct mlx5_devx_virtio_q_couners_attr attr = {0};
483 if (!virtq->virtq || !virtq->enable) {
484 DRV_LOG(ERR, "Failed to read virtq %d statistics - virtq "
488 MLX5_ASSERT(virtq->counters);
489 ret = mlx5_devx_cmd_query_virtio_q_counters(virtq->counters, &attr);
491 DRV_LOG(ERR, "Failed to read virtq %d stats from HW.", qid);
494 ret = (int)RTE_MIN(n, (unsigned int)MLX5_VDPA_STATS_MAX);
495 if (ret == MLX5_VDPA_STATS_RECEIVED_DESCRIPTORS)
497 stats[MLX5_VDPA_STATS_RECEIVED_DESCRIPTORS] = (struct rte_vdpa_stat) {
498 .id = MLX5_VDPA_STATS_RECEIVED_DESCRIPTORS,
499 .value = attr.received_desc - virtq->reset.received_desc,
501 if (ret == MLX5_VDPA_STATS_COMPLETED_DESCRIPTORS)
503 stats[MLX5_VDPA_STATS_COMPLETED_DESCRIPTORS] = (struct rte_vdpa_stat) {
504 .id = MLX5_VDPA_STATS_COMPLETED_DESCRIPTORS,
505 .value = attr.completed_desc - virtq->reset.completed_desc,
507 if (ret == MLX5_VDPA_STATS_BAD_DESCRIPTOR_ERRORS)
509 stats[MLX5_VDPA_STATS_BAD_DESCRIPTOR_ERRORS] = (struct rte_vdpa_stat) {
510 .id = MLX5_VDPA_STATS_BAD_DESCRIPTOR_ERRORS,
511 .value = attr.bad_desc_errors - virtq->reset.bad_desc_errors,
513 if (ret == MLX5_VDPA_STATS_EXCEED_MAX_CHAIN)
515 stats[MLX5_VDPA_STATS_EXCEED_MAX_CHAIN] = (struct rte_vdpa_stat) {
516 .id = MLX5_VDPA_STATS_EXCEED_MAX_CHAIN,
517 .value = attr.exceed_max_chain - virtq->reset.exceed_max_chain,
519 if (ret == MLX5_VDPA_STATS_INVALID_BUFFER)
521 stats[MLX5_VDPA_STATS_INVALID_BUFFER] = (struct rte_vdpa_stat) {
522 .id = MLX5_VDPA_STATS_INVALID_BUFFER,
523 .value = attr.invalid_buffer - virtq->reset.invalid_buffer,
525 if (ret == MLX5_VDPA_STATS_COMPLETION_ERRORS)
527 stats[MLX5_VDPA_STATS_COMPLETION_ERRORS] = (struct rte_vdpa_stat) {
528 .id = MLX5_VDPA_STATS_COMPLETION_ERRORS,
529 .value = attr.error_cqes - virtq->reset.error_cqes,
535 mlx5_vdpa_virtq_stats_reset(struct mlx5_vdpa_priv *priv, int qid)
537 struct mlx5_vdpa_virtq *virtq = &priv->virtqs[qid];
540 if (!virtq->virtq || !virtq->enable) {
541 DRV_LOG(ERR, "Failed to read virtq %d statistics - virtq "
545 MLX5_ASSERT(virtq->counters);
546 ret = mlx5_devx_cmd_query_virtio_q_counters(virtq->counters,
549 DRV_LOG(ERR, "Failed to read virtq %d reset stats from HW.",