1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
8 #include <rte_malloc.h>
12 #include <mlx5_common.h>
14 #include "mlx5_vdpa_utils.h"
15 #include "mlx5_vdpa.h"
19 mlx5_vdpa_virtq_handler(void *cb_arg)
21 struct mlx5_vdpa_virtq *virtq = cb_arg;
22 struct mlx5_vdpa_priv *priv = virtq->priv;
27 nbytes = read(virtq->intr_handle.fd, &buf, 8);
30 errno == EWOULDBLOCK ||
33 DRV_LOG(ERR, "Failed to read kickfd of virtq %d: %s",
34 virtq->index, strerror(errno));
38 rte_write32(virtq->index, priv->virtq_db_addr);
39 if (virtq->notifier_state == MLX5_VDPA_NOTIFIER_STATE_DISABLED) {
40 if (rte_vhost_host_notifier_ctrl(priv->vid, virtq->index, true))
41 virtq->notifier_state = MLX5_VDPA_NOTIFIER_STATE_ERR;
43 virtq->notifier_state =
44 MLX5_VDPA_NOTIFIER_STATE_ENABLED;
45 DRV_LOG(INFO, "Virtq %u notifier state is %s.", virtq->index,
46 virtq->notifier_state ==
47 MLX5_VDPA_NOTIFIER_STATE_ENABLED ? "enabled" :
50 DRV_LOG(DEBUG, "Ring virtq %u doorbell.", virtq->index);
54 mlx5_vdpa_virtq_unset(struct mlx5_vdpa_virtq *virtq)
57 int retries = MLX5_VDPA_INTR_RETRIES;
60 if (virtq->intr_handle.fd != -1) {
61 while (retries-- && ret == -EAGAIN) {
62 ret = rte_intr_callback_unregister(&virtq->intr_handle,
63 mlx5_vdpa_virtq_handler,
66 DRV_LOG(DEBUG, "Try again to unregister fd %d "
67 "of virtq %d interrupt, retries = %d.",
68 virtq->intr_handle.fd,
69 (int)virtq->index, retries);
70 usleep(MLX5_VDPA_INTR_RETRIES_USEC);
73 virtq->intr_handle.fd = -1;
76 ret = mlx5_vdpa_virtq_stop(virtq->priv, virtq->index);
78 DRV_LOG(WARNING, "Failed to stop virtq %d.",
80 claim_zero(mlx5_devx_cmd_destroy(virtq->virtq));
83 for (i = 0; i < RTE_DIM(virtq->umems); ++i) {
84 if (virtq->umems[i].obj)
85 claim_zero(mlx5_glue->devx_umem_dereg
86 (virtq->umems[i].obj));
87 if (virtq->umems[i].buf)
88 rte_free(virtq->umems[i].buf);
90 memset(&virtq->umems, 0, sizeof(virtq->umems));
92 mlx5_vdpa_event_qp_destroy(&virtq->eqp);
93 virtq->notifier_state = MLX5_VDPA_NOTIFIER_STATE_DISABLED;
98 mlx5_vdpa_virtqs_release(struct mlx5_vdpa_priv *priv)
101 struct mlx5_vdpa_virtq *virtq;
103 for (i = 0; i < priv->nr_virtqs; i++) {
104 virtq = &priv->virtqs[i];
105 mlx5_vdpa_virtq_unset(virtq);
106 if (virtq->counters) {
107 claim_zero(mlx5_devx_cmd_destroy(virtq->counters));
108 virtq->counters = NULL;
109 memset(&virtq->reset, 0, sizeof(virtq->reset));
111 memset(virtq->err_time, 0, sizeof(virtq->err_time));
114 for (i = 0; i < priv->num_lag_ports; i++) {
116 claim_zero(mlx5_devx_cmd_destroy(priv->tiss[i]));
117 priv->tiss[i] = NULL;
121 claim_zero(mlx5_devx_cmd_destroy(priv->td));
124 if (priv->virtq_db_addr) {
125 claim_zero(munmap(priv->virtq_db_addr, priv->var->length));
126 priv->virtq_db_addr = NULL;
133 mlx5_vdpa_virtq_modify(struct mlx5_vdpa_virtq *virtq, int state)
135 struct mlx5_devx_virtq_attr attr = {
136 .type = MLX5_VIRTQ_MODIFY_TYPE_STATE,
137 .state = state ? MLX5_VIRTQ_STATE_RDY :
138 MLX5_VIRTQ_STATE_SUSPEND,
139 .queue_index = virtq->index,
142 return mlx5_devx_cmd_modify_virtq(virtq->virtq, &attr);
146 mlx5_vdpa_virtq_stop(struct mlx5_vdpa_priv *priv, int index)
148 struct mlx5_vdpa_virtq *virtq = &priv->virtqs[index];
153 ret = mlx5_vdpa_virtq_modify(virtq, 0);
156 virtq->stopped = true;
157 DRV_LOG(DEBUG, "vid %u virtq %u was stopped.", priv->vid, index);
158 return mlx5_vdpa_virtq_query(priv, index);
162 mlx5_vdpa_virtq_query(struct mlx5_vdpa_priv *priv, int index)
164 struct mlx5_devx_virtq_attr attr = {0};
165 struct mlx5_vdpa_virtq *virtq = &priv->virtqs[index];
168 if (mlx5_devx_cmd_query_virtq(virtq->virtq, &attr)) {
169 DRV_LOG(ERR, "Failed to query virtq %d.", index);
172 DRV_LOG(INFO, "Query vid %d vring %d: hw_available_idx=%d, "
173 "hw_used_index=%d", priv->vid, index,
174 attr.hw_available_index, attr.hw_used_index);
175 ret = rte_vhost_set_vring_base(priv->vid, index,
176 attr.hw_available_index,
179 DRV_LOG(ERR, "Failed to set virtq %d base.", index);
182 if (attr.state == MLX5_VIRTQ_STATE_ERROR)
183 DRV_LOG(WARNING, "vid %d vring %d hw error=%hhu",
184 priv->vid, index, attr.error_type);
189 mlx5_vdpa_hva_to_gpa(struct rte_vhost_memory *mem, uint64_t hva)
191 struct rte_vhost_mem_region *reg;
195 for (i = 0; i < mem->nregions; i++) {
196 reg = &mem->regions[i];
197 if (hva >= reg->host_user_addr &&
198 hva < reg->host_user_addr + reg->size) {
199 gpa = hva - reg->host_user_addr + reg->guest_phys_addr;
207 mlx5_vdpa_virtq_setup(struct mlx5_vdpa_priv *priv, int index)
209 struct mlx5_vdpa_virtq *virtq = &priv->virtqs[index];
210 struct rte_vhost_vring vq;
211 struct mlx5_devx_virtq_attr attr = {0};
215 uint16_t last_avail_idx;
216 uint16_t last_used_idx;
217 uint16_t event_num = MLX5_EVENT_TYPE_OBJECT_CHANGE;
220 ret = rte_vhost_get_vhost_vring(priv->vid, index, &vq);
223 virtq->index = index;
224 virtq->vq_size = vq.size;
225 attr.tso_ipv4 = !!(priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO4));
226 attr.tso_ipv6 = !!(priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO6));
227 attr.tx_csum = !!(priv->features & (1ULL << VIRTIO_NET_F_CSUM));
228 attr.rx_csum = !!(priv->features & (1ULL << VIRTIO_NET_F_GUEST_CSUM));
229 attr.virtio_version_1_0 = !!(priv->features & (1ULL <<
230 VIRTIO_F_VERSION_1));
231 attr.type = (priv->features & (1ULL << VIRTIO_F_RING_PACKED)) ?
232 MLX5_VIRTQ_TYPE_PACKED : MLX5_VIRTQ_TYPE_SPLIT;
234 * No need event QPs creation when the guest in poll mode or when the
235 * capability allows it.
237 attr.event_mode = vq.callfd != -1 || !(priv->caps.event_mode & (1 <<
238 MLX5_VIRTQ_EVENT_MODE_NO_MSIX)) ?
239 MLX5_VIRTQ_EVENT_MODE_QP :
240 MLX5_VIRTQ_EVENT_MODE_NO_MSIX;
241 if (attr.event_mode == MLX5_VIRTQ_EVENT_MODE_QP) {
242 ret = mlx5_vdpa_event_qp_create(priv, vq.size, vq.callfd,
245 DRV_LOG(ERR, "Failed to create event QPs for virtq %d.",
249 attr.qp_id = virtq->eqp.fw_qp->id;
251 DRV_LOG(INFO, "Virtq %d is, for sure, working by poll mode, no"
252 " need event QPs and event mechanism.", index);
254 if (priv->caps.queue_counters_valid) {
255 if (!virtq->counters)
256 virtq->counters = mlx5_devx_cmd_create_virtio_q_counters
258 if (!virtq->counters) {
259 DRV_LOG(ERR, "Failed to create virtq couners for virtq"
263 attr.counters_obj_id = virtq->counters->id;
265 /* Setup 3 UMEMs for each virtq. */
266 for (i = 0; i < RTE_DIM(virtq->umems); ++i) {
267 virtq->umems[i].size = priv->caps.umems[i].a * vq.size +
268 priv->caps.umems[i].b;
269 virtq->umems[i].buf = rte_zmalloc(__func__,
270 virtq->umems[i].size, 4096);
271 if (!virtq->umems[i].buf) {
272 DRV_LOG(ERR, "Cannot allocate umem %d memory for virtq"
276 virtq->umems[i].obj = mlx5_glue->devx_umem_reg(priv->ctx,
278 virtq->umems[i].size,
279 IBV_ACCESS_LOCAL_WRITE);
280 if (!virtq->umems[i].obj) {
281 DRV_LOG(ERR, "Failed to register umem %d for virtq %u.",
285 attr.umems[i].id = virtq->umems[i].obj->umem_id;
286 attr.umems[i].offset = 0;
287 attr.umems[i].size = virtq->umems[i].size;
289 if (attr.type == MLX5_VIRTQ_TYPE_SPLIT) {
290 gpa = mlx5_vdpa_hva_to_gpa(priv->vmem,
291 (uint64_t)(uintptr_t)vq.desc);
293 DRV_LOG(ERR, "Failed to get descriptor ring GPA.");
296 attr.desc_addr = gpa;
297 gpa = mlx5_vdpa_hva_to_gpa(priv->vmem,
298 (uint64_t)(uintptr_t)vq.used);
300 DRV_LOG(ERR, "Failed to get GPA for used ring.");
303 attr.used_addr = gpa;
304 gpa = mlx5_vdpa_hva_to_gpa(priv->vmem,
305 (uint64_t)(uintptr_t)vq.avail);
307 DRV_LOG(ERR, "Failed to get GPA for available ring.");
310 attr.available_addr = gpa;
312 ret = rte_vhost_get_vring_base(priv->vid, index, &last_avail_idx,
317 DRV_LOG(WARNING, "Couldn't get vring base, idx are set to 0");
319 DRV_LOG(INFO, "vid %d: Init last_avail_idx=%d, last_used_idx=%d for "
320 "virtq %d.", priv->vid, last_avail_idx,
321 last_used_idx, index);
323 attr.hw_available_index = last_avail_idx;
324 attr.hw_used_index = last_used_idx;
325 attr.q_size = vq.size;
326 attr.mkey = priv->gpa_mkey_index;
327 attr.tis_id = priv->tiss[(index / 2) % priv->num_lag_ports]->id;
328 attr.queue_index = index;
330 attr.hw_latency_mode = priv->hw_latency_mode;
331 attr.hw_max_latency_us = priv->hw_max_latency_us;
332 attr.hw_max_pending_comp = priv->hw_max_pending_comp;
333 virtq->virtq = mlx5_devx_cmd_create_virtq(priv->ctx, &attr);
337 claim_zero(rte_vhost_enable_guest_notification(priv->vid, index, 1));
338 if (mlx5_vdpa_virtq_modify(virtq, 1))
341 rte_write32(virtq->index, priv->virtq_db_addr);
342 /* Setup doorbell mapping. */
343 virtq->intr_handle.fd = vq.kickfd;
344 if (virtq->intr_handle.fd == -1) {
345 DRV_LOG(WARNING, "Virtq %d kickfd is invalid.", index);
347 virtq->intr_handle.type = RTE_INTR_HANDLE_EXT;
348 if (rte_intr_callback_register(&virtq->intr_handle,
349 mlx5_vdpa_virtq_handler,
351 virtq->intr_handle.fd = -1;
352 DRV_LOG(ERR, "Failed to register virtq %d interrupt.",
356 DRV_LOG(DEBUG, "Register fd %d interrupt for virtq %d.",
357 virtq->intr_handle.fd, index);
360 /* Subscribe virtq error event. */
362 cookie = ((uint64_t)virtq->version << 32) + index;
363 ret = mlx5_glue->devx_subscribe_devx_event(priv->err_chnl,
368 DRV_LOG(ERR, "Failed to subscribe device %d virtq %d error event.",
373 virtq->stopped = false;
374 DRV_LOG(DEBUG, "vid %u virtq %u was created successfully.", priv->vid,
378 mlx5_vdpa_virtq_unset(virtq);
383 mlx5_vdpa_features_validate(struct mlx5_vdpa_priv *priv)
385 if (priv->features & (1ULL << VIRTIO_F_RING_PACKED)) {
386 if (!(priv->caps.virtio_queue_type & (1 <<
387 MLX5_VIRTQ_TYPE_PACKED))) {
388 DRV_LOG(ERR, "Failed to configur PACKED mode for vdev "
389 "%d - it was not reported by HW/driver"
390 " capability.", priv->vid);
394 if (priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO4)) {
395 if (!priv->caps.tso_ipv4) {
396 DRV_LOG(ERR, "Failed to enable TSO4 for vdev %d - TSO4"
397 " was not reported by HW/driver capability.",
402 if (priv->features & (1ULL << VIRTIO_NET_F_HOST_TSO6)) {
403 if (!priv->caps.tso_ipv6) {
404 DRV_LOG(ERR, "Failed to enable TSO6 for vdev %d - TSO6"
405 " was not reported by HW/driver capability.",
410 if (priv->features & (1ULL << VIRTIO_NET_F_CSUM)) {
411 if (!priv->caps.tx_csum) {
412 DRV_LOG(ERR, "Failed to enable CSUM for vdev %d - CSUM"
413 " was not reported by HW/driver capability.",
418 if (priv->features & (1ULL << VIRTIO_NET_F_GUEST_CSUM)) {
419 if (!priv->caps.rx_csum) {
420 DRV_LOG(ERR, "Failed to enable GUEST CSUM for vdev %d"
421 " GUEST CSUM was not reported by HW/driver "
422 "capability.", priv->vid);
426 if (priv->features & (1ULL << VIRTIO_F_VERSION_1)) {
427 if (!priv->caps.virtio_version_1_0) {
428 DRV_LOG(ERR, "Failed to enable version 1 for vdev %d "
429 "version 1 was not reported by HW/driver"
430 " capability.", priv->vid);
438 mlx5_vdpa_virtqs_prepare(struct mlx5_vdpa_priv *priv)
440 struct mlx5_devx_tis_attr tis_attr = {0};
442 uint16_t nr_vring = rte_vhost_get_vring_num(priv->vid);
443 int ret = rte_vhost_get_negotiated_features(priv->vid, &priv->features);
445 if (ret || mlx5_vdpa_features_validate(priv)) {
446 DRV_LOG(ERR, "Failed to configure negotiated features.");
449 if (nr_vring > priv->caps.max_num_virtio_queues * 2) {
450 DRV_LOG(ERR, "Do not support more than %d virtqs(%d).",
451 (int)priv->caps.max_num_virtio_queues * 2,
455 /* Always map the entire page. */
456 priv->virtq_db_addr = mmap(NULL, priv->var->length, PROT_READ |
457 PROT_WRITE, MAP_SHARED, priv->ctx->cmd_fd,
458 priv->var->mmap_off);
459 if (priv->virtq_db_addr == MAP_FAILED) {
460 DRV_LOG(ERR, "Failed to map doorbell page %u.", errno);
461 priv->virtq_db_addr = NULL;
464 DRV_LOG(DEBUG, "VAR address of doorbell mapping is %p.",
465 priv->virtq_db_addr);
467 priv->td = mlx5_devx_cmd_create_td(priv->ctx);
469 DRV_LOG(ERR, "Failed to create transport domain.");
472 tis_attr.transport_domain = priv->td->id;
473 for (i = 0; i < priv->num_lag_ports; i++) {
474 /* 0 is auto affinity, non-zero value to propose port. */
475 tis_attr.lag_tx_port_affinity = i + 1;
476 priv->tiss[i] = mlx5_devx_cmd_create_tis(priv->ctx, &tis_attr);
477 if (!priv->tiss[i]) {
478 DRV_LOG(ERR, "Failed to create TIS %u.", i);
482 priv->nr_virtqs = nr_vring;
483 for (i = 0; i < nr_vring; i++)
484 if (priv->virtqs[i].enable && mlx5_vdpa_virtq_setup(priv, i))
488 mlx5_vdpa_virtqs_release(priv);
493 mlx5_vdpa_virtq_is_modified(struct mlx5_vdpa_priv *priv,
494 struct mlx5_vdpa_virtq *virtq)
496 struct rte_vhost_vring vq;
497 int ret = rte_vhost_get_vhost_vring(priv->vid, virtq->index, &vq);
501 if (vq.size != virtq->vq_size || vq.kickfd != virtq->intr_handle.fd)
503 if (virtq->eqp.cq.cq) {
504 if (vq.callfd != virtq->eqp.cq.callfd)
506 } else if (vq.callfd != -1) {
513 mlx5_vdpa_virtq_enable(struct mlx5_vdpa_priv *priv, int index, int enable)
515 struct mlx5_vdpa_virtq *virtq = &priv->virtqs[index];
518 DRV_LOG(INFO, "Update virtq %d status %sable -> %sable.", index,
519 virtq->enable ? "en" : "dis", enable ? "en" : "dis");
520 if (!priv->configured) {
521 virtq->enable = !!enable;
524 if (virtq->enable == !!enable) {
527 ret = mlx5_vdpa_virtq_is_modified(priv, virtq);
529 DRV_LOG(ERR, "Virtq %d modify check failed.", index);
534 DRV_LOG(INFO, "Virtq %d was modified, recreate it.", index);
538 if (is_virtq_recvq(virtq->index, priv->nr_virtqs)) {
539 ret = mlx5_vdpa_steer_update(priv);
541 DRV_LOG(WARNING, "Failed to disable steering "
542 "for virtq %d.", index);
544 mlx5_vdpa_virtq_unset(virtq);
547 ret = mlx5_vdpa_virtq_setup(priv, index);
549 DRV_LOG(ERR, "Failed to setup virtq %d.", index);
553 if (is_virtq_recvq(virtq->index, priv->nr_virtqs)) {
554 ret = mlx5_vdpa_steer_update(priv);
556 DRV_LOG(WARNING, "Failed to enable steering "
557 "for virtq %d.", index);
564 mlx5_vdpa_virtq_stats_get(struct mlx5_vdpa_priv *priv, int qid,
565 struct rte_vdpa_stat *stats, unsigned int n)
567 struct mlx5_vdpa_virtq *virtq = &priv->virtqs[qid];
568 struct mlx5_devx_virtio_q_couners_attr attr = {0};
571 if (!virtq->counters) {
572 DRV_LOG(ERR, "Failed to read virtq %d statistics - virtq "
576 ret = mlx5_devx_cmd_query_virtio_q_counters(virtq->counters, &attr);
578 DRV_LOG(ERR, "Failed to read virtq %d stats from HW.", qid);
581 ret = (int)RTE_MIN(n, (unsigned int)MLX5_VDPA_STATS_MAX);
582 if (ret == MLX5_VDPA_STATS_RECEIVED_DESCRIPTORS)
584 stats[MLX5_VDPA_STATS_RECEIVED_DESCRIPTORS] = (struct rte_vdpa_stat) {
585 .id = MLX5_VDPA_STATS_RECEIVED_DESCRIPTORS,
586 .value = attr.received_desc - virtq->reset.received_desc,
588 if (ret == MLX5_VDPA_STATS_COMPLETED_DESCRIPTORS)
590 stats[MLX5_VDPA_STATS_COMPLETED_DESCRIPTORS] = (struct rte_vdpa_stat) {
591 .id = MLX5_VDPA_STATS_COMPLETED_DESCRIPTORS,
592 .value = attr.completed_desc - virtq->reset.completed_desc,
594 if (ret == MLX5_VDPA_STATS_BAD_DESCRIPTOR_ERRORS)
596 stats[MLX5_VDPA_STATS_BAD_DESCRIPTOR_ERRORS] = (struct rte_vdpa_stat) {
597 .id = MLX5_VDPA_STATS_BAD_DESCRIPTOR_ERRORS,
598 .value = attr.bad_desc_errors - virtq->reset.bad_desc_errors,
600 if (ret == MLX5_VDPA_STATS_EXCEED_MAX_CHAIN)
602 stats[MLX5_VDPA_STATS_EXCEED_MAX_CHAIN] = (struct rte_vdpa_stat) {
603 .id = MLX5_VDPA_STATS_EXCEED_MAX_CHAIN,
604 .value = attr.exceed_max_chain - virtq->reset.exceed_max_chain,
606 if (ret == MLX5_VDPA_STATS_INVALID_BUFFER)
608 stats[MLX5_VDPA_STATS_INVALID_BUFFER] = (struct rte_vdpa_stat) {
609 .id = MLX5_VDPA_STATS_INVALID_BUFFER,
610 .value = attr.invalid_buffer - virtq->reset.invalid_buffer,
612 if (ret == MLX5_VDPA_STATS_COMPLETION_ERRORS)
614 stats[MLX5_VDPA_STATS_COMPLETION_ERRORS] = (struct rte_vdpa_stat) {
615 .id = MLX5_VDPA_STATS_COMPLETION_ERRORS,
616 .value = attr.error_cqes - virtq->reset.error_cqes,
622 mlx5_vdpa_virtq_stats_reset(struct mlx5_vdpa_priv *priv, int qid)
624 struct mlx5_vdpa_virtq *virtq = &priv->virtqs[qid];
627 if (!virtq->counters) {
628 DRV_LOG(ERR, "Failed to read virtq %d statistics - virtq "
632 ret = mlx5_devx_cmd_query_virtio_q_counters(virtq->counters,
635 DRV_LOG(ERR, "Failed to read virtq %d reset stats from HW.",