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32 ***************************************************************************/
35 * 82540EM Gigabit Ethernet Controller
36 * 82540EP Gigabit Ethernet Controller
37 * 82545EM Gigabit Ethernet Controller (Copper)
38 * 82545EM Gigabit Ethernet Controller (Fiber)
39 * 82545GM Gigabit Ethernet Controller
40 * 82546EB Gigabit Ethernet Controller (Copper)
41 * 82546EB Gigabit Ethernet Controller (Fiber)
42 * 82546GB Gigabit Ethernet Controller
45 #include "e1000_api.h"
47 STATIC s32 e1000_init_phy_params_82540(struct e1000_hw *hw);
48 STATIC s32 e1000_init_nvm_params_82540(struct e1000_hw *hw);
49 STATIC s32 e1000_init_mac_params_82540(struct e1000_hw *hw);
50 STATIC s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
51 STATIC void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);
52 STATIC s32 e1000_init_hw_82540(struct e1000_hw *hw);
53 STATIC s32 e1000_reset_hw_82540(struct e1000_hw *hw);
54 STATIC s32 e1000_set_phy_mode_82540(struct e1000_hw *hw);
55 STATIC s32 e1000_set_vco_speed_82540(struct e1000_hw *hw);
56 STATIC s32 e1000_setup_copper_link_82540(struct e1000_hw *hw);
57 STATIC s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
58 STATIC void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
59 STATIC s32 e1000_read_mac_addr_82540(struct e1000_hw *hw);
62 * e1000_init_phy_params_82540 - Init PHY func ptrs.
63 * @hw: pointer to the HW structure
65 STATIC s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
67 struct e1000_phy_info *phy = &hw->phy;
71 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
72 phy->reset_delay_us = 10000;
73 phy->type = e1000_phy_m88;
75 /* Function Pointers */
76 phy->ops.check_polarity = e1000_check_polarity_m88;
77 phy->ops.commit = e1000_phy_sw_reset_generic;
78 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
79 phy->ops.get_cable_length = e1000_get_cable_length_m88;
80 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
81 phy->ops.read_reg = e1000_read_phy_reg_m88;
82 phy->ops.reset = e1000_phy_hw_reset_generic;
83 phy->ops.write_reg = e1000_write_phy_reg_m88;
84 phy->ops.get_info = e1000_get_phy_info_m88;
85 phy->ops.power_up = e1000_power_up_phy_copper;
86 phy->ops.power_down = e1000_power_down_phy_copper_82540;
88 ret_val = e1000_get_phy_id(hw);
93 switch (hw->mac.type) {
96 case e1000_82545_rev_3:
98 case e1000_82546_rev_3:
99 if (phy->id == M88E1011_I_PHY_ID)
103 ret_val = -E1000_ERR_PHY;
113 * e1000_init_nvm_params_82540 - Init NVM func ptrs.
114 * @hw: pointer to the HW structure
116 STATIC s32 e1000_init_nvm_params_82540(struct e1000_hw *hw)
118 struct e1000_nvm_info *nvm = &hw->nvm;
119 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
121 DEBUGFUNC("e1000_init_nvm_params_82540");
123 nvm->type = e1000_nvm_eeprom_microwire;
124 nvm->delay_usec = 50;
125 nvm->opcode_bits = 3;
126 switch (nvm->override) {
127 case e1000_nvm_override_microwire_large:
128 nvm->address_bits = 8;
129 nvm->word_size = 256;
131 case e1000_nvm_override_microwire_small:
132 nvm->address_bits = 6;
136 nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6;
137 nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64;
141 /* Function Pointers */
142 nvm->ops.acquire = e1000_acquire_nvm_generic;
143 nvm->ops.read = e1000_read_nvm_microwire;
144 nvm->ops.release = e1000_release_nvm_generic;
145 nvm->ops.update = e1000_update_nvm_checksum_generic;
146 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
147 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
148 nvm->ops.write = e1000_write_nvm_microwire;
150 return E1000_SUCCESS;
154 * e1000_init_mac_params_82540 - Init MAC func ptrs.
155 * @hw: pointer to the HW structure
157 STATIC s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
159 struct e1000_mac_info *mac = &hw->mac;
160 s32 ret_val = E1000_SUCCESS;
162 DEBUGFUNC("e1000_init_mac_params_82540");
165 switch (hw->device_id) {
166 case E1000_DEV_ID_82545EM_FIBER:
167 case E1000_DEV_ID_82545GM_FIBER:
168 case E1000_DEV_ID_82546EB_FIBER:
169 case E1000_DEV_ID_82546GB_FIBER:
170 hw->phy.media_type = e1000_media_type_fiber;
172 case E1000_DEV_ID_82545GM_SERDES:
173 case E1000_DEV_ID_82546GB_SERDES:
174 hw->phy.media_type = e1000_media_type_internal_serdes;
177 hw->phy.media_type = e1000_media_type_copper;
181 /* Set mta register count */
182 mac->mta_reg_count = 128;
183 /* Set rar entry count */
184 mac->rar_entry_count = E1000_RAR_ENTRIES;
186 /* Function pointers */
188 /* bus type/speed/width */
189 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
191 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
193 mac->ops.reset_hw = e1000_reset_hw_82540;
194 /* hw initialization */
195 mac->ops.init_hw = e1000_init_hw_82540;
197 mac->ops.setup_link = e1000_setup_link_generic;
198 /* physical interface setup */
199 mac->ops.setup_physical_interface =
200 (hw->phy.media_type == e1000_media_type_copper)
201 ? e1000_setup_copper_link_82540
202 : e1000_setup_fiber_serdes_link_82540;
204 switch (hw->phy.media_type) {
205 case e1000_media_type_copper:
206 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
208 case e1000_media_type_fiber:
209 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
211 case e1000_media_type_internal_serdes:
212 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
215 ret_val = -E1000_ERR_CONFIG;
220 mac->ops.get_link_up_info =
221 (hw->phy.media_type == e1000_media_type_copper)
222 ? e1000_get_speed_and_duplex_copper_generic
223 : e1000_get_speed_and_duplex_fiber_serdes_generic;
224 /* multicast address update */
225 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
227 mac->ops.write_vfta = e1000_write_vfta_generic;
229 mac->ops.clear_vfta = e1000_clear_vfta_generic;
230 /* read mac address */
231 mac->ops.read_mac_addr = e1000_read_mac_addr_82540;
233 mac->ops.id_led_init = e1000_id_led_init_generic;
235 mac->ops.setup_led = e1000_setup_led_generic;
237 mac->ops.cleanup_led = e1000_cleanup_led_generic;
238 /* turn on/off LED */
239 mac->ops.led_on = e1000_led_on_generic;
240 mac->ops.led_off = e1000_led_off_generic;
241 /* clear hardware counters */
242 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540;
249 * e1000_init_function_pointers_82540 - Init func ptrs.
250 * @hw: pointer to the HW structure
252 * Called to initialize all function pointers and parameters.
254 void e1000_init_function_pointers_82540(struct e1000_hw *hw)
256 DEBUGFUNC("e1000_init_function_pointers_82540");
258 hw->mac.ops.init_params = e1000_init_mac_params_82540;
259 hw->nvm.ops.init_params = e1000_init_nvm_params_82540;
260 hw->phy.ops.init_params = e1000_init_phy_params_82540;
264 * e1000_reset_hw_82540 - Reset hardware
265 * @hw: pointer to the HW structure
267 * This resets the hardware into a known state.
269 STATIC s32 e1000_reset_hw_82540(struct e1000_hw *hw)
272 s32 ret_val = E1000_SUCCESS;
274 DEBUGFUNC("e1000_reset_hw_82540");
276 DEBUGOUT("Masking off all interrupts\n");
277 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
279 E1000_WRITE_REG(hw, E1000_RCTL, 0);
280 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
281 E1000_WRITE_FLUSH(hw);
284 * Delay to allow any outstanding PCI transactions to complete
285 * before resetting the device.
289 ctrl = E1000_READ_REG(hw, E1000_CTRL);
291 DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n");
292 switch (hw->mac.type) {
293 case e1000_82545_rev_3:
294 case e1000_82546_rev_3:
295 E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);
299 * These controllers can't ack the 64-bit write when
300 * issuing the reset, so we use IO-mapping as a
301 * workaround to issue the reset.
303 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
307 /* Wait for EEPROM reload */
310 /* Disable HW ARPs on ASF enabled adapters */
311 manc = E1000_READ_REG(hw, E1000_MANC);
312 manc &= ~E1000_MANC_ARP_EN;
313 E1000_WRITE_REG(hw, E1000_MANC, manc);
315 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
316 E1000_READ_REG(hw, E1000_ICR);
322 * e1000_init_hw_82540 - Initialize hardware
323 * @hw: pointer to the HW structure
325 * This inits the hardware readying it for operation.
327 STATIC s32 e1000_init_hw_82540(struct e1000_hw *hw)
329 struct e1000_mac_info *mac = &hw->mac;
330 u32 txdctl, ctrl_ext;
334 DEBUGFUNC("e1000_init_hw_82540");
336 /* Initialize identification LED */
337 ret_val = mac->ops.id_led_init(hw);
339 DEBUGOUT("Error initializing identification LED\n");
340 /* This is not fatal and we should not stop init due to this */
343 /* Disabling VLAN filtering */
344 DEBUGOUT("Initializing the IEEE VLAN\n");
345 if (mac->type < e1000_82545_rev_3)
346 E1000_WRITE_REG(hw, E1000_VET, 0);
348 mac->ops.clear_vfta(hw);
350 /* Setup the receive address. */
351 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
353 /* Zero out the Multicast HASH table */
354 DEBUGOUT("Zeroing the MTA\n");
355 for (i = 0; i < mac->mta_reg_count; i++) {
356 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
358 * Avoid back to back register writes by adding the register
359 * read (flush). This is to protect against some strange
360 * bridge configurations that may issue Memory Write Block
361 * (MWB) to our register space. The *_rev_3 hardware at
362 * least doesn't respond correctly to every other dword in an
363 * MWB to our register space.
365 E1000_WRITE_FLUSH(hw);
368 if (mac->type < e1000_82545_rev_3)
369 e1000_pcix_mmrbc_workaround_generic(hw);
371 /* Setup link and flow control */
372 ret_val = mac->ops.setup_link(hw);
374 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
375 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
376 E1000_TXDCTL_FULL_TX_DESC_WB;
377 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
380 * Clear all of the statistics registers (clear on read). It is
381 * important that we do this after we have tried to establish link
382 * because the symbol error count will increment wildly if there
385 e1000_clear_hw_cntrs_82540(hw);
387 if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||
388 (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {
389 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
391 * Relaxed ordering must be disabled to avoid a parity
392 * error crash in a PCI slot.
394 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
395 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
402 * e1000_setup_copper_link_82540 - Configure copper link settings
403 * @hw: pointer to the HW structure
405 * Calls the appropriate function to configure the link for auto-neg or forced
406 * speed and duplex. Then we check for link, once link is established calls
407 * to configure collision distance and flow control are called. If link is
408 * not established, we return -E1000_ERR_PHY (-2).
410 STATIC s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
416 DEBUGFUNC("e1000_setup_copper_link_82540");
418 ctrl = E1000_READ_REG(hw, E1000_CTRL);
419 ctrl |= E1000_CTRL_SLU;
420 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
421 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
423 ret_val = e1000_set_phy_mode_82540(hw);
427 if (hw->mac.type == e1000_82545_rev_3 ||
428 hw->mac.type == e1000_82546_rev_3) {
429 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
434 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
440 ret_val = e1000_copper_link_setup_m88(hw);
444 ret_val = e1000_setup_copper_link_generic(hw);
451 * e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes
452 * @hw: pointer to the HW structure
454 * Set the output amplitude to the value in the EEPROM and adjust the VCO
455 * speed to improve Bit Error Rate (BER) performance. Configures collision
456 * distance and flow control for fiber and serdes links. Upon successful
457 * setup, poll for link.
459 STATIC s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)
461 struct e1000_mac_info *mac = &hw->mac;
462 s32 ret_val = E1000_SUCCESS;
464 DEBUGFUNC("e1000_setup_fiber_serdes_link_82540");
467 case e1000_82545_rev_3:
468 case e1000_82546_rev_3:
469 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
471 * If we're on serdes media, adjust the output
472 * amplitude to value set in the EEPROM.
474 ret_val = e1000_adjust_serdes_amplitude_82540(hw);
478 /* Adjust VCO speed to improve BER performance */
479 ret_val = e1000_set_vco_speed_82540(hw);
486 ret_val = e1000_setup_fiber_serdes_link_generic(hw);
493 * e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM
494 * @hw: pointer to the HW structure
496 * Adjust the SERDES output amplitude based on the EEPROM settings.
498 STATIC s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
503 DEBUGFUNC("e1000_adjust_serdes_amplitude_82540");
505 ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data);
509 if (nvm_data != NVM_RESERVED_WORD) {
510 /* Adjust serdes output amplitude only. */
511 nvm_data &= NVM_SERDES_AMPLITUDE_MASK;
512 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL,
523 * e1000_set_vco_speed_82540 - Set VCO speed for better performance
524 * @hw: pointer to the HW structure
526 * Set the VCO speed to improve Bit Error Rate (BER) performance.
528 STATIC s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
531 u16 default_page = 0;
534 DEBUGFUNC("e1000_set_vco_speed_82540");
536 /* Set PHY register 30, page 5, bit 8 to 0 */
538 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_PAGE_SELECT,
543 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
547 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
551 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
552 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
556 /* Set PHY register 30, page 4, bit 11 to 1 */
558 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
562 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
566 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
567 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
571 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
579 * e1000_set_phy_mode_82540 - Set PHY to class A mode
580 * @hw: pointer to the HW structure
582 * Sets the PHY to class A mode and assumes the following operations will
583 * follow to enable the new class mode:
584 * 1. Do a PHY soft reset.
585 * 2. Restart auto-negotiation or force link.
587 STATIC s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
589 s32 ret_val = E1000_SUCCESS;
592 DEBUGFUNC("e1000_set_phy_mode_82540");
594 if (hw->mac.type != e1000_82545_rev_3)
597 ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data);
599 ret_val = -E1000_ERR_PHY;
603 if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) {
604 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
607 ret_val = -E1000_ERR_PHY;
610 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL,
613 ret_val = -E1000_ERR_PHY;
624 * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down
625 * @hw: pointer to the HW structure
627 * In the case of a PHY power down to save power, or to turn off link during a
628 * driver unload, or wake on lan is not enabled, remove the link.
630 STATIC void e1000_power_down_phy_copper_82540(struct e1000_hw *hw)
632 /* If the management interface is not enabled, then power down */
633 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
634 e1000_power_down_phy_copper(hw);
640 * e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters
641 * @hw: pointer to the HW structure
643 * Clears the hardware counters by reading the counter registers.
645 STATIC void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)
647 DEBUGFUNC("e1000_clear_hw_cntrs_82540");
649 e1000_clear_hw_cntrs_base_generic(hw);
651 E1000_READ_REG(hw, E1000_PRC64);
652 E1000_READ_REG(hw, E1000_PRC127);
653 E1000_READ_REG(hw, E1000_PRC255);
654 E1000_READ_REG(hw, E1000_PRC511);
655 E1000_READ_REG(hw, E1000_PRC1023);
656 E1000_READ_REG(hw, E1000_PRC1522);
657 E1000_READ_REG(hw, E1000_PTC64);
658 E1000_READ_REG(hw, E1000_PTC127);
659 E1000_READ_REG(hw, E1000_PTC255);
660 E1000_READ_REG(hw, E1000_PTC511);
661 E1000_READ_REG(hw, E1000_PTC1023);
662 E1000_READ_REG(hw, E1000_PTC1522);
664 E1000_READ_REG(hw, E1000_ALGNERRC);
665 E1000_READ_REG(hw, E1000_RXERRC);
666 E1000_READ_REG(hw, E1000_TNCRS);
667 E1000_READ_REG(hw, E1000_CEXTERR);
668 E1000_READ_REG(hw, E1000_TSCTC);
669 E1000_READ_REG(hw, E1000_TSCTFC);
671 E1000_READ_REG(hw, E1000_MGTPRC);
672 E1000_READ_REG(hw, E1000_MGTPDC);
673 E1000_READ_REG(hw, E1000_MGTPTC);
677 * e1000_read_mac_addr_82540 - Read device MAC address
678 * @hw: pointer to the HW structure
680 * Reads the device MAC address from the EEPROM and stores the value.
681 * Since devices with two ports use the same EEPROM, we increment the
682 * last bit in the MAC address for the second port.
684 * This version is being used over generic because of customer issues
685 * with VmWare and Virtual Box when using generic. It seems in
686 * the emulated 82545, RAR[0] does NOT have a valid address after a
687 * reset, this older method works and using this breaks nothing for
688 * these legacy adapters.
690 s32 e1000_read_mac_addr_82540(struct e1000_hw *hw)
692 s32 ret_val = E1000_SUCCESS;
693 u16 offset, nvm_data, i;
695 DEBUGFUNC("e1000_read_mac_addr");
697 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
699 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
701 DEBUGOUT("NVM Read Error\n");
704 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
705 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
708 /* Flip last bit of mac address if we're on second port */
709 if (hw->bus.func == E1000_FUNC_1)
710 hw->mac.perm_addr[5] ^= 1;
712 for (i = 0; i < ETH_ADDR_LEN; i++)
713 hw->mac.addr[i] = hw->mac.perm_addr[i];