1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001 - 2015 Intel Corporation
6 * 82540EM Gigabit Ethernet Controller
7 * 82540EP Gigabit Ethernet Controller
8 * 82545EM Gigabit Ethernet Controller (Copper)
9 * 82545EM Gigabit Ethernet Controller (Fiber)
10 * 82545GM Gigabit Ethernet Controller
11 * 82546EB Gigabit Ethernet Controller (Copper)
12 * 82546EB Gigabit Ethernet Controller (Fiber)
13 * 82546GB Gigabit Ethernet Controller
16 #include "e1000_api.h"
18 STATIC s32 e1000_init_phy_params_82540(struct e1000_hw *hw);
19 STATIC s32 e1000_init_nvm_params_82540(struct e1000_hw *hw);
20 STATIC s32 e1000_init_mac_params_82540(struct e1000_hw *hw);
21 STATIC s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
22 STATIC void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);
23 STATIC s32 e1000_init_hw_82540(struct e1000_hw *hw);
24 STATIC s32 e1000_reset_hw_82540(struct e1000_hw *hw);
25 STATIC s32 e1000_set_phy_mode_82540(struct e1000_hw *hw);
26 STATIC s32 e1000_set_vco_speed_82540(struct e1000_hw *hw);
27 STATIC s32 e1000_setup_copper_link_82540(struct e1000_hw *hw);
28 STATIC s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
29 STATIC void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
30 STATIC s32 e1000_read_mac_addr_82540(struct e1000_hw *hw);
33 * e1000_init_phy_params_82540 - Init PHY func ptrs.
34 * @hw: pointer to the HW structure
36 STATIC s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
38 struct e1000_phy_info *phy = &hw->phy;
42 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
43 phy->reset_delay_us = 10000;
44 phy->type = e1000_phy_m88;
46 /* Function Pointers */
47 phy->ops.check_polarity = e1000_check_polarity_m88;
48 phy->ops.commit = e1000_phy_sw_reset_generic;
49 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
50 phy->ops.get_cable_length = e1000_get_cable_length_m88;
51 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
52 phy->ops.read_reg = e1000_read_phy_reg_m88;
53 phy->ops.reset = e1000_phy_hw_reset_generic;
54 phy->ops.write_reg = e1000_write_phy_reg_m88;
55 phy->ops.get_info = e1000_get_phy_info_m88;
56 phy->ops.power_up = e1000_power_up_phy_copper;
57 phy->ops.power_down = e1000_power_down_phy_copper_82540;
59 ret_val = e1000_get_phy_id(hw);
64 switch (hw->mac.type) {
67 case e1000_82545_rev_3:
69 case e1000_82546_rev_3:
70 if (phy->id == M88E1011_I_PHY_ID)
74 ret_val = -E1000_ERR_PHY;
84 * e1000_init_nvm_params_82540 - Init NVM func ptrs.
85 * @hw: pointer to the HW structure
87 STATIC s32 e1000_init_nvm_params_82540(struct e1000_hw *hw)
89 struct e1000_nvm_info *nvm = &hw->nvm;
90 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
92 DEBUGFUNC("e1000_init_nvm_params_82540");
94 nvm->type = e1000_nvm_eeprom_microwire;
97 switch (nvm->override) {
98 case e1000_nvm_override_microwire_large:
99 nvm->address_bits = 8;
100 nvm->word_size = 256;
102 case e1000_nvm_override_microwire_small:
103 nvm->address_bits = 6;
107 nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6;
108 nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64;
112 /* Function Pointers */
113 nvm->ops.acquire = e1000_acquire_nvm_generic;
114 nvm->ops.read = e1000_read_nvm_microwire;
115 nvm->ops.release = e1000_release_nvm_generic;
116 nvm->ops.update = e1000_update_nvm_checksum_generic;
117 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
118 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
119 nvm->ops.write = e1000_write_nvm_microwire;
121 return E1000_SUCCESS;
125 * e1000_init_mac_params_82540 - Init MAC func ptrs.
126 * @hw: pointer to the HW structure
128 STATIC s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
130 struct e1000_mac_info *mac = &hw->mac;
131 s32 ret_val = E1000_SUCCESS;
133 DEBUGFUNC("e1000_init_mac_params_82540");
136 switch (hw->device_id) {
137 case E1000_DEV_ID_82545EM_FIBER:
138 case E1000_DEV_ID_82545GM_FIBER:
139 case E1000_DEV_ID_82546EB_FIBER:
140 case E1000_DEV_ID_82546GB_FIBER:
141 hw->phy.media_type = e1000_media_type_fiber;
143 case E1000_DEV_ID_82545GM_SERDES:
144 case E1000_DEV_ID_82546GB_SERDES:
145 hw->phy.media_type = e1000_media_type_internal_serdes;
148 hw->phy.media_type = e1000_media_type_copper;
152 /* Set mta register count */
153 mac->mta_reg_count = 128;
154 /* Set rar entry count */
155 mac->rar_entry_count = E1000_RAR_ENTRIES;
157 /* Function pointers */
159 /* bus type/speed/width */
160 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
162 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
164 mac->ops.reset_hw = e1000_reset_hw_82540;
165 /* hw initialization */
166 mac->ops.init_hw = e1000_init_hw_82540;
168 mac->ops.setup_link = e1000_setup_link_generic;
169 /* physical interface setup */
170 mac->ops.setup_physical_interface =
171 (hw->phy.media_type == e1000_media_type_copper)
172 ? e1000_setup_copper_link_82540
173 : e1000_setup_fiber_serdes_link_82540;
175 switch (hw->phy.media_type) {
176 case e1000_media_type_copper:
177 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
179 case e1000_media_type_fiber:
180 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
182 case e1000_media_type_internal_serdes:
183 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
186 ret_val = -E1000_ERR_CONFIG;
191 mac->ops.get_link_up_info =
192 (hw->phy.media_type == e1000_media_type_copper)
193 ? e1000_get_speed_and_duplex_copper_generic
194 : e1000_get_speed_and_duplex_fiber_serdes_generic;
195 /* multicast address update */
196 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
198 mac->ops.write_vfta = e1000_write_vfta_generic;
200 mac->ops.clear_vfta = e1000_clear_vfta_generic;
201 /* read mac address */
202 mac->ops.read_mac_addr = e1000_read_mac_addr_82540;
204 mac->ops.id_led_init = e1000_id_led_init_generic;
206 mac->ops.setup_led = e1000_setup_led_generic;
208 mac->ops.cleanup_led = e1000_cleanup_led_generic;
209 /* turn on/off LED */
210 mac->ops.led_on = e1000_led_on_generic;
211 mac->ops.led_off = e1000_led_off_generic;
212 /* clear hardware counters */
213 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540;
220 * e1000_init_function_pointers_82540 - Init func ptrs.
221 * @hw: pointer to the HW structure
223 * Called to initialize all function pointers and parameters.
225 void e1000_init_function_pointers_82540(struct e1000_hw *hw)
227 DEBUGFUNC("e1000_init_function_pointers_82540");
229 hw->mac.ops.init_params = e1000_init_mac_params_82540;
230 hw->nvm.ops.init_params = e1000_init_nvm_params_82540;
231 hw->phy.ops.init_params = e1000_init_phy_params_82540;
235 * e1000_reset_hw_82540 - Reset hardware
236 * @hw: pointer to the HW structure
238 * This resets the hardware into a known state.
240 STATIC s32 e1000_reset_hw_82540(struct e1000_hw *hw)
243 s32 ret_val = E1000_SUCCESS;
245 DEBUGFUNC("e1000_reset_hw_82540");
247 DEBUGOUT("Masking off all interrupts\n");
248 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
250 E1000_WRITE_REG(hw, E1000_RCTL, 0);
251 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
252 E1000_WRITE_FLUSH(hw);
255 * Delay to allow any outstanding PCI transactions to complete
256 * before resetting the device.
260 ctrl = E1000_READ_REG(hw, E1000_CTRL);
262 DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n");
263 switch (hw->mac.type) {
264 case e1000_82545_rev_3:
265 case e1000_82546_rev_3:
266 E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);
270 * These controllers can't ack the 64-bit write when
271 * issuing the reset, so we use IO-mapping as a
272 * workaround to issue the reset.
274 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
278 /* Wait for EEPROM reload */
281 /* Disable HW ARPs on ASF enabled adapters */
282 manc = E1000_READ_REG(hw, E1000_MANC);
283 manc &= ~E1000_MANC_ARP_EN;
284 E1000_WRITE_REG(hw, E1000_MANC, manc);
286 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
287 E1000_READ_REG(hw, E1000_ICR);
293 * e1000_init_hw_82540 - Initialize hardware
294 * @hw: pointer to the HW structure
296 * This inits the hardware readying it for operation.
298 STATIC s32 e1000_init_hw_82540(struct e1000_hw *hw)
300 struct e1000_mac_info *mac = &hw->mac;
301 u32 txdctl, ctrl_ext;
305 DEBUGFUNC("e1000_init_hw_82540");
307 /* Initialize identification LED */
308 ret_val = mac->ops.id_led_init(hw);
310 DEBUGOUT("Error initializing identification LED\n");
311 /* This is not fatal and we should not stop init due to this */
314 /* Disabling VLAN filtering */
315 DEBUGOUT("Initializing the IEEE VLAN\n");
316 if (mac->type < e1000_82545_rev_3)
317 E1000_WRITE_REG(hw, E1000_VET, 0);
319 mac->ops.clear_vfta(hw);
321 /* Setup the receive address. */
322 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
324 /* Zero out the Multicast HASH table */
325 DEBUGOUT("Zeroing the MTA\n");
326 for (i = 0; i < mac->mta_reg_count; i++) {
327 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
329 * Avoid back to back register writes by adding the register
330 * read (flush). This is to protect against some strange
331 * bridge configurations that may issue Memory Write Block
332 * (MWB) to our register space. The *_rev_3 hardware at
333 * least doesn't respond correctly to every other dword in an
334 * MWB to our register space.
336 E1000_WRITE_FLUSH(hw);
339 if (mac->type < e1000_82545_rev_3)
340 e1000_pcix_mmrbc_workaround_generic(hw);
342 /* Setup link and flow control */
343 ret_val = mac->ops.setup_link(hw);
345 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
346 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
347 E1000_TXDCTL_FULL_TX_DESC_WB;
348 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
351 * Clear all of the statistics registers (clear on read). It is
352 * important that we do this after we have tried to establish link
353 * because the symbol error count will increment wildly if there
356 e1000_clear_hw_cntrs_82540(hw);
358 if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||
359 (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {
360 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
362 * Relaxed ordering must be disabled to avoid a parity
363 * error crash in a PCI slot.
365 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
366 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
373 * e1000_setup_copper_link_82540 - Configure copper link settings
374 * @hw: pointer to the HW structure
376 * Calls the appropriate function to configure the link for auto-neg or forced
377 * speed and duplex. Then we check for link, once link is established calls
378 * to configure collision distance and flow control are called. If link is
379 * not established, we return -E1000_ERR_PHY (-2).
381 STATIC s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
387 DEBUGFUNC("e1000_setup_copper_link_82540");
389 ctrl = E1000_READ_REG(hw, E1000_CTRL);
390 ctrl |= E1000_CTRL_SLU;
391 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
392 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
394 ret_val = e1000_set_phy_mode_82540(hw);
398 if (hw->mac.type == e1000_82545_rev_3 ||
399 hw->mac.type == e1000_82546_rev_3) {
400 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
405 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
411 ret_val = e1000_copper_link_setup_m88(hw);
415 ret_val = e1000_setup_copper_link_generic(hw);
422 * e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes
423 * @hw: pointer to the HW structure
425 * Set the output amplitude to the value in the EEPROM and adjust the VCO
426 * speed to improve Bit Error Rate (BER) performance. Configures collision
427 * distance and flow control for fiber and serdes links. Upon successful
428 * setup, poll for link.
430 STATIC s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)
432 struct e1000_mac_info *mac = &hw->mac;
433 s32 ret_val = E1000_SUCCESS;
435 DEBUGFUNC("e1000_setup_fiber_serdes_link_82540");
438 case e1000_82545_rev_3:
439 case e1000_82546_rev_3:
440 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
442 * If we're on serdes media, adjust the output
443 * amplitude to value set in the EEPROM.
445 ret_val = e1000_adjust_serdes_amplitude_82540(hw);
449 /* Adjust VCO speed to improve BER performance */
450 ret_val = e1000_set_vco_speed_82540(hw);
457 ret_val = e1000_setup_fiber_serdes_link_generic(hw);
464 * e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM
465 * @hw: pointer to the HW structure
467 * Adjust the SERDES output amplitude based on the EEPROM settings.
469 STATIC s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
474 DEBUGFUNC("e1000_adjust_serdes_amplitude_82540");
476 ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data);
480 if (nvm_data != NVM_RESERVED_WORD) {
481 /* Adjust serdes output amplitude only. */
482 nvm_data &= NVM_SERDES_AMPLITUDE_MASK;
483 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL,
494 * e1000_set_vco_speed_82540 - Set VCO speed for better performance
495 * @hw: pointer to the HW structure
497 * Set the VCO speed to improve Bit Error Rate (BER) performance.
499 STATIC s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
502 u16 default_page = 0;
505 DEBUGFUNC("e1000_set_vco_speed_82540");
507 /* Set PHY register 30, page 5, bit 8 to 0 */
509 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_PAGE_SELECT,
514 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
518 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
522 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
523 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
527 /* Set PHY register 30, page 4, bit 11 to 1 */
529 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
533 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
537 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
538 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
542 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
550 * e1000_set_phy_mode_82540 - Set PHY to class A mode
551 * @hw: pointer to the HW structure
553 * Sets the PHY to class A mode and assumes the following operations will
554 * follow to enable the new class mode:
555 * 1. Do a PHY soft reset.
556 * 2. Restart auto-negotiation or force link.
558 STATIC s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
560 s32 ret_val = E1000_SUCCESS;
563 DEBUGFUNC("e1000_set_phy_mode_82540");
565 if (hw->mac.type != e1000_82545_rev_3)
568 ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data);
570 ret_val = -E1000_ERR_PHY;
574 if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) {
575 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
578 ret_val = -E1000_ERR_PHY;
581 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL,
584 ret_val = -E1000_ERR_PHY;
595 * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down
596 * @hw: pointer to the HW structure
598 * In the case of a PHY power down to save power, or to turn off link during a
599 * driver unload, or wake on lan is not enabled, remove the link.
601 STATIC void e1000_power_down_phy_copper_82540(struct e1000_hw *hw)
603 /* If the management interface is not enabled, then power down */
604 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
605 e1000_power_down_phy_copper(hw);
611 * e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters
612 * @hw: pointer to the HW structure
614 * Clears the hardware counters by reading the counter registers.
616 STATIC void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)
618 DEBUGFUNC("e1000_clear_hw_cntrs_82540");
620 e1000_clear_hw_cntrs_base_generic(hw);
622 E1000_READ_REG(hw, E1000_PRC64);
623 E1000_READ_REG(hw, E1000_PRC127);
624 E1000_READ_REG(hw, E1000_PRC255);
625 E1000_READ_REG(hw, E1000_PRC511);
626 E1000_READ_REG(hw, E1000_PRC1023);
627 E1000_READ_REG(hw, E1000_PRC1522);
628 E1000_READ_REG(hw, E1000_PTC64);
629 E1000_READ_REG(hw, E1000_PTC127);
630 E1000_READ_REG(hw, E1000_PTC255);
631 E1000_READ_REG(hw, E1000_PTC511);
632 E1000_READ_REG(hw, E1000_PTC1023);
633 E1000_READ_REG(hw, E1000_PTC1522);
635 E1000_READ_REG(hw, E1000_ALGNERRC);
636 E1000_READ_REG(hw, E1000_RXERRC);
637 E1000_READ_REG(hw, E1000_TNCRS);
638 E1000_READ_REG(hw, E1000_CEXTERR);
639 E1000_READ_REG(hw, E1000_TSCTC);
640 E1000_READ_REG(hw, E1000_TSCTFC);
642 E1000_READ_REG(hw, E1000_MGTPRC);
643 E1000_READ_REG(hw, E1000_MGTPDC);
644 E1000_READ_REG(hw, E1000_MGTPTC);
648 * e1000_read_mac_addr_82540 - Read device MAC address
649 * @hw: pointer to the HW structure
651 * Reads the device MAC address from the EEPROM and stores the value.
652 * Since devices with two ports use the same EEPROM, we increment the
653 * last bit in the MAC address for the second port.
655 * This version is being used over generic because of customer issues
656 * with VmWare and Virtual Box when using generic. It seems in
657 * the emulated 82545, RAR[0] does NOT have a valid address after a
658 * reset, this older method works and using this breaks nothing for
659 * these legacy adapters.
661 s32 e1000_read_mac_addr_82540(struct e1000_hw *hw)
663 s32 ret_val = E1000_SUCCESS;
664 u16 offset, nvm_data, i;
666 DEBUGFUNC("e1000_read_mac_addr");
668 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
670 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
672 DEBUGOUT("NVM Read Error\n");
675 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
676 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
679 /* Flip last bit of mac address if we're on second port */
680 if (hw->bus.func == E1000_FUNC_1)
681 hw->mac.perm_addr[5] ^= 1;
683 for (i = 0; i < ETH_ADDR_LEN; i++)
684 hw->mac.addr[i] = hw->mac.perm_addr[i];