1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
35 * 82575EB Gigabit Network Connection
36 * 82575EB Gigabit Backplane Connection
37 * 82575GB Gigabit Network Connection
38 * 82576 Gigabit Network Connection
39 * 82576 Quad Port Gigabit Mezzanine Adapter
40 * 82580 Gigabit Network Connection
41 * I350 Gigabit Network Connection
44 #include "e1000_api.h"
45 #include "e1000_i210.h"
47 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
48 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
49 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
50 STATIC void e1000_release_phy_82575(struct e1000_hw *hw);
51 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
52 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
53 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw);
54 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw);
55 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
56 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
58 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
59 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
61 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw);
62 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw);
63 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
64 u32 offset, u16 *data);
65 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
66 u32 offset, u16 data);
67 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
69 STATIC s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
71 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
73 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
74 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
75 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw);
76 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
77 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
78 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
79 u32 offset, u16 data);
80 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
81 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
82 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
83 u16 *speed, u16 *duplex);
84 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
85 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
86 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);
87 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
88 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
89 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
90 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
91 STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
92 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
93 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
94 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
95 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
96 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
97 STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
99 STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
101 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
102 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
103 STATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
105 STATIC void e1000_i2c_start(struct e1000_hw *hw);
106 STATIC void e1000_i2c_stop(struct e1000_hw *hw);
107 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
108 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
109 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
110 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
111 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
112 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
113 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
114 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
115 STATIC bool e1000_get_i2c_data(u32 *i2cctl);
117 STATIC const u16 e1000_82580_rxpbs_table[] = {
118 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
119 #define E1000_82580_RXPBS_TABLE_SIZE \
120 (sizeof(e1000_82580_rxpbs_table) / \
121 sizeof(e1000_82580_rxpbs_table[0]))
125 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
126 * @hw: pointer to the HW structure
128 * Called to determine if the I2C pins are being used for I2C or as an
129 * external MDIO interface since the two options are mutually exclusive.
131 STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
134 bool ext_mdio = false;
136 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
138 switch (hw->mac.type) {
141 reg = E1000_READ_REG(hw, E1000_MDIC);
142 ext_mdio = !!(reg & E1000_MDIC_DEST);
149 reg = E1000_READ_REG(hw, E1000_MDICNFG);
150 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
159 * e1000_init_phy_params_82575 - Init PHY func ptrs.
160 * @hw: pointer to the HW structure
162 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
164 struct e1000_phy_info *phy = &hw->phy;
165 s32 ret_val = E1000_SUCCESS;
168 DEBUGFUNC("e1000_init_phy_params_82575");
170 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
171 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
173 if (hw->phy.media_type != e1000_media_type_copper) {
174 phy->type = e1000_phy_none;
178 phy->ops.power_up = e1000_power_up_phy_copper;
179 phy->ops.power_down = e1000_power_down_phy_copper_82575;
181 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
182 phy->reset_delay_us = 100;
184 phy->ops.acquire = e1000_acquire_phy_82575;
185 phy->ops.check_reset_block = e1000_check_reset_block_generic;
186 phy->ops.commit = e1000_phy_sw_reset_generic;
187 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
188 phy->ops.release = e1000_release_phy_82575;
190 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
192 if (e1000_sgmii_active_82575(hw)) {
193 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
194 ctrl_ext |= E1000_CTRL_I2C_ENA;
196 phy->ops.reset = e1000_phy_hw_reset_generic;
197 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
200 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
201 e1000_reset_mdicnfg_82580(hw);
203 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
204 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
205 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
207 switch (hw->mac.type) {
211 phy->ops.read_reg = e1000_read_phy_reg_82580;
212 phy->ops.write_reg = e1000_write_phy_reg_82580;
216 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
217 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
220 phy->ops.read_reg = e1000_read_phy_reg_igp;
221 phy->ops.write_reg = e1000_write_phy_reg_igp;
225 /* Set phy->phy_addr and phy->id. */
226 ret_val = e1000_get_phy_id_82575(hw);
228 /* Verify phy id and set remaining function pointers */
230 case M88E1543_E_PHY_ID:
231 case M88E1512_E_PHY_ID:
232 case I347AT4_E_PHY_ID:
233 case M88E1112_E_PHY_ID:
234 case M88E1340M_E_PHY_ID:
235 case M88E1111_I_PHY_ID:
236 phy->type = e1000_phy_m88;
237 phy->ops.check_polarity = e1000_check_polarity_m88;
238 phy->ops.get_info = e1000_get_phy_info_m88;
239 if (phy->id == I347AT4_E_PHY_ID ||
240 phy->id == M88E1112_E_PHY_ID ||
241 phy->id == M88E1340M_E_PHY_ID)
242 phy->ops.get_cable_length =
243 e1000_get_cable_length_m88_gen2;
244 else if (phy->id == M88E1543_E_PHY_ID ||
245 phy->id == M88E1512_E_PHY_ID)
246 phy->ops.get_cable_length =
247 e1000_get_cable_length_m88_gen2;
249 phy->ops.get_cable_length = e1000_get_cable_length_m88;
250 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
251 /* Check if this PHY is confgured for media swap. */
252 if (phy->id == M88E1112_E_PHY_ID) {
255 ret_val = phy->ops.write_reg(hw,
256 E1000_M88E1112_PAGE_ADDR,
261 ret_val = phy->ops.read_reg(hw,
262 E1000_M88E1112_MAC_CTRL_1,
267 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
268 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
269 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
270 data == E1000_M88E1112_AUTO_COPPER_BASEX)
271 hw->mac.ops.check_for_link =
272 e1000_check_for_link_media_swap;
274 if (phy->id == M88E1512_E_PHY_ID) {
275 ret_val = e1000_initialize_M88E1512_phy(hw);
279 if (phy->id == M88E1543_E_PHY_ID) {
280 ret_val = e1000_initialize_M88E1543_phy(hw);
285 case IGP03E1000_E_PHY_ID:
286 case IGP04E1000_E_PHY_ID:
287 phy->type = e1000_phy_igp_3;
288 phy->ops.check_polarity = e1000_check_polarity_igp;
289 phy->ops.get_info = e1000_get_phy_info_igp;
290 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
291 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
292 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
293 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
295 case I82580_I_PHY_ID:
297 phy->type = e1000_phy_82580;
298 phy->ops.check_polarity = e1000_check_polarity_82577;
299 phy->ops.force_speed_duplex =
300 e1000_phy_force_speed_duplex_82577;
301 phy->ops.get_cable_length = e1000_get_cable_length_82577;
302 phy->ops.get_info = e1000_get_phy_info_82577;
303 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
304 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
307 phy->type = e1000_phy_i210;
308 phy->ops.check_polarity = e1000_check_polarity_m88;
309 phy->ops.get_info = e1000_get_phy_info_m88;
310 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
311 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
312 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
313 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
315 case BCM54616_E_PHY_ID:
316 phy->type = e1000_phy_none;
319 ret_val = -E1000_ERR_PHY;
328 * e1000_init_nvm_params_82575 - Init NVM func ptrs.
329 * @hw: pointer to the HW structure
331 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
333 struct e1000_nvm_info *nvm = &hw->nvm;
334 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
337 DEBUGFUNC("e1000_init_nvm_params_82575");
339 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
340 E1000_EECD_SIZE_EX_SHIFT);
342 * Added to a constant, "size" becomes the left-shift value
343 * for setting word_size.
345 size += NVM_WORD_SIZE_BASE_SHIFT;
347 /* Just in case size is out of range, cap it to the largest
348 * EEPROM size supported
353 nvm->word_size = 1 << size;
354 if (hw->mac.type < e1000_i210) {
355 nvm->opcode_bits = 8;
358 switch (nvm->override) {
359 case e1000_nvm_override_spi_large:
361 nvm->address_bits = 16;
363 case e1000_nvm_override_spi_small:
365 nvm->address_bits = 8;
368 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
369 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
373 if (nvm->word_size == (1 << 15))
374 nvm->page_size = 128;
376 nvm->type = e1000_nvm_eeprom_spi;
378 nvm->type = e1000_nvm_flash_hw;
381 /* Function Pointers */
382 nvm->ops.acquire = e1000_acquire_nvm_82575;
383 nvm->ops.release = e1000_release_nvm_82575;
384 if (nvm->word_size < (1 << 15))
385 nvm->ops.read = e1000_read_nvm_eerd;
387 nvm->ops.read = e1000_read_nvm_spi;
389 nvm->ops.write = e1000_write_nvm_spi;
390 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
391 nvm->ops.update = e1000_update_nvm_checksum_generic;
392 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
394 /* override generic family function pointers for specific descendants */
395 switch (hw->mac.type) {
397 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
398 nvm->ops.update = e1000_update_nvm_checksum_82580;
402 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
403 nvm->ops.update = e1000_update_nvm_checksum_i350;
409 return E1000_SUCCESS;
413 * e1000_init_mac_params_82575 - Init MAC func ptrs.
414 * @hw: pointer to the HW structure
416 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
418 struct e1000_mac_info *mac = &hw->mac;
419 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
421 DEBUGFUNC("e1000_init_mac_params_82575");
423 /* Derives media type */
424 e1000_get_media_type_82575(hw);
425 /* Set mta register count */
426 mac->mta_reg_count = 128;
427 /* Set uta register count */
428 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
429 /* Set rar entry count */
430 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
431 if (mac->type == e1000_82576)
432 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
433 if (mac->type == e1000_82580)
434 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
435 if (mac->type == e1000_i350 || mac->type == e1000_i354)
436 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
438 /* Enable EEE default settings for EEE supported devices */
439 if (mac->type >= e1000_i350)
440 dev_spec->eee_disable = false;
442 /* Allow a single clear of the SW semaphore on I210 and newer */
443 if (mac->type >= e1000_i210)
444 dev_spec->clear_semaphore_once = true;
446 /* Set if part includes ASF firmware */
447 mac->asf_firmware_present = true;
449 mac->has_fwsm = true;
450 /* ARC supported; valid only if manageability features are enabled. */
451 mac->arc_subsystem_valid =
452 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
454 /* Function pointers */
456 /* bus type/speed/width */
457 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
459 if (mac->type >= e1000_82580)
460 mac->ops.reset_hw = e1000_reset_hw_82580;
462 mac->ops.reset_hw = e1000_reset_hw_82575;
463 /* hw initialization */
464 if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
465 mac->ops.init_hw = e1000_init_hw_i210;
467 mac->ops.init_hw = e1000_init_hw_82575;
469 mac->ops.setup_link = e1000_setup_link_generic;
470 /* physical interface link setup */
471 mac->ops.setup_physical_interface =
472 (hw->phy.media_type == e1000_media_type_copper)
473 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
474 /* physical interface shutdown */
475 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
476 /* physical interface power up */
477 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
479 mac->ops.check_for_link = e1000_check_for_link_82575;
480 /* read mac address */
481 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
482 /* configure collision distance */
483 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
484 /* multicast address update */
485 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
486 if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
488 mac->ops.write_vfta = e1000_write_vfta_i350;
490 mac->ops.clear_vfta = e1000_clear_vfta_i350;
493 mac->ops.write_vfta = e1000_write_vfta_generic;
495 mac->ops.clear_vfta = e1000_clear_vfta_generic;
497 if (hw->mac.type >= e1000_82580)
498 mac->ops.validate_mdi_setting =
499 e1000_validate_mdi_setting_crossover_generic;
501 mac->ops.id_led_init = e1000_id_led_init_generic;
503 mac->ops.blink_led = e1000_blink_led_generic;
505 mac->ops.setup_led = e1000_setup_led_generic;
507 mac->ops.cleanup_led = e1000_cleanup_led_generic;
508 /* turn on/off LED */
509 mac->ops.led_on = e1000_led_on_generic;
510 mac->ops.led_off = e1000_led_off_generic;
511 /* clear hardware counters */
512 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
514 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
515 /* acquire SW_FW sync */
516 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
517 mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
518 if (mac->type >= e1000_i210) {
519 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
520 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
523 /* set lan id for port to determine which phy lock to use */
524 hw->mac.ops.set_lan_id(hw);
526 return E1000_SUCCESS;
530 * e1000_init_function_pointers_82575 - Init func ptrs.
531 * @hw: pointer to the HW structure
533 * Called to initialize all function pointers and parameters.
535 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
537 DEBUGFUNC("e1000_init_function_pointers_82575");
539 hw->mac.ops.init_params = e1000_init_mac_params_82575;
540 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
541 hw->phy.ops.init_params = e1000_init_phy_params_82575;
542 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
546 * e1000_acquire_phy_82575 - Acquire rights to access PHY
547 * @hw: pointer to the HW structure
549 * Acquire access rights to the correct PHY.
551 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
553 u16 mask = E1000_SWFW_PHY0_SM;
555 DEBUGFUNC("e1000_acquire_phy_82575");
557 if (hw->bus.func == E1000_FUNC_1)
558 mask = E1000_SWFW_PHY1_SM;
559 else if (hw->bus.func == E1000_FUNC_2)
560 mask = E1000_SWFW_PHY2_SM;
561 else if (hw->bus.func == E1000_FUNC_3)
562 mask = E1000_SWFW_PHY3_SM;
564 return hw->mac.ops.acquire_swfw_sync(hw, mask);
568 * e1000_release_phy_82575 - Release rights to access PHY
569 * @hw: pointer to the HW structure
571 * A wrapper to release access rights to the correct PHY.
573 STATIC void e1000_release_phy_82575(struct e1000_hw *hw)
575 u16 mask = E1000_SWFW_PHY0_SM;
577 DEBUGFUNC("e1000_release_phy_82575");
579 if (hw->bus.func == E1000_FUNC_1)
580 mask = E1000_SWFW_PHY1_SM;
581 else if (hw->bus.func == E1000_FUNC_2)
582 mask = E1000_SWFW_PHY2_SM;
583 else if (hw->bus.func == E1000_FUNC_3)
584 mask = E1000_SWFW_PHY3_SM;
586 hw->mac.ops.release_swfw_sync(hw, mask);
590 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
591 * @hw: pointer to the HW structure
592 * @offset: register offset to be read
593 * @data: pointer to the read data
595 * Reads the PHY register at offset using the serial gigabit media independent
596 * interface and stores the retrieved information in data.
598 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
601 s32 ret_val = -E1000_ERR_PARAM;
603 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
605 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
606 DEBUGOUT1("PHY Address %u is out of range\n", offset);
610 ret_val = hw->phy.ops.acquire(hw);
614 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
616 hw->phy.ops.release(hw);
623 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
624 * @hw: pointer to the HW structure
625 * @offset: register offset to write to
626 * @data: data to write at register offset
628 * Writes the data to PHY register at the offset using the serial gigabit
629 * media independent interface.
631 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
634 s32 ret_val = -E1000_ERR_PARAM;
636 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
638 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
639 DEBUGOUT1("PHY Address %d is out of range\n", offset);
643 ret_val = hw->phy.ops.acquire(hw);
647 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
649 hw->phy.ops.release(hw);
656 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
657 * @hw: pointer to the HW structure
659 * Retrieves the PHY address and ID for both PHY's which do and do not use
662 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
664 struct e1000_phy_info *phy = &hw->phy;
665 s32 ret_val = E1000_SUCCESS;
670 DEBUGFUNC("e1000_get_phy_id_82575");
672 /* some i354 devices need an extra read for phy id */
673 if (hw->mac.type == e1000_i354)
674 e1000_get_phy_id(hw);
677 * For SGMII PHYs, we try the list of possible addresses until
678 * we find one that works. For non-SGMII PHYs
679 * (e.g. integrated copper PHYs), an address of 1 should
680 * work. The result of this function should mean phy->phy_addr
681 * and phy->id are set correctly.
683 if (!e1000_sgmii_active_82575(hw)) {
685 ret_val = e1000_get_phy_id(hw);
689 if (e1000_sgmii_uses_mdio_82575(hw)) {
690 switch (hw->mac.type) {
693 mdic = E1000_READ_REG(hw, E1000_MDIC);
694 mdic &= E1000_MDIC_PHY_MASK;
695 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
702 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
703 mdic &= E1000_MDICNFG_PHY_MASK;
704 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
707 ret_val = -E1000_ERR_PHY;
711 ret_val = e1000_get_phy_id(hw);
715 /* Power on sgmii phy if it is disabled */
716 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
717 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
718 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
719 E1000_WRITE_FLUSH(hw);
723 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
724 * Therefore, we need to test 1-7
726 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
727 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
728 if (ret_val == E1000_SUCCESS) {
729 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
732 * At the time of this writing, The M88 part is
733 * the only supported SGMII PHY product.
735 if (phy_id == M88_VENDOR)
738 DEBUGOUT1("PHY address %u was unreadable\n",
743 /* A valid PHY type couldn't be found. */
744 if (phy->addr == 8) {
746 ret_val = -E1000_ERR_PHY;
748 ret_val = e1000_get_phy_id(hw);
751 /* restore previous sfp cage power state */
752 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
759 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
760 * @hw: pointer to the HW structure
762 * Resets the PHY using the serial gigabit media independent interface.
764 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
766 s32 ret_val = E1000_SUCCESS;
767 struct e1000_phy_info *phy = &hw->phy;
769 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
772 * This isn't a true "hard" reset, but is the only reset
773 * available to us at this time.
776 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
778 if (!(hw->phy.ops.write_reg))
782 * SFP documentation requires the following to configure the SPF module
783 * to work on SGMII. No further documentation is given.
785 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
789 ret_val = hw->phy.ops.commit(hw);
793 if (phy->id == M88E1512_E_PHY_ID)
794 ret_val = e1000_initialize_M88E1512_phy(hw);
800 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
801 * @hw: pointer to the HW structure
802 * @active: true to enable LPLU, false to disable
804 * Sets the LPLU D0 state according to the active flag. When
805 * activating LPLU this function also disables smart speed
806 * and vice versa. LPLU will not be activated unless the
807 * device autonegotiation advertisement meets standards of
808 * either 10 or 10/100 or 10/100/1000 at all duplexes.
809 * This is a function pointer entry point only called by
810 * PHY setup routines.
812 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
814 struct e1000_phy_info *phy = &hw->phy;
815 s32 ret_val = E1000_SUCCESS;
818 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
820 if (!(hw->phy.ops.read_reg))
823 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
828 data |= IGP02E1000_PM_D0_LPLU;
829 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
834 /* When LPLU is enabled, we should disable SmartSpeed */
835 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
837 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
838 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
843 data &= ~IGP02E1000_PM_D0_LPLU;
844 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
847 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
848 * during Dx states where the power conservation is most
849 * important. During driver activity we should enable
850 * SmartSpeed, so performance is maintained.
852 if (phy->smart_speed == e1000_smart_speed_on) {
853 ret_val = phy->ops.read_reg(hw,
854 IGP01E1000_PHY_PORT_CONFIG,
859 data |= IGP01E1000_PSCFR_SMART_SPEED;
860 ret_val = phy->ops.write_reg(hw,
861 IGP01E1000_PHY_PORT_CONFIG,
865 } else if (phy->smart_speed == e1000_smart_speed_off) {
866 ret_val = phy->ops.read_reg(hw,
867 IGP01E1000_PHY_PORT_CONFIG,
872 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
873 ret_val = phy->ops.write_reg(hw,
874 IGP01E1000_PHY_PORT_CONFIG,
886 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
887 * @hw: pointer to the HW structure
888 * @active: true to enable LPLU, false to disable
890 * Sets the LPLU D0 state according to the active flag. When
891 * activating LPLU this function also disables smart speed
892 * and vice versa. LPLU will not be activated unless the
893 * device autonegotiation advertisement meets standards of
894 * either 10 or 10/100 or 10/100/1000 at all duplexes.
895 * This is a function pointer entry point only called by
896 * PHY setup routines.
898 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
900 struct e1000_phy_info *phy = &hw->phy;
903 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
905 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
908 data |= E1000_82580_PM_D0_LPLU;
910 /* When LPLU is enabled, we should disable SmartSpeed */
911 data &= ~E1000_82580_PM_SPD;
913 data &= ~E1000_82580_PM_D0_LPLU;
916 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
917 * during Dx states where the power conservation is most
918 * important. During driver activity we should enable
919 * SmartSpeed, so performance is maintained.
921 if (phy->smart_speed == e1000_smart_speed_on)
922 data |= E1000_82580_PM_SPD;
923 else if (phy->smart_speed == e1000_smart_speed_off)
924 data &= ~E1000_82580_PM_SPD;
927 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
928 return E1000_SUCCESS;
932 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
933 * @hw: pointer to the HW structure
934 * @active: boolean used to enable/disable lplu
936 * Success returns 0, Failure returns 1
938 * The low power link up (lplu) state is set to the power management level D3
939 * and SmartSpeed is disabled when active is true, else clear lplu for D3
940 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
941 * is used during Dx states where the power conservation is most important.
942 * During driver activity, SmartSpeed should be enabled so performance is
945 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
947 struct e1000_phy_info *phy = &hw->phy;
950 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
952 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
955 data &= ~E1000_82580_PM_D3_LPLU;
957 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
958 * during Dx states where the power conservation is most
959 * important. During driver activity we should enable
960 * SmartSpeed, so performance is maintained.
962 if (phy->smart_speed == e1000_smart_speed_on)
963 data |= E1000_82580_PM_SPD;
964 else if (phy->smart_speed == e1000_smart_speed_off)
965 data &= ~E1000_82580_PM_SPD;
966 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
967 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
968 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
969 data |= E1000_82580_PM_D3_LPLU;
970 /* When LPLU is enabled, we should disable SmartSpeed */
971 data &= ~E1000_82580_PM_SPD;
974 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
975 return E1000_SUCCESS;
979 * e1000_acquire_nvm_82575 - Request for access to EEPROM
980 * @hw: pointer to the HW structure
982 * Acquire the necessary semaphores for exclusive access to the EEPROM.
983 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
984 * Return successful if access grant bit set, else clear the request for
985 * EEPROM access and return -E1000_ERR_NVM (-1).
987 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
989 s32 ret_val = E1000_SUCCESS;
991 DEBUGFUNC("e1000_acquire_nvm_82575");
993 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
998 * Check if there is some access
999 * error this access may hook on
1001 if (hw->mac.type == e1000_i350) {
1002 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1003 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
1004 E1000_EECD_TIMEOUT)) {
1005 /* Clear all access error flags */
1006 E1000_WRITE_REG(hw, E1000_EECD, eecd |
1007 E1000_EECD_ERROR_CLR);
1008 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1012 if (hw->mac.type == e1000_82580) {
1013 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1014 if (eecd & E1000_EECD_BLOCKED) {
1015 /* Clear access error flag */
1016 E1000_WRITE_REG(hw, E1000_EECD, eecd |
1017 E1000_EECD_BLOCKED);
1018 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1022 ret_val = e1000_acquire_nvm_generic(hw);
1024 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1031 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
1032 * @hw: pointer to the HW structure
1034 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1035 * then release the semaphores acquired.
1037 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
1039 DEBUGFUNC("e1000_release_nvm_82575");
1041 e1000_release_nvm_generic(hw);
1043 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1047 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1048 * @hw: pointer to the HW structure
1049 * @mask: specifies which semaphore to acquire
1051 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1052 * will also specify which port we're acquiring the lock for.
1054 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1058 u32 fwmask = mask << 16;
1059 s32 ret_val = E1000_SUCCESS;
1060 s32 i = 0, timeout = 200;
1062 DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1064 while (i < timeout) {
1065 if (e1000_get_hw_semaphore_generic(hw)) {
1066 ret_val = -E1000_ERR_SWFW_SYNC;
1070 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1071 if (!(swfw_sync & (fwmask | swmask)))
1075 * Firmware currently using resource (fwmask)
1076 * or other software thread using resource (swmask)
1078 e1000_put_hw_semaphore_generic(hw);
1084 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1085 ret_val = -E1000_ERR_SWFW_SYNC;
1089 swfw_sync |= swmask;
1090 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1092 e1000_put_hw_semaphore_generic(hw);
1099 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1100 * @hw: pointer to the HW structure
1101 * @mask: specifies which semaphore to acquire
1103 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1104 * will also specify which port we're releasing the lock for.
1106 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1110 DEBUGFUNC("e1000_release_swfw_sync_82575");
1112 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1115 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1117 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1119 e1000_put_hw_semaphore_generic(hw);
1123 * e1000_get_cfg_done_82575 - Read config done bit
1124 * @hw: pointer to the HW structure
1126 * Read the management control register for the config done bit for
1127 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1128 * to read the config done bit, so an error is *ONLY* logged and returns
1129 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1130 * would not be able to be reset or change link.
1132 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1134 s32 timeout = PHY_CFG_TIMEOUT;
1135 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1137 DEBUGFUNC("e1000_get_cfg_done_82575");
1139 if (hw->bus.func == E1000_FUNC_1)
1140 mask = E1000_NVM_CFG_DONE_PORT_1;
1141 else if (hw->bus.func == E1000_FUNC_2)
1142 mask = E1000_NVM_CFG_DONE_PORT_2;
1143 else if (hw->bus.func == E1000_FUNC_3)
1144 mask = E1000_NVM_CFG_DONE_PORT_3;
1146 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1152 DEBUGOUT("MNG configuration cycle has not completed.\n");
1154 /* If EEPROM is not marked present, init the PHY manually */
1155 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1156 (hw->phy.type == e1000_phy_igp_3))
1157 e1000_phy_init_script_igp3(hw);
1159 return E1000_SUCCESS;
1163 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1164 * @hw: pointer to the HW structure
1165 * @speed: stores the current speed
1166 * @duplex: stores the current duplex
1168 * This is a wrapper function, if using the serial gigabit media independent
1169 * interface, use PCS to retrieve the link speed and duplex information.
1170 * Otherwise, use the generic function to get the link speed and duplex info.
1172 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1177 DEBUGFUNC("e1000_get_link_up_info_82575");
1179 if (hw->phy.media_type != e1000_media_type_copper)
1180 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1183 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1190 * e1000_check_for_link_82575 - Check for link
1191 * @hw: pointer to the HW structure
1193 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1194 * use the generic interface for determining link.
1196 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1201 DEBUGFUNC("e1000_check_for_link_82575");
1203 if (hw->phy.media_type != e1000_media_type_copper) {
1204 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1207 * Use this flag to determine if link needs to be checked or
1208 * not. If we have link clear the flag so that we do not
1209 * continue to check for link.
1211 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1214 * Configure Flow Control now that Auto-Neg has completed.
1215 * First, we need to restore the desired flow control
1216 * settings because we may have had to re-autoneg with a
1217 * different link partner.
1219 ret_val = e1000_config_fc_after_link_up_generic(hw);
1221 DEBUGOUT("Error configuring flow control\n");
1223 ret_val = e1000_check_for_copper_link_generic(hw);
1230 * e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1231 * @hw: pointer to the HW structure
1233 * Poll the M88E1112 interfaces to see which interface achieved link.
1235 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1237 struct e1000_phy_info *phy = &hw->phy;
1242 DEBUGFUNC("e1000_check_for_link_media_swap");
1244 /* Check for copper. */
1245 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1249 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1253 if (data & E1000_M88E1112_STATUS_LINK)
1254 port = E1000_MEDIA_PORT_COPPER;
1256 /* Check for other. */
1257 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1261 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1265 if (data & E1000_M88E1112_STATUS_LINK)
1266 port = E1000_MEDIA_PORT_OTHER;
1268 /* Determine if a swap needs to happen. */
1269 if (port && (hw->dev_spec._82575.media_port != port)) {
1270 hw->dev_spec._82575.media_port = port;
1271 hw->dev_spec._82575.media_changed = true;
1274 if (port == E1000_MEDIA_PORT_COPPER) {
1275 /* reset page to 0 */
1276 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1279 e1000_check_for_link_82575(hw);
1281 e1000_check_for_link_82575(hw);
1282 /* reset page to 0 */
1283 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1288 return E1000_SUCCESS;
1292 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1293 * @hw: pointer to the HW structure
1295 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1299 DEBUGFUNC("e1000_power_up_serdes_link_82575");
1301 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1302 !e1000_sgmii_active_82575(hw))
1305 /* Enable PCS to turn on link */
1306 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1307 reg |= E1000_PCS_CFG_PCS_EN;
1308 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1310 /* Power up the laser */
1311 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1312 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1313 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1315 /* flush the write to verify completion */
1316 E1000_WRITE_FLUSH(hw);
1321 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1322 * @hw: pointer to the HW structure
1323 * @speed: stores the current speed
1324 * @duplex: stores the current duplex
1326 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1327 * duplex, then store the values in the pointers provided.
1329 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1330 u16 *speed, u16 *duplex)
1332 struct e1000_mac_info *mac = &hw->mac;
1336 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1339 * Read the PCS Status register for link state. For non-copper mode,
1340 * the status register is not accurate. The PCS status register is
1343 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1346 * The link up bit determines when link is up on autoneg.
1348 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1349 mac->serdes_has_link = true;
1351 /* Detect and store PCS speed */
1352 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1353 *speed = SPEED_1000;
1354 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1359 /* Detect and store PCS duplex */
1360 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1361 *duplex = FULL_DUPLEX;
1363 *duplex = HALF_DUPLEX;
1365 /* Check if it is an I354 2.5Gb backplane connection. */
1366 if (mac->type == e1000_i354) {
1367 status = E1000_READ_REG(hw, E1000_STATUS);
1368 if ((status & E1000_STATUS_2P5_SKU) &&
1369 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1370 *speed = SPEED_2500;
1371 *duplex = FULL_DUPLEX;
1372 DEBUGOUT("2500 Mbs, ");
1373 DEBUGOUT("Full Duplex\n");
1378 mac->serdes_has_link = false;
1383 return E1000_SUCCESS;
1387 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1388 * @hw: pointer to the HW structure
1390 * In the case of serdes shut down sfp and PCS on driver unload
1391 * when management pass thru is not enabled.
1393 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1397 DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1399 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1400 !e1000_sgmii_active_82575(hw))
1403 if (!e1000_enable_mng_pass_thru(hw)) {
1404 /* Disable PCS to turn off link */
1405 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1406 reg &= ~E1000_PCS_CFG_PCS_EN;
1407 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1409 /* shutdown the laser */
1410 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1411 reg |= E1000_CTRL_EXT_SDP3_DATA;
1412 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1414 /* flush the write to verify completion */
1415 E1000_WRITE_FLUSH(hw);
1423 * e1000_reset_hw_82575 - Reset hardware
1424 * @hw: pointer to the HW structure
1426 * This resets the hardware into a known state.
1428 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1433 DEBUGFUNC("e1000_reset_hw_82575");
1436 * Prevent the PCI-E bus from sticking if there is no TLP connection
1437 * on the last TLP read/write transaction when MAC is reset.
1439 ret_val = e1000_disable_pcie_master_generic(hw);
1441 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1443 /* set the completion timeout for interface */
1444 ret_val = e1000_set_pcie_completion_timeout(hw);
1446 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1448 DEBUGOUT("Masking off all interrupts\n");
1449 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1451 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1452 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1453 E1000_WRITE_FLUSH(hw);
1457 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1459 DEBUGOUT("Issuing a global reset to MAC\n");
1460 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1462 ret_val = e1000_get_auto_rd_done_generic(hw);
1465 * When auto config read does not complete, do not
1466 * return with an error. This can happen in situations
1467 * where there is no eeprom and prevents getting link.
1469 DEBUGOUT("Auto Read Done did not complete\n");
1472 /* If EEPROM is not present, run manual init scripts */
1473 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1474 e1000_reset_init_script_82575(hw);
1476 /* Clear any pending interrupt events. */
1477 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1478 E1000_READ_REG(hw, E1000_ICR);
1480 /* Install any alternate MAC address into RAR0 */
1481 ret_val = e1000_check_alt_mac_addr_generic(hw);
1487 * e1000_init_hw_82575 - Initialize hardware
1488 * @hw: pointer to the HW structure
1490 * This inits the hardware readying it for operation.
1492 s32 e1000_init_hw_82575(struct e1000_hw *hw)
1494 struct e1000_mac_info *mac = &hw->mac;
1496 u16 i, rar_count = mac->rar_entry_count;
1498 DEBUGFUNC("e1000_init_hw_82575");
1500 /* Initialize identification LED */
1501 ret_val = mac->ops.id_led_init(hw);
1503 DEBUGOUT("Error initializing identification LED\n");
1504 /* This is not fatal and we should not stop init due to this */
1507 /* Disabling VLAN filtering */
1508 DEBUGOUT("Initializing the IEEE VLAN\n");
1509 mac->ops.clear_vfta(hw);
1511 /* Setup the receive address */
1512 e1000_init_rx_addrs_generic(hw, rar_count);
1514 /* Zero out the Multicast HASH table */
1515 DEBUGOUT("Zeroing the MTA\n");
1516 for (i = 0; i < mac->mta_reg_count; i++)
1517 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1519 /* Zero out the Unicast HASH table */
1520 DEBUGOUT("Zeroing the UTA\n");
1521 for (i = 0; i < mac->uta_reg_count; i++)
1522 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1524 /* Setup link and flow control */
1525 ret_val = mac->ops.setup_link(hw);
1527 /* Set the default MTU size */
1528 hw->dev_spec._82575.mtu = 1500;
1531 * Clear all of the statistics registers (clear on read). It is
1532 * important that we do this after we have tried to establish link
1533 * because the symbol error count will increment wildly if there
1536 e1000_clear_hw_cntrs_82575(hw);
1542 * e1000_setup_copper_link_82575 - Configure copper link settings
1543 * @hw: pointer to the HW structure
1545 * Configures the link for auto-neg or forced speed and duplex. Then we check
1546 * for link, once link is established calls to configure collision distance
1547 * and flow control are called.
1549 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1555 DEBUGFUNC("e1000_setup_copper_link_82575");
1557 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1558 ctrl |= E1000_CTRL_SLU;
1559 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1560 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1562 /* Clear Go Link Disconnect bit on supported devices */
1563 switch (hw->mac.type) {
1568 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1569 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1570 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1576 ret_val = e1000_setup_serdes_link_82575(hw);
1580 if (e1000_sgmii_active_82575(hw)) {
1581 /* allow time for SFP cage time to power up phy */
1584 ret_val = hw->phy.ops.reset(hw);
1586 DEBUGOUT("Error resetting the PHY.\n");
1590 switch (hw->phy.type) {
1591 case e1000_phy_i210:
1593 switch (hw->phy.id) {
1594 case I347AT4_E_PHY_ID:
1595 case M88E1112_E_PHY_ID:
1596 case M88E1340M_E_PHY_ID:
1597 case M88E1543_E_PHY_ID:
1598 case M88E1512_E_PHY_ID:
1600 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1603 ret_val = e1000_copper_link_setup_m88(hw);
1607 case e1000_phy_igp_3:
1608 ret_val = e1000_copper_link_setup_igp(hw);
1610 case e1000_phy_82580:
1611 ret_val = e1000_copper_link_setup_82577(hw);
1613 case e1000_phy_none:
1616 ret_val = -E1000_ERR_PHY;
1623 ret_val = e1000_setup_copper_link_generic(hw);
1629 * e1000_setup_serdes_link_82575 - Setup link for serdes
1630 * @hw: pointer to the HW structure
1632 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1633 * used on copper connections where the serialized gigabit media independent
1634 * interface (sgmii), or serdes fiber is being used. Configures the link
1635 * for auto-negotiation or forces speed/duplex.
1637 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1639 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1641 s32 ret_val = E1000_SUCCESS;
1644 DEBUGFUNC("e1000_setup_serdes_link_82575");
1646 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1647 !e1000_sgmii_active_82575(hw))
1651 * On the 82575, SerDes loopback mode persists until it is
1652 * explicitly turned off or a power cycle is performed. A read to
1653 * the register does not indicate its status. Therefore, we ensure
1654 * loopback mode is disabled during initialization.
1656 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1658 /* power on the sfp cage if present */
1659 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1660 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1661 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1663 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1664 ctrl_reg |= E1000_CTRL_SLU;
1666 /* set both sw defined pins on 82575/82576*/
1667 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1668 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1670 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1672 /* default pcs_autoneg to the same setting as mac autoneg */
1673 pcs_autoneg = hw->mac.autoneg;
1675 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1676 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1677 /* sgmii mode lets the phy handle forcing speed/duplex */
1679 /* autoneg time out should be disabled for SGMII mode */
1680 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1682 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1683 /* disable PCS autoneg and support parallel detect only */
1684 pcs_autoneg = false;
1685 /* fall through to default case */
1687 if (hw->mac.type == e1000_82575 ||
1688 hw->mac.type == e1000_82576) {
1689 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1691 DEBUGOUT("NVM Read Error\n");
1695 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1696 pcs_autoneg = false;
1700 * non-SGMII modes only supports a speed of 1000/Full for the
1701 * link so it is best to just force the MAC and let the pcs
1702 * link either autoneg or be forced to 1000/Full
1704 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1705 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1707 /* set speed of 1000/Full if speed/duplex is forced */
1708 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1712 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1715 * New SerDes mode allows for forcing speed or autonegotiating speed
1716 * at 1gb. Autoneg should be default set by most drivers. This is the
1717 * mode that will be compatible with older link partners and switches.
1718 * However, both are supported by the hardware and some drivers/tools.
1720 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1721 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1724 /* Set PCS register for autoneg */
1725 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1726 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1728 /* Disable force flow control for autoneg */
1729 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1731 /* Configure flow control advertisement for autoneg */
1732 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1733 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1735 switch (hw->fc.requested_mode) {
1737 case e1000_fc_rx_pause:
1738 anadv_reg |= E1000_TXCW_ASM_DIR;
1739 anadv_reg |= E1000_TXCW_PAUSE;
1741 case e1000_fc_tx_pause:
1742 anadv_reg |= E1000_TXCW_ASM_DIR;
1748 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1750 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1752 /* Set PCS register for forced link */
1753 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1755 /* Force flow control for forced link */
1756 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1758 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1761 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1763 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1764 e1000_force_mac_fc_generic(hw);
1770 * e1000_get_media_type_82575 - derives current media type.
1771 * @hw: pointer to the HW structure
1773 * The media type is chosen reflecting few settings.
1774 * The following are taken into account:
1775 * - link mode set in the current port Init Control Word #3
1776 * - current link mode settings in CSR register
1777 * - MDIO vs. I2C PHY control interface chosen
1778 * - SFP module media type
1780 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1782 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1783 s32 ret_val = E1000_SUCCESS;
1787 /* Set internal phy as default */
1788 dev_spec->sgmii_active = false;
1789 dev_spec->module_plugged = false;
1791 /* Get CSR setting */
1792 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1794 /* extract link mode setting */
1795 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1797 switch (link_mode) {
1798 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1799 hw->phy.media_type = e1000_media_type_internal_serdes;
1801 case E1000_CTRL_EXT_LINK_MODE_GMII:
1802 hw->phy.media_type = e1000_media_type_copper;
1804 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1805 /* Get phy control interface type set (MDIO vs. I2C)*/
1806 if (e1000_sgmii_uses_mdio_82575(hw)) {
1807 hw->phy.media_type = e1000_media_type_copper;
1808 dev_spec->sgmii_active = true;
1811 /* fall through for I2C based SGMII */
1812 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1813 /* read media type from SFP EEPROM */
1814 ret_val = e1000_set_sfp_media_type_82575(hw);
1815 if ((ret_val != E1000_SUCCESS) ||
1816 (hw->phy.media_type == e1000_media_type_unknown)) {
1818 * If media type was not identified then return media
1819 * type defined by the CTRL_EXT settings.
1821 hw->phy.media_type = e1000_media_type_internal_serdes;
1823 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1824 hw->phy.media_type = e1000_media_type_copper;
1825 dev_spec->sgmii_active = true;
1831 /* do not change link mode for 100BaseFX */
1832 if (dev_spec->eth_flags.e100_base_fx)
1835 /* change current link mode setting */
1836 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1838 if (hw->phy.media_type == e1000_media_type_copper)
1839 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1841 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1843 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1852 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1853 * @hw: pointer to the HW structure
1855 * The media type is chosen based on SFP module.
1856 * compatibility flags retrieved from SFP ID EEPROM.
1858 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1860 s32 ret_val = E1000_ERR_CONFIG;
1862 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1863 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1864 u8 tranceiver_type = 0;
1867 /* Turn I2C interface ON and power on sfp cage */
1868 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1869 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1870 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1872 E1000_WRITE_FLUSH(hw);
1874 /* Read SFP module data */
1876 ret_val = e1000_read_sfp_data_byte(hw,
1877 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1879 if (ret_val == E1000_SUCCESS)
1884 if (ret_val != E1000_SUCCESS)
1887 ret_val = e1000_read_sfp_data_byte(hw,
1888 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1890 if (ret_val != E1000_SUCCESS)
1893 /* Check if there is some SFP module plugged and powered */
1894 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1895 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1896 dev_spec->module_plugged = true;
1897 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1898 hw->phy.media_type = e1000_media_type_internal_serdes;
1899 } else if (eth_flags->e100_base_fx) {
1900 dev_spec->sgmii_active = true;
1901 hw->phy.media_type = e1000_media_type_internal_serdes;
1902 } else if (eth_flags->e1000_base_t) {
1903 dev_spec->sgmii_active = true;
1904 hw->phy.media_type = e1000_media_type_copper;
1906 hw->phy.media_type = e1000_media_type_unknown;
1907 DEBUGOUT("PHY module has not been recognized\n");
1911 hw->phy.media_type = e1000_media_type_unknown;
1913 ret_val = E1000_SUCCESS;
1915 /* Restore I2C interface setting */
1916 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1921 * e1000_valid_led_default_82575 - Verify a valid default LED config
1922 * @hw: pointer to the HW structure
1923 * @data: pointer to the NVM (EEPROM)
1925 * Read the EEPROM for the current default LED configuration. If the
1926 * LED configuration is not valid, set to a valid LED configuration.
1928 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1932 DEBUGFUNC("e1000_valid_led_default_82575");
1934 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1936 DEBUGOUT("NVM Read Error\n");
1940 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1941 switch (hw->phy.media_type) {
1942 case e1000_media_type_internal_serdes:
1943 *data = ID_LED_DEFAULT_82575_SERDES;
1945 case e1000_media_type_copper:
1947 *data = ID_LED_DEFAULT;
1956 * e1000_sgmii_active_82575 - Return sgmii state
1957 * @hw: pointer to the HW structure
1959 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1960 * which can be enabled for use in the embedded applications. Simply
1961 * return the current state of the sgmii interface.
1963 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1965 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1966 return dev_spec->sgmii_active;
1970 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1971 * @hw: pointer to the HW structure
1973 * Inits recommended HW defaults after a reset when there is no EEPROM
1974 * detected. This is only for the 82575.
1976 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1978 DEBUGFUNC("e1000_reset_init_script_82575");
1980 if (hw->mac.type == e1000_82575) {
1981 DEBUGOUT("Running reset init script for 82575\n");
1982 /* SerDes configuration via SERDESCTRL */
1983 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1984 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1985 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1986 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1988 /* CCM configuration via CCMCTL register */
1989 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1990 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1992 /* PCIe lanes configuration */
1993 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1994 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1995 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1996 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1998 /* PCIe PLL Configuration */
1999 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
2000 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
2001 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
2004 return E1000_SUCCESS;
2008 * e1000_read_mac_addr_82575 - Read device MAC address
2009 * @hw: pointer to the HW structure
2011 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
2015 DEBUGFUNC("e1000_read_mac_addr_82575");
2018 * If there's an alternate MAC address place it in RAR0
2019 * so that it will override the Si installed default perm
2022 ret_val = e1000_check_alt_mac_addr_generic(hw);
2026 ret_val = e1000_read_mac_addr_generic(hw);
2033 * e1000_config_collision_dist_82575 - Configure collision distance
2034 * @hw: pointer to the HW structure
2036 * Configures the collision distance to the default value and is used
2037 * during link setup.
2039 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2043 DEBUGFUNC("e1000_config_collision_dist_82575");
2045 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2047 tctl_ext &= ~E1000_TCTL_EXT_COLD;
2048 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2050 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2051 E1000_WRITE_FLUSH(hw);
2055 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2056 * @hw: pointer to the HW structure
2058 * In the case of a PHY power down to save power, or to turn off link during a
2059 * driver unload, or wake on lan is not enabled, remove the link.
2061 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2063 struct e1000_phy_info *phy = &hw->phy;
2065 if (!(phy->ops.check_reset_block))
2068 /* If the management interface is not enabled, then power down */
2069 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2070 e1000_power_down_phy_copper(hw);
2076 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2077 * @hw: pointer to the HW structure
2079 * Clears the hardware counters by reading the counter registers.
2081 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2083 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2085 e1000_clear_hw_cntrs_base_generic(hw);
2087 E1000_READ_REG(hw, E1000_PRC64);
2088 E1000_READ_REG(hw, E1000_PRC127);
2089 E1000_READ_REG(hw, E1000_PRC255);
2090 E1000_READ_REG(hw, E1000_PRC511);
2091 E1000_READ_REG(hw, E1000_PRC1023);
2092 E1000_READ_REG(hw, E1000_PRC1522);
2093 E1000_READ_REG(hw, E1000_PTC64);
2094 E1000_READ_REG(hw, E1000_PTC127);
2095 E1000_READ_REG(hw, E1000_PTC255);
2096 E1000_READ_REG(hw, E1000_PTC511);
2097 E1000_READ_REG(hw, E1000_PTC1023);
2098 E1000_READ_REG(hw, E1000_PTC1522);
2100 E1000_READ_REG(hw, E1000_ALGNERRC);
2101 E1000_READ_REG(hw, E1000_RXERRC);
2102 E1000_READ_REG(hw, E1000_TNCRS);
2103 E1000_READ_REG(hw, E1000_CEXTERR);
2104 E1000_READ_REG(hw, E1000_TSCTC);
2105 E1000_READ_REG(hw, E1000_TSCTFC);
2107 E1000_READ_REG(hw, E1000_MGTPRC);
2108 E1000_READ_REG(hw, E1000_MGTPDC);
2109 E1000_READ_REG(hw, E1000_MGTPTC);
2111 E1000_READ_REG(hw, E1000_IAC);
2112 E1000_READ_REG(hw, E1000_ICRXOC);
2114 E1000_READ_REG(hw, E1000_ICRXPTC);
2115 E1000_READ_REG(hw, E1000_ICRXATC);
2116 E1000_READ_REG(hw, E1000_ICTXPTC);
2117 E1000_READ_REG(hw, E1000_ICTXATC);
2118 E1000_READ_REG(hw, E1000_ICTXQEC);
2119 E1000_READ_REG(hw, E1000_ICTXQMTC);
2120 E1000_READ_REG(hw, E1000_ICRXDMTC);
2122 E1000_READ_REG(hw, E1000_CBTMPC);
2123 E1000_READ_REG(hw, E1000_HTDPMC);
2124 E1000_READ_REG(hw, E1000_CBRMPC);
2125 E1000_READ_REG(hw, E1000_RPTHC);
2126 E1000_READ_REG(hw, E1000_HGPTC);
2127 E1000_READ_REG(hw, E1000_HTCBDPC);
2128 E1000_READ_REG(hw, E1000_HGORCL);
2129 E1000_READ_REG(hw, E1000_HGORCH);
2130 E1000_READ_REG(hw, E1000_HGOTCL);
2131 E1000_READ_REG(hw, E1000_HGOTCH);
2132 E1000_READ_REG(hw, E1000_LENERRS);
2134 /* This register should not be read in copper configurations */
2135 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2136 e1000_sgmii_active_82575(hw))
2137 E1000_READ_REG(hw, E1000_SCVPC);
2141 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2142 * @hw: pointer to the HW structure
2144 * After Rx enable, if manageability is enabled then there is likely some
2145 * bad data at the start of the fifo and possibly in the DMA fifo. This
2146 * function clears the fifos and flushes any packets that came in as rx was
2149 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2151 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2154 DEBUGFUNC("e1000_rx_fifo_flush_82575");
2156 /* disable IPv6 options as per hardware errata */
2157 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2158 rfctl |= E1000_RFCTL_IPV6_EX_DIS;
2159 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2161 if (hw->mac.type != e1000_82575 ||
2162 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2165 /* Disable all Rx queues */
2166 for (i = 0; i < 4; i++) {
2167 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2168 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2169 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2171 /* Poll all queues to verify they have shut down */
2172 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2175 for (i = 0; i < 4; i++)
2176 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2177 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2182 DEBUGOUT("Queue disable timed out after 10ms\n");
2184 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2185 * incoming packets are rejected. Set enable and wait 2ms so that
2186 * any packet that was coming in as RCTL.EN was set is flushed
2188 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2190 rlpml = E1000_READ_REG(hw, E1000_RLPML);
2191 E1000_WRITE_REG(hw, E1000_RLPML, 0);
2193 rctl = E1000_READ_REG(hw, E1000_RCTL);
2194 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2195 temp_rctl |= E1000_RCTL_LPE;
2197 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2198 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2199 E1000_WRITE_FLUSH(hw);
2202 /* Enable Rx queues that were previously enabled and restore our
2205 for (i = 0; i < 4; i++)
2206 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2207 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2208 E1000_WRITE_FLUSH(hw);
2210 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2211 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2213 /* Flush receive errors generated by workaround */
2214 E1000_READ_REG(hw, E1000_ROC);
2215 E1000_READ_REG(hw, E1000_RNBC);
2216 E1000_READ_REG(hw, E1000_MPC);
2220 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
2221 * @hw: pointer to the HW structure
2223 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2224 * however the hardware default for these parts is 500us to 1ms which is less
2225 * than the 10ms recommended by the pci-e spec. To address this we need to
2226 * increase the value to either 10ms to 200ms for capability version 1 config,
2227 * or 16ms to 55ms for version 2.
2229 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2231 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2232 s32 ret_val = E1000_SUCCESS;
2235 /* only take action if timeout value is defaulted to 0 */
2236 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2240 * if capababilities version is type 1 we can write the
2241 * timeout of 10ms to 200ms through the GCR register
2243 if (!(gcr & E1000_GCR_CAP_VER2)) {
2244 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2249 * for version 2 capabilities we need to write the config space
2250 * directly in order to set the completion timeout value for
2253 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2258 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2260 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2263 /* disable completion timeout resend */
2264 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2266 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2271 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2272 * @hw: pointer to the hardware struct
2273 * @enable: state to enter, either enabled or disabled
2274 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2276 * enables/disables L2 switch anti-spoofing functionality.
2278 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2280 u32 reg_val, reg_offset;
2282 switch (hw->mac.type) {
2284 reg_offset = E1000_DTXSWC;
2288 reg_offset = E1000_TXSWC;
2294 reg_val = E1000_READ_REG(hw, reg_offset);
2296 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2297 E1000_DTXSWC_VLAN_SPOOF_MASK);
2298 /* The PF can spoof - it has to in order to
2299 * support emulation mode NICs
2301 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2303 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2304 E1000_DTXSWC_VLAN_SPOOF_MASK);
2306 E1000_WRITE_REG(hw, reg_offset, reg_val);
2310 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2311 * @hw: pointer to the hardware struct
2312 * @enable: state to enter, either enabled or disabled
2314 * enables/disables L2 switch loopback functionality.
2316 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2320 switch (hw->mac.type) {
2322 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2324 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2326 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2327 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2331 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2333 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2335 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2336 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2339 /* Currently no other hardware supports loopback */
2347 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2348 * @hw: pointer to the hardware struct
2349 * @enable: state to enter, either enabled or disabled
2351 * enables/disables replication of packets across multiple pools.
2353 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2355 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2358 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2360 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2362 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2366 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
2367 * @hw: pointer to the HW structure
2368 * @offset: register offset to be read
2369 * @data: pointer to the read data
2371 * Reads the MDI control register in the PHY at offset and stores the
2372 * information read to data.
2374 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2378 DEBUGFUNC("e1000_read_phy_reg_82580");
2380 ret_val = hw->phy.ops.acquire(hw);
2384 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2386 hw->phy.ops.release(hw);
2393 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
2394 * @hw: pointer to the HW structure
2395 * @offset: register offset to write to
2396 * @data: data to write to register at offset
2398 * Writes data to MDI control register in the PHY at offset.
2400 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2404 DEBUGFUNC("e1000_write_phy_reg_82580");
2406 ret_val = hw->phy.ops.acquire(hw);
2410 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2412 hw->phy.ops.release(hw);
2419 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2420 * @hw: pointer to the HW structure
2422 * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2423 * the values found in the EEPROM. This addresses an issue in which these
2424 * bits are not restored from EEPROM after reset.
2426 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2428 s32 ret_val = E1000_SUCCESS;
2432 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2434 if (hw->mac.type != e1000_82580)
2436 if (!e1000_sgmii_active_82575(hw))
2439 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2440 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2443 DEBUGOUT("NVM Read Error\n");
2447 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2448 if (nvm_data & NVM_WORD24_EXT_MDIO)
2449 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2450 if (nvm_data & NVM_WORD24_COM_MDIO)
2451 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2452 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2458 * e1000_reset_hw_82580 - Reset hardware
2459 * @hw: pointer to the HW structure
2461 * This resets function or entire device (all ports, etc.)
2464 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2466 s32 ret_val = E1000_SUCCESS;
2467 /* BH SW mailbox bit in SW_FW_SYNC */
2468 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2470 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2472 DEBUGFUNC("e1000_reset_hw_82580");
2474 hw->dev_spec._82575.global_device_reset = false;
2476 /* 82580 does not reliably do global_device_reset due to hw errata */
2477 if (hw->mac.type == e1000_82580)
2478 global_device_reset = false;
2480 /* Get current control state. */
2481 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2484 * Prevent the PCI-E bus from sticking if there is no TLP connection
2485 * on the last TLP read/write transaction when MAC is reset.
2487 ret_val = e1000_disable_pcie_master_generic(hw);
2489 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2491 DEBUGOUT("Masking off all interrupts\n");
2492 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2493 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2494 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2495 E1000_WRITE_FLUSH(hw);
2499 /* Determine whether or not a global dev reset is requested */
2500 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2502 global_device_reset = false;
2504 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2505 E1000_STAT_DEV_RST_SET))
2506 ctrl |= E1000_CTRL_DEV_RST;
2508 ctrl |= E1000_CTRL_RST;
2510 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2512 switch (hw->device_id) {
2513 case E1000_DEV_ID_DH89XXCC_SGMII:
2516 E1000_WRITE_FLUSH(hw);
2520 /* Add delay to insure DEV_RST or RST has time to complete */
2523 ret_val = e1000_get_auto_rd_done_generic(hw);
2526 * When auto config read does not complete, do not
2527 * return with an error. This can happen in situations
2528 * where there is no eeprom and prevents getting link.
2530 DEBUGOUT("Auto Read Done did not complete\n");
2533 /* clear global device reset status bit */
2534 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2536 /* Clear any pending interrupt events. */
2537 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2538 E1000_READ_REG(hw, E1000_ICR);
2540 ret_val = e1000_reset_mdicnfg_82580(hw);
2542 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2544 /* Install any alternate MAC address into RAR0 */
2545 ret_val = e1000_check_alt_mac_addr_generic(hw);
2547 /* Release semaphore */
2548 if (global_device_reset)
2549 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2555 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2556 * @data: data received by reading RXPBS register
2558 * The 82580 uses a table based approach for packet buffer allocation sizes.
2559 * This function converts the retrieved value into the correct table value
2560 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2561 * 0x0 36 72 144 1 2 4 8 16
2562 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2564 u16 e1000_rxpbs_adjust_82580(u32 data)
2568 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2569 ret_val = e1000_82580_rxpbs_table[data];
2575 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2577 * @hw: pointer to the HW structure
2578 * @offset: offset in words of the checksum protected region
2580 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2581 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2583 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2585 s32 ret_val = E1000_SUCCESS;
2589 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2591 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2592 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2594 DEBUGOUT("NVM Read Error\n");
2597 checksum += nvm_data;
2600 if (checksum != (u16) NVM_SUM) {
2601 DEBUGOUT("NVM Checksum Invalid\n");
2602 ret_val = -E1000_ERR_NVM;
2611 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2613 * @hw: pointer to the HW structure
2614 * @offset: offset in words of the checksum protected region
2616 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2617 * up to the checksum. Then calculates the EEPROM checksum and writes the
2618 * value to the EEPROM.
2620 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2626 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2628 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2629 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2631 DEBUGOUT("NVM Read Error while updating checksum.\n");
2634 checksum += nvm_data;
2636 checksum = (u16) NVM_SUM - checksum;
2637 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2640 DEBUGOUT("NVM Write Error while updating checksum.\n");
2647 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2648 * @hw: pointer to the HW structure
2650 * Calculates the EEPROM section checksum by reading/adding each word of
2651 * the EEPROM and then verifies that the sum of the EEPROM is
2654 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2657 u16 eeprom_regions_count = 1;
2661 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2663 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2665 DEBUGOUT("NVM Read Error\n");
2669 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2670 /* if chekcsums compatibility bit is set validate checksums
2671 * for all 4 ports. */
2672 eeprom_regions_count = 4;
2675 for (j = 0; j < eeprom_regions_count; j++) {
2676 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2677 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2679 if (ret_val != E1000_SUCCESS)
2688 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2689 * @hw: pointer to the HW structure
2691 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2692 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2693 * checksum and writes the value to the EEPROM.
2695 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2701 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2703 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2705 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2709 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2710 /* set compatibility bit to validate checksums appropriately */
2711 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2712 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2715 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2720 for (j = 0; j < 4; j++) {
2721 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2722 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2732 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2733 * @hw: pointer to the HW structure
2735 * Calculates the EEPROM section checksum by reading/adding each word of
2736 * the EEPROM and then verifies that the sum of the EEPROM is
2739 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2741 s32 ret_val = E1000_SUCCESS;
2745 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2747 for (j = 0; j < 4; j++) {
2748 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2749 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2751 if (ret_val != E1000_SUCCESS)
2760 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2761 * @hw: pointer to the HW structure
2763 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2764 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2765 * checksum and writes the value to the EEPROM.
2767 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2769 s32 ret_val = E1000_SUCCESS;
2773 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2775 for (j = 0; j < 4; j++) {
2776 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2777 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2778 if (ret_val != E1000_SUCCESS)
2787 * __e1000_access_emi_reg - Read/write EMI register
2788 * @hw: pointer to the HW structure
2789 * @addr: EMI address to program
2790 * @data: pointer to value to read/write from/to the EMI address
2791 * @read: boolean flag to indicate read or write
2793 STATIC s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2794 u16 *data, bool read)
2798 DEBUGFUNC("__e1000_access_emi_reg");
2800 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2805 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2807 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2813 * e1000_read_emi_reg - Read Extended Management Interface register
2814 * @hw: pointer to the HW structure
2815 * @addr: EMI address to program
2816 * @data: value to be read from the EMI address
2818 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2820 DEBUGFUNC("e1000_read_emi_reg");
2822 return __e1000_access_emi_reg(hw, addr, data, true);
2826 * e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2827 * @hw: pointer to the HW structure
2829 * Initialize Marvell 1512 to work correctly with Avoton.
2831 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2833 struct e1000_phy_info *phy = &hw->phy;
2834 s32 ret_val = E1000_SUCCESS;
2836 DEBUGFUNC("e1000_initialize_M88E1512_phy");
2838 /* Check if this is correct PHY. */
2839 if (phy->id != M88E1512_E_PHY_ID)
2842 /* Switch to PHY page 0xFF. */
2843 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2847 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2851 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2855 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2859 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2863 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2867 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2871 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2875 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2879 /* Switch to PHY page 0xFB. */
2880 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2884 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2888 /* Switch to PHY page 0x12. */
2889 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2893 /* Change mode to SGMII-to-Copper */
2894 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2898 /* Return the PHY to page 0. */
2899 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2903 ret_val = phy->ops.commit(hw);
2905 DEBUGOUT("Error committing the PHY changes\n");
2915 * e1000_initialize_M88E1543_phy - Initialize M88E1543 PHY
2916 * @hw: pointer to the HW structure
2918 * Initialize Marvell 1543 to work correctly with Avoton.
2920 s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw)
2922 struct e1000_phy_info *phy = &hw->phy;
2923 s32 ret_val = E1000_SUCCESS;
2925 DEBUGFUNC("e1000_initialize_M88E1543_phy");
2927 /* Check if this is correct PHY. */
2928 if (phy->id != M88E1543_E_PHY_ID)
2931 /* Switch to PHY page 0xFF. */
2932 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2936 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2940 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2944 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2948 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2952 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2956 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2960 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2964 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2968 /* Switch to PHY page 0xFB. */
2969 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2973 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);
2977 /* Switch to PHY page 0x12. */
2978 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2982 /* Change mode to SGMII-to-Copper */
2983 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2987 /* Switch to PHY page 1. */
2988 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2992 /* Change mode to 1000BASE-X/SGMII and autoneg enable; reset */
2993 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2997 /* Return the PHY to page 0. */
2998 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
3002 ret_val = phy->ops.commit(hw);
3004 DEBUGOUT("Error committing the PHY changes\n");
3014 * e1000_set_eee_i350 - Enable/disable EEE support
3015 * @hw: pointer to the HW structure
3016 * @adv1g: boolean flag enabling 1G EEE advertisement
3017 * @adv100m: boolean flag enabling 100M EEE advertisement
3019 * Enable/disable EEE based on setting in dev_spec structure.
3022 s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
3026 DEBUGFUNC("e1000_set_eee_i350");
3028 if ((hw->mac.type < e1000_i350) ||
3029 (hw->phy.media_type != e1000_media_type_copper))
3031 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
3032 eeer = E1000_READ_REG(hw, E1000_EEER);
3034 /* enable or disable per user setting */
3035 if (!(hw->dev_spec._82575.eee_disable)) {
3036 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
3039 ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
3041 ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
3044 ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
3046 ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
3048 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
3051 /* This bit should not be set in normal operation. */
3052 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
3053 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
3055 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
3056 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
3059 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
3060 E1000_WRITE_REG(hw, E1000_EEER, eeer);
3061 E1000_READ_REG(hw, E1000_IPCNFG);
3062 E1000_READ_REG(hw, E1000_EEER);
3065 return E1000_SUCCESS;
3069 * e1000_set_eee_i354 - Enable/disable EEE support
3070 * @hw: pointer to the HW structure
3071 * @adv1g: boolean flag enabling 1G EEE advertisement
3072 * @adv100m: boolean flag enabling 100M EEE advertisement
3074 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
3077 s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
3079 struct e1000_phy_info *phy = &hw->phy;
3080 s32 ret_val = E1000_SUCCESS;
3083 DEBUGFUNC("e1000_set_eee_i354");
3085 if ((hw->phy.media_type != e1000_media_type_copper) ||
3086 ((phy->id != M88E1543_E_PHY_ID) &&
3087 (phy->id != M88E1512_E_PHY_ID)))
3090 if (!hw->dev_spec._82575.eee_disable) {
3091 /* Switch to PHY page 18. */
3092 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
3096 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
3101 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
3102 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
3107 /* Return the PHY to page 0. */
3108 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
3112 /* Turn on EEE advertisement. */
3113 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3114 E1000_EEE_ADV_DEV_I354,
3120 phy_data |= E1000_EEE_ADV_100_SUPPORTED;
3122 phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
3125 phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
3127 phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
3129 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3130 E1000_EEE_ADV_DEV_I354,
3133 /* Turn off EEE advertisement. */
3134 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3135 E1000_EEE_ADV_DEV_I354,
3140 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
3141 E1000_EEE_ADV_1000_SUPPORTED);
3142 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3143 E1000_EEE_ADV_DEV_I354,
3152 * e1000_get_eee_status_i354 - Get EEE status
3153 * @hw: pointer to the HW structure
3154 * @status: EEE status
3156 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
3159 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
3161 struct e1000_phy_info *phy = &hw->phy;
3162 s32 ret_val = E1000_SUCCESS;
3165 DEBUGFUNC("e1000_get_eee_status_i354");
3167 /* Check if EEE is supported on this device. */
3168 if ((hw->phy.media_type != e1000_media_type_copper) ||
3169 ((phy->id != M88E1543_E_PHY_ID) &&
3170 (phy->id != M88E1512_E_PHY_ID)))
3173 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
3174 E1000_PCS_STATUS_DEV_I354,
3179 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
3180 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
3186 /* Due to a hw errata, if the host tries to configure the VFTA register
3187 * while performing queries from the BMC or DMA, then the VFTA in some
3188 * cases won't be written.
3192 * e1000_clear_vfta_i350 - Clear VLAN filter table
3193 * @hw: pointer to the HW structure
3195 * Clears the register array which contains the VLAN filter table by
3196 * setting all the values to 0.
3198 void e1000_clear_vfta_i350(struct e1000_hw *hw)
3203 DEBUGFUNC("e1000_clear_vfta_350");
3205 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
3206 for (i = 0; i < 10; i++)
3207 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
3209 E1000_WRITE_FLUSH(hw);
3214 * e1000_write_vfta_i350 - Write value to VLAN filter table
3215 * @hw: pointer to the HW structure
3216 * @offset: register offset in VLAN filter table
3217 * @value: register value written to VLAN filter table
3219 * Writes value at the given offset in the register array which stores
3220 * the VLAN filter table.
3222 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
3226 DEBUGFUNC("e1000_write_vfta_350");
3228 for (i = 0; i < 10; i++)
3229 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
3231 E1000_WRITE_FLUSH(hw);
3236 * e1000_set_i2c_bb - Enable I2C bit-bang
3237 * @hw: pointer to the HW structure
3239 * Enable I2C bit-bang interface
3242 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3244 s32 ret_val = E1000_SUCCESS;
3245 u32 ctrl_ext, i2cparams;
3247 DEBUGFUNC("e1000_set_i2c_bb");
3249 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3250 ctrl_ext |= E1000_CTRL_I2C_ENA;
3251 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3252 E1000_WRITE_FLUSH(hw);
3254 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3255 i2cparams |= E1000_I2CBB_EN;
3256 i2cparams |= E1000_I2C_DATA_OE_N;
3257 i2cparams |= E1000_I2C_CLK_OE_N;
3258 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3259 E1000_WRITE_FLUSH(hw);
3265 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3266 * @hw: pointer to hardware structure
3267 * @byte_offset: byte offset to read
3268 * @dev_addr: device address
3271 * Performs byte read operation over I2C interface at
3272 * a specified device address.
3274 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3275 u8 dev_addr, u8 *data)
3277 s32 status = E1000_SUCCESS;
3284 DEBUGFUNC("e1000_read_i2c_byte_generic");
3286 swfw_mask = E1000_SWFW_PHY0_SM;
3289 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3291 status = E1000_ERR_SWFW_SYNC;
3295 e1000_i2c_start(hw);
3297 /* Device Address and write indication */
3298 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3299 if (status != E1000_SUCCESS)
3302 status = e1000_get_i2c_ack(hw);
3303 if (status != E1000_SUCCESS)
3306 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3307 if (status != E1000_SUCCESS)
3310 status = e1000_get_i2c_ack(hw);
3311 if (status != E1000_SUCCESS)
3314 e1000_i2c_start(hw);
3316 /* Device Address and read indication */
3317 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3318 if (status != E1000_SUCCESS)
3321 status = e1000_get_i2c_ack(hw);
3322 if (status != E1000_SUCCESS)
3325 status = e1000_clock_in_i2c_byte(hw, data);
3326 if (status != E1000_SUCCESS)
3329 status = e1000_clock_out_i2c_bit(hw, nack);
3330 if (status != E1000_SUCCESS)
3337 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3339 e1000_i2c_bus_clear(hw);
3341 if (retry < max_retry)
3342 DEBUGOUT("I2C byte read error - Retrying.\n");
3344 DEBUGOUT("I2C byte read error.\n");
3346 } while (retry < max_retry);
3348 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3356 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3357 * @hw: pointer to hardware structure
3358 * @byte_offset: byte offset to write
3359 * @dev_addr: device address
3360 * @data: value to write
3362 * Performs byte write operation over I2C interface at
3363 * a specified device address.
3365 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3366 u8 dev_addr, u8 data)
3368 s32 status = E1000_SUCCESS;
3373 DEBUGFUNC("e1000_write_i2c_byte_generic");
3375 swfw_mask = E1000_SWFW_PHY0_SM;
3377 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3378 status = E1000_ERR_SWFW_SYNC;
3379 goto write_byte_out;
3383 e1000_i2c_start(hw);
3385 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3386 if (status != E1000_SUCCESS)
3389 status = e1000_get_i2c_ack(hw);
3390 if (status != E1000_SUCCESS)
3393 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3394 if (status != E1000_SUCCESS)
3397 status = e1000_get_i2c_ack(hw);
3398 if (status != E1000_SUCCESS)
3401 status = e1000_clock_out_i2c_byte(hw, data);
3402 if (status != E1000_SUCCESS)
3405 status = e1000_get_i2c_ack(hw);
3406 if (status != E1000_SUCCESS)
3413 e1000_i2c_bus_clear(hw);
3415 if (retry < max_retry)
3416 DEBUGOUT("I2C byte write error - Retrying.\n");
3418 DEBUGOUT("I2C byte write error.\n");
3419 } while (retry < max_retry);
3421 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3429 * e1000_i2c_start - Sets I2C start condition
3430 * @hw: pointer to hardware structure
3432 * Sets I2C start condition (High -> Low on SDA while SCL is High)
3434 STATIC void e1000_i2c_start(struct e1000_hw *hw)
3436 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3438 DEBUGFUNC("e1000_i2c_start");
3440 /* Start condition must begin with data and clock high */
3441 e1000_set_i2c_data(hw, &i2cctl, 1);
3442 e1000_raise_i2c_clk(hw, &i2cctl);
3444 /* Setup time for start condition (4.7us) */
3445 usec_delay(E1000_I2C_T_SU_STA);
3447 e1000_set_i2c_data(hw, &i2cctl, 0);
3449 /* Hold time for start condition (4us) */
3450 usec_delay(E1000_I2C_T_HD_STA);
3452 e1000_lower_i2c_clk(hw, &i2cctl);
3454 /* Minimum low period of clock is 4.7 us */
3455 usec_delay(E1000_I2C_T_LOW);
3460 * e1000_i2c_stop - Sets I2C stop condition
3461 * @hw: pointer to hardware structure
3463 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
3465 STATIC void e1000_i2c_stop(struct e1000_hw *hw)
3467 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3469 DEBUGFUNC("e1000_i2c_stop");
3471 /* Stop condition must begin with data low and clock high */
3472 e1000_set_i2c_data(hw, &i2cctl, 0);
3473 e1000_raise_i2c_clk(hw, &i2cctl);
3475 /* Setup time for stop condition (4us) */
3476 usec_delay(E1000_I2C_T_SU_STO);
3478 e1000_set_i2c_data(hw, &i2cctl, 1);
3480 /* bus free time between stop and start (4.7us)*/
3481 usec_delay(E1000_I2C_T_BUF);
3485 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3486 * @hw: pointer to hardware structure
3487 * @data: data byte to clock in
3489 * Clocks in one byte data via I2C data/clock
3491 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3496 DEBUGFUNC("e1000_clock_in_i2c_byte");
3499 for (i = 7; i >= 0; i--) {
3500 e1000_clock_in_i2c_bit(hw, &bit);
3504 return E1000_SUCCESS;
3508 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3509 * @hw: pointer to hardware structure
3510 * @data: data byte clocked out
3512 * Clocks out one byte data via I2C data/clock
3514 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3516 s32 status = E1000_SUCCESS;
3521 DEBUGFUNC("e1000_clock_out_i2c_byte");
3523 for (i = 7; i >= 0; i--) {
3524 bit = (data >> i) & 0x1;
3525 status = e1000_clock_out_i2c_bit(hw, bit);
3527 if (status != E1000_SUCCESS)
3531 /* Release SDA line (set high) */
3532 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3534 i2cctl |= E1000_I2C_DATA_OE_N;
3535 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3536 E1000_WRITE_FLUSH(hw);
3542 * e1000_get_i2c_ack - Polls for I2C ACK
3543 * @hw: pointer to hardware structure
3545 * Clocks in/out one bit via I2C data/clock
3547 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3549 s32 status = E1000_SUCCESS;
3551 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3555 DEBUGFUNC("e1000_get_i2c_ack");
3557 e1000_raise_i2c_clk(hw, &i2cctl);
3559 /* Minimum high period of clock is 4us */
3560 usec_delay(E1000_I2C_T_HIGH);
3562 /* Wait until SCL returns high */
3563 for (i = 0; i < timeout; i++) {
3565 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3566 if (i2cctl & E1000_I2C_CLK_IN)
3569 if (!(i2cctl & E1000_I2C_CLK_IN))
3570 return E1000_ERR_I2C;
3572 ack = e1000_get_i2c_data(&i2cctl);
3574 DEBUGOUT("I2C ack was not received.\n");
3575 status = E1000_ERR_I2C;
3578 e1000_lower_i2c_clk(hw, &i2cctl);
3580 /* Minimum low period of clock is 4.7 us */
3581 usec_delay(E1000_I2C_T_LOW);
3587 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3588 * @hw: pointer to hardware structure
3589 * @data: read data value
3591 * Clocks in one bit via I2C data/clock
3593 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3595 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3597 DEBUGFUNC("e1000_clock_in_i2c_bit");
3599 e1000_raise_i2c_clk(hw, &i2cctl);
3601 /* Minimum high period of clock is 4us */
3602 usec_delay(E1000_I2C_T_HIGH);
3604 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3605 *data = e1000_get_i2c_data(&i2cctl);
3607 e1000_lower_i2c_clk(hw, &i2cctl);
3609 /* Minimum low period of clock is 4.7 us */
3610 usec_delay(E1000_I2C_T_LOW);
3612 return E1000_SUCCESS;
3616 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3617 * @hw: pointer to hardware structure
3618 * @data: data value to write
3620 * Clocks out one bit via I2C data/clock
3622 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3625 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3627 DEBUGFUNC("e1000_clock_out_i2c_bit");
3629 status = e1000_set_i2c_data(hw, &i2cctl, data);
3630 if (status == E1000_SUCCESS) {
3631 e1000_raise_i2c_clk(hw, &i2cctl);
3633 /* Minimum high period of clock is 4us */
3634 usec_delay(E1000_I2C_T_HIGH);
3636 e1000_lower_i2c_clk(hw, &i2cctl);
3638 /* Minimum low period of clock is 4.7 us.
3639 * This also takes care of the data hold time.
3641 usec_delay(E1000_I2C_T_LOW);
3643 status = E1000_ERR_I2C;
3644 DEBUGOUT1("I2C data was not set to %X\n", data);
3650 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3651 * @hw: pointer to hardware structure
3652 * @i2cctl: Current value of I2CCTL register
3654 * Raises the I2C clock line '0'->'1'
3656 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3658 DEBUGFUNC("e1000_raise_i2c_clk");
3660 *i2cctl |= E1000_I2C_CLK_OUT;
3661 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3662 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3663 E1000_WRITE_FLUSH(hw);
3665 /* SCL rise time (1000ns) */
3666 usec_delay(E1000_I2C_T_RISE);
3670 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3671 * @hw: pointer to hardware structure
3672 * @i2cctl: Current value of I2CCTL register
3674 * Lowers the I2C clock line '1'->'0'
3676 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3679 DEBUGFUNC("e1000_lower_i2c_clk");
3681 *i2cctl &= ~E1000_I2C_CLK_OUT;
3682 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3683 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3684 E1000_WRITE_FLUSH(hw);
3686 /* SCL fall time (300ns) */
3687 usec_delay(E1000_I2C_T_FALL);
3691 * e1000_set_i2c_data - Sets the I2C data bit
3692 * @hw: pointer to hardware structure
3693 * @i2cctl: Current value of I2CCTL register
3694 * @data: I2C data value (0 or 1) to set
3696 * Sets the I2C data bit
3698 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3700 s32 status = E1000_SUCCESS;
3702 DEBUGFUNC("e1000_set_i2c_data");
3705 *i2cctl |= E1000_I2C_DATA_OUT;
3707 *i2cctl &= ~E1000_I2C_DATA_OUT;
3709 *i2cctl &= ~E1000_I2C_DATA_OE_N;
3710 *i2cctl |= E1000_I2C_CLK_OE_N;
3711 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3712 E1000_WRITE_FLUSH(hw);
3714 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3715 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3717 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3718 if (data != e1000_get_i2c_data(i2cctl)) {
3719 status = E1000_ERR_I2C;
3720 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3727 * e1000_get_i2c_data - Reads the I2C SDA data bit
3728 * @hw: pointer to hardware structure
3729 * @i2cctl: Current value of I2CCTL register
3731 * Returns the I2C data bit value
3733 STATIC bool e1000_get_i2c_data(u32 *i2cctl)
3737 DEBUGFUNC("e1000_get_i2c_data");
3739 if (*i2cctl & E1000_I2C_DATA_IN)
3748 * e1000_i2c_bus_clear - Clears the I2C bus
3749 * @hw: pointer to hardware structure
3751 * Clears the I2C bus by sending nine clock pulses.
3752 * Used when data line is stuck low.
3754 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3756 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3759 DEBUGFUNC("e1000_i2c_bus_clear");
3761 e1000_i2c_start(hw);
3763 e1000_set_i2c_data(hw, &i2cctl, 1);
3765 for (i = 0; i < 9; i++) {
3766 e1000_raise_i2c_clk(hw, &i2cctl);
3768 /* Min high period of clock is 4us */
3769 usec_delay(E1000_I2C_T_HIGH);
3771 e1000_lower_i2c_clk(hw, &i2cctl);
3773 /* Min low period of clock is 4.7us*/
3774 usec_delay(E1000_I2C_T_LOW);
3777 e1000_i2c_start(hw);
3779 /* Put the i2c bus back to default state */