1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
37 #include "e1000_osdep.h"
38 #include "e1000_regs.h"
39 #include "e1000_defines.h"
43 #define E1000_DEV_ID_82542 0x1000
44 #define E1000_DEV_ID_82543GC_FIBER 0x1001
45 #define E1000_DEV_ID_82543GC_COPPER 0x1004
46 #define E1000_DEV_ID_82544EI_COPPER 0x1008
47 #define E1000_DEV_ID_82544EI_FIBER 0x1009
48 #define E1000_DEV_ID_82544GC_COPPER 0x100C
49 #define E1000_DEV_ID_82544GC_LOM 0x100D
50 #define E1000_DEV_ID_82540EM 0x100E
51 #define E1000_DEV_ID_82540EM_LOM 0x1015
52 #define E1000_DEV_ID_82540EP_LOM 0x1016
53 #define E1000_DEV_ID_82540EP 0x1017
54 #define E1000_DEV_ID_82540EP_LP 0x101E
55 #define E1000_DEV_ID_82545EM_COPPER 0x100F
56 #define E1000_DEV_ID_82545EM_FIBER 0x1011
57 #define E1000_DEV_ID_82545GM_COPPER 0x1026
58 #define E1000_DEV_ID_82545GM_FIBER 0x1027
59 #define E1000_DEV_ID_82545GM_SERDES 0x1028
60 #define E1000_DEV_ID_82546EB_COPPER 0x1010
61 #define E1000_DEV_ID_82546EB_FIBER 0x1012
62 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
63 #define E1000_DEV_ID_82546GB_COPPER 0x1079
64 #define E1000_DEV_ID_82546GB_FIBER 0x107A
65 #define E1000_DEV_ID_82546GB_SERDES 0x107B
66 #define E1000_DEV_ID_82546GB_PCIE 0x108A
67 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
68 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
69 #define E1000_DEV_ID_82541EI 0x1013
70 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
71 #define E1000_DEV_ID_82541ER_LOM 0x1014
72 #define E1000_DEV_ID_82541ER 0x1078
73 #define E1000_DEV_ID_82541GI 0x1076
74 #define E1000_DEV_ID_82541GI_LF 0x107C
75 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
76 #define E1000_DEV_ID_82547EI 0x1019
77 #define E1000_DEV_ID_82547EI_MOBILE 0x101A
78 #define E1000_DEV_ID_82547GI 0x1075
79 #define E1000_DEV_ID_82571EB_COPPER 0x105E
80 #define E1000_DEV_ID_82571EB_FIBER 0x105F
81 #define E1000_DEV_ID_82571EB_SERDES 0x1060
82 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
83 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
84 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
85 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
86 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
87 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
88 #define E1000_DEV_ID_82572EI_COPPER 0x107D
89 #define E1000_DEV_ID_82572EI_FIBER 0x107E
90 #define E1000_DEV_ID_82572EI_SERDES 0x107F
91 #define E1000_DEV_ID_82572EI 0x10B9
92 #define E1000_DEV_ID_82573E 0x108B
93 #define E1000_DEV_ID_82573E_IAMT 0x108C
94 #define E1000_DEV_ID_82573L 0x109A
95 #define E1000_DEV_ID_82574L 0x10D3
96 #define E1000_DEV_ID_82574LA 0x10F6
97 #define E1000_DEV_ID_82583V 0x150C
98 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
99 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
100 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
101 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
102 #define E1000_DEV_ID_ICH8_82567V_3 0x1501
103 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
104 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
105 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
106 #define E1000_DEV_ID_ICH8_IFE 0x104C
107 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
108 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
109 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
110 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
111 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
112 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
113 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
114 #define E1000_DEV_ID_ICH9_BM 0x10E5
115 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
116 #define E1000_DEV_ID_ICH9_IFE 0x10C0
117 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
118 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
119 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
120 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
121 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
122 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
123 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
124 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525
125 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
126 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
127 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
128 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
129 #define E1000_DEV_ID_PCH2_LV_LM 0x1502
130 #define E1000_DEV_ID_PCH2_LV_V 0x1503
131 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
132 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
133 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
134 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
135 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0
136 #define E1000_DEV_ID_PCH_I218_V2 0x15A1
137 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
138 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
139 #define E1000_DEV_ID_82576 0x10C9
140 #define E1000_DEV_ID_82576_FIBER 0x10E6
141 #define E1000_DEV_ID_82576_SERDES 0x10E7
142 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
143 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
144 #define E1000_DEV_ID_82576_NS 0x150A
145 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
146 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
147 #define E1000_DEV_ID_82576_VF 0x10CA
148 #define E1000_DEV_ID_82576_VF_HV 0x152D
149 #define E1000_DEV_ID_I350_VF 0x1520
150 #define E1000_DEV_ID_I350_VF_HV 0x152F
151 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
152 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
153 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
154 #define E1000_DEV_ID_82580_COPPER 0x150E
155 #define E1000_DEV_ID_82580_FIBER 0x150F
156 #define E1000_DEV_ID_82580_SERDES 0x1510
157 #define E1000_DEV_ID_82580_SGMII 0x1511
158 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
159 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
160 #define E1000_DEV_ID_I350_COPPER 0x1521
161 #define E1000_DEV_ID_I350_FIBER 0x1522
162 #define E1000_DEV_ID_I350_SERDES 0x1523
163 #define E1000_DEV_ID_I350_SGMII 0x1524
164 #define E1000_DEV_ID_I350_DA4 0x1546
165 #define E1000_DEV_ID_I210_COPPER 0x1533
166 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534
167 #define E1000_DEV_ID_I210_COPPER_IT 0x1535
168 #define E1000_DEV_ID_I210_FIBER 0x1536
169 #define E1000_DEV_ID_I210_SERDES 0x1537
170 #define E1000_DEV_ID_I210_SGMII 0x1538
171 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B
172 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C
173 #define E1000_DEV_ID_I211_COPPER 0x1539
174 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
175 #define E1000_DEV_ID_I354_SGMII 0x1F41
176 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45
177 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
178 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
179 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
180 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440
182 #define E1000_REVISION_0 0
183 #define E1000_REVISION_1 1
184 #define E1000_REVISION_2 2
185 #define E1000_REVISION_3 3
186 #define E1000_REVISION_4 4
188 #define E1000_FUNC_0 0
189 #define E1000_FUNC_1 1
190 #define E1000_FUNC_2 2
191 #define E1000_FUNC_3 3
193 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
194 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
195 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
196 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
198 enum e1000_mac_type {
233 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
236 enum e1000_media_type {
237 e1000_media_type_unknown = 0,
238 e1000_media_type_copper = 1,
239 e1000_media_type_fiber = 2,
240 e1000_media_type_internal_serdes = 3,
241 e1000_num_media_types
244 enum e1000_nvm_type {
245 e1000_nvm_unknown = 0,
247 e1000_nvm_eeprom_spi,
248 e1000_nvm_eeprom_microwire,
254 enum e1000_nvm_override {
255 e1000_nvm_override_none = 0,
256 e1000_nvm_override_spi_small,
257 e1000_nvm_override_spi_large,
258 e1000_nvm_override_microwire_small,
259 e1000_nvm_override_microwire_large
262 enum e1000_phy_type {
263 e1000_phy_unknown = 0,
281 enum e1000_bus_type {
282 e1000_bus_type_unknown = 0,
285 e1000_bus_type_pci_express,
286 e1000_bus_type_reserved
289 enum e1000_bus_speed {
290 e1000_bus_speed_unknown = 0,
296 e1000_bus_speed_2500,
297 e1000_bus_speed_5000,
298 e1000_bus_speed_reserved
301 enum e1000_bus_width {
302 e1000_bus_width_unknown = 0,
303 e1000_bus_width_pcie_x1,
304 e1000_bus_width_pcie_x2,
305 e1000_bus_width_pcie_x4 = 4,
306 e1000_bus_width_pcie_x8 = 8,
309 e1000_bus_width_reserved
312 enum e1000_1000t_rx_status {
313 e1000_1000t_rx_status_not_ok = 0,
314 e1000_1000t_rx_status_ok,
315 e1000_1000t_rx_status_undefined = 0xFF
318 enum e1000_rev_polarity {
319 e1000_rev_polarity_normal = 0,
320 e1000_rev_polarity_reversed,
321 e1000_rev_polarity_undefined = 0xFF
329 e1000_fc_default = 0xFF
332 enum e1000_ffe_config {
333 e1000_ffe_config_enabled = 0,
334 e1000_ffe_config_active,
335 e1000_ffe_config_blocked
338 enum e1000_dsp_config {
339 e1000_dsp_config_disabled = 0,
340 e1000_dsp_config_enabled,
341 e1000_dsp_config_activated,
342 e1000_dsp_config_undefined = 0xFF
346 e1000_ms_hw_default = 0,
347 e1000_ms_force_master,
348 e1000_ms_force_slave,
352 enum e1000_smart_speed {
353 e1000_smart_speed_default = 0,
354 e1000_smart_speed_on,
355 e1000_smart_speed_off
358 enum e1000_serdes_link_state {
359 e1000_serdes_link_down = 0,
360 e1000_serdes_link_autoneg_progress,
361 e1000_serdes_link_autoneg_complete,
362 e1000_serdes_link_forced_up
368 /* Receive Descriptor */
369 struct e1000_rx_desc {
370 __le64 buffer_addr; /* Address of the descriptor's data buffer */
371 __le16 length; /* Length of data DMAed into data buffer */
372 __le16 csum; /* Packet checksum */
373 u8 status; /* Descriptor status */
374 u8 errors; /* Descriptor Errors */
378 /* Receive Descriptor - Extended */
379 union e1000_rx_desc_extended {
386 __le32 mrq; /* Multiple Rx Queues */
388 __le32 rss; /* RSS Hash */
390 __le16 ip_id; /* IP id */
391 __le16 csum; /* Packet Checksum */
396 __le32 status_error; /* ext status/error */
398 __le16 vlan; /* VLAN tag */
400 } wb; /* writeback */
403 #define MAX_PS_BUFFERS 4
405 /* Number of packet split data buffers (not including the header buffer) */
406 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
408 /* Receive Descriptor - Packet Split */
409 union e1000_rx_desc_packet_split {
411 /* one buffer for protocol header(s), three data buffers */
412 __le64 buffer_addr[MAX_PS_BUFFERS];
416 __le32 mrq; /* Multiple Rx Queues */
418 __le32 rss; /* RSS Hash */
420 __le16 ip_id; /* IP id */
421 __le16 csum; /* Packet Checksum */
426 __le32 status_error; /* ext status/error */
427 __le16 length0; /* length of buffer 0 */
428 __le16 vlan; /* VLAN tag */
431 __le16 header_status;
432 /* length of buffers 1-3 */
433 __le16 length[PS_PAGE_BUFFERS];
436 } wb; /* writeback */
439 /* Transmit Descriptor */
440 struct e1000_tx_desc {
441 __le64 buffer_addr; /* Address of the descriptor's data buffer */
445 __le16 length; /* Data buffer length */
446 u8 cso; /* Checksum offset */
447 u8 cmd; /* Descriptor control */
453 u8 status; /* Descriptor status */
454 u8 css; /* Checksum start */
460 /* Offload Context Descriptor */
461 struct e1000_context_desc {
465 u8 ipcss; /* IP checksum start */
466 u8 ipcso; /* IP checksum offset */
467 __le16 ipcse; /* IP checksum end */
473 u8 tucss; /* TCP checksum start */
474 u8 tucso; /* TCP checksum offset */
475 __le16 tucse; /* TCP checksum end */
478 __le32 cmd_and_length;
482 u8 status; /* Descriptor status */
483 u8 hdr_len; /* Header length */
484 __le16 mss; /* Maximum segment size */
489 /* Offload data descriptor */
490 struct e1000_data_desc {
491 __le64 buffer_addr; /* Address of the descriptor's buffer address */
495 __le16 length; /* Data buffer length */
503 u8 status; /* Descriptor status */
504 u8 popts; /* Packet Options */
510 /* Statistics counters collected by the MAC */
511 struct e1000_hw_stats {
594 struct e1000_vf_stats {
626 struct e1000_phy_stats {
631 struct e1000_host_mng_dhcp_cookie {
642 /* Host Interface "Rev 1" */
643 struct e1000_host_command_header {
650 #define E1000_HI_MAX_DATA_LENGTH 252
651 struct e1000_host_command_info {
652 struct e1000_host_command_header command_header;
653 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
656 /* Host Interface "Rev 2" */
657 struct e1000_host_mng_command_header {
665 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
666 struct e1000_host_mng_command_info {
667 struct e1000_host_mng_command_header command_header;
668 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
671 #include "e1000_mac.h"
672 #include "e1000_phy.h"
673 #include "e1000_nvm.h"
674 #include "e1000_manage.h"
675 #include "e1000_mbx.h"
677 /* Function pointers for the MAC. */
678 struct e1000_mac_operations {
679 s32 (*init_params)(struct e1000_hw *);
680 s32 (*id_led_init)(struct e1000_hw *);
681 s32 (*blink_led)(struct e1000_hw *);
682 bool (*check_mng_mode)(struct e1000_hw *);
683 s32 (*check_for_link)(struct e1000_hw *);
684 s32 (*cleanup_led)(struct e1000_hw *);
685 void (*clear_hw_cntrs)(struct e1000_hw *);
686 void (*clear_vfta)(struct e1000_hw *);
687 s32 (*get_bus_info)(struct e1000_hw *);
688 void (*set_lan_id)(struct e1000_hw *);
689 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
690 s32 (*led_on)(struct e1000_hw *);
691 s32 (*led_off)(struct e1000_hw *);
692 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
693 s32 (*reset_hw)(struct e1000_hw *);
694 s32 (*init_hw)(struct e1000_hw *);
695 void (*shutdown_serdes)(struct e1000_hw *);
696 void (*power_up_serdes)(struct e1000_hw *);
697 s32 (*setup_link)(struct e1000_hw *);
698 s32 (*setup_physical_interface)(struct e1000_hw *);
699 s32 (*setup_led)(struct e1000_hw *);
700 void (*write_vfta)(struct e1000_hw *, u32, u32);
701 void (*config_collision_dist)(struct e1000_hw *);
702 int (*rar_set)(struct e1000_hw *, u8*, u32);
703 s32 (*read_mac_addr)(struct e1000_hw *);
704 s32 (*validate_mdi_setting)(struct e1000_hw *);
705 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
706 void (*release_swfw_sync)(struct e1000_hw *, u16);
709 /* When to use various PHY register access functions:
712 * Function Does Does When to use
713 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
714 * X_reg L,P,A n/a for simple PHY reg accesses
715 * X_reg_locked P,A L for multiple accesses of different regs
717 * X_reg_page A L,P for multiple accesses of different regs
720 * Where X=[read|write], L=locking, P=sets page, A=register access
723 struct e1000_phy_operations {
724 s32 (*init_params)(struct e1000_hw *);
725 s32 (*acquire)(struct e1000_hw *);
726 s32 (*cfg_on_link_up)(struct e1000_hw *);
727 s32 (*check_polarity)(struct e1000_hw *);
728 s32 (*check_reset_block)(struct e1000_hw *);
729 s32 (*commit)(struct e1000_hw *);
730 s32 (*force_speed_duplex)(struct e1000_hw *);
731 s32 (*get_cfg_done)(struct e1000_hw *hw);
732 s32 (*get_cable_length)(struct e1000_hw *);
733 s32 (*get_info)(struct e1000_hw *);
734 s32 (*set_page)(struct e1000_hw *, u16);
735 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
736 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
737 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
738 void (*release)(struct e1000_hw *);
739 s32 (*reset)(struct e1000_hw *);
740 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
741 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
742 s32 (*write_reg)(struct e1000_hw *, u32, u16);
743 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
744 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
745 void (*power_up)(struct e1000_hw *);
746 void (*power_down)(struct e1000_hw *);
747 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
748 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
751 /* Function pointers for the NVM. */
752 struct e1000_nvm_operations {
753 s32 (*init_params)(struct e1000_hw *);
754 s32 (*acquire)(struct e1000_hw *);
755 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
756 void (*release)(struct e1000_hw *);
757 void (*reload)(struct e1000_hw *);
758 s32 (*update)(struct e1000_hw *);
759 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
760 s32 (*validate)(struct e1000_hw *);
761 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
764 struct e1000_mac_info {
765 struct e1000_mac_operations ops;
766 u8 addr[ETH_ADDR_LEN];
767 u8 perm_addr[ETH_ADDR_LEN];
769 enum e1000_mac_type type;
787 /* Maximum size of the MTA register table in all supported adapters */
788 #define MAX_MTA_REG 128
789 u32 mta_shadow[MAX_MTA_REG];
792 u8 forced_speed_duplex;
796 bool arc_subsystem_valid;
797 bool asf_firmware_present;
800 bool get_link_status;
802 bool report_tx_early;
803 enum e1000_serdes_link_state serdes_link_state;
804 bool serdes_has_link;
805 bool tx_pkt_filtering;
808 struct e1000_phy_info {
809 struct e1000_phy_operations ops;
810 enum e1000_phy_type type;
812 enum e1000_1000t_rx_status local_rx;
813 enum e1000_1000t_rx_status remote_rx;
814 enum e1000_ms_type ms_type;
815 enum e1000_ms_type original_ms_type;
816 enum e1000_rev_polarity cable_polarity;
817 enum e1000_smart_speed smart_speed;
821 u32 reset_delay_us; /* in usec */
824 enum e1000_media_type media_type;
826 u16 autoneg_advertised;
829 u16 max_cable_length;
830 u16 min_cable_length;
834 bool disable_polarity_correction;
836 bool polarity_correction;
837 bool speed_downgraded;
838 bool autoneg_wait_to_complete;
841 struct e1000_nvm_info {
842 struct e1000_nvm_operations ops;
843 enum e1000_nvm_type type;
844 enum e1000_nvm_override override;
856 struct e1000_bus_info {
857 enum e1000_bus_type type;
858 enum e1000_bus_speed speed;
859 enum e1000_bus_width width;
865 struct e1000_fc_info {
866 u32 high_water; /* Flow control high-water mark */
867 u32 low_water; /* Flow control low-water mark */
868 u16 pause_time; /* Flow control pause timer */
869 u16 refresh_time; /* Flow control refresh timer */
870 bool send_xon; /* Flow control send XON */
871 bool strict_ieee; /* Strict IEEE mode */
872 enum e1000_fc_mode current_mode; /* FC mode in effect */
873 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
876 struct e1000_mbx_operations {
877 s32 (*init_params)(struct e1000_hw *hw);
878 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
879 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
880 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
881 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
882 s32 (*check_for_msg)(struct e1000_hw *, u16);
883 s32 (*check_for_ack)(struct e1000_hw *, u16);
884 s32 (*check_for_rst)(struct e1000_hw *, u16);
887 struct e1000_mbx_stats {
896 struct e1000_mbx_info {
897 struct e1000_mbx_operations ops;
898 struct e1000_mbx_stats stats;
904 struct e1000_dev_spec_82541 {
905 enum e1000_dsp_config dsp_config;
906 enum e1000_ffe_config ffe_config;
908 bool phy_init_script;
911 struct e1000_dev_spec_82542 {
915 struct e1000_dev_spec_82543 {
916 u32 tbi_compatibility;
918 bool init_phy_disabled;
921 struct e1000_dev_spec_82571 {
924 E1000_MUTEX swflag_mutex;
927 struct e1000_dev_spec_80003es2lan {
931 struct e1000_shadow_ram {
936 #define E1000_SHADOW_RAM_WORDS 2048
939 /* I218 PHY Ultra Low Power (ULP) states */
940 enum e1000_ulp_state {
941 e1000_ulp_state_unknown,
946 #endif /* ULP_SUPPORT */
947 struct e1000_dev_spec_ich8lan {
948 bool kmrn_lock_loss_workaround_enabled;
949 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
950 E1000_MUTEX nvm_mutex;
951 E1000_MUTEX swflag_mutex;
956 enum e1000_ulp_state ulp_state;
957 #endif /* NAHUM6LP_HW && ULP_SUPPORT */
963 struct e1000_dev_spec_82575 {
965 bool global_device_reset;
968 bool clear_semaphore_once;
970 struct sfp_e1000_flags eth_flags;
975 struct e1000_dev_spec_vf {
985 unsigned long io_base;
987 struct e1000_mac_info mac;
988 struct e1000_fc_info fc;
989 struct e1000_phy_info phy;
990 struct e1000_nvm_info nvm;
991 struct e1000_bus_info bus;
992 struct e1000_mbx_info mbx;
993 struct e1000_host_mng_dhcp_cookie mng_cookie;
996 struct e1000_dev_spec_82541 _82541;
997 struct e1000_dev_spec_82542 _82542;
998 struct e1000_dev_spec_82543 _82543;
999 struct e1000_dev_spec_82571 _82571;
1000 struct e1000_dev_spec_80003es2lan _80003es2lan;
1001 struct e1000_dev_spec_ich8lan ich8lan;
1002 struct e1000_dev_spec_82575 _82575;
1003 struct e1000_dev_spec_vf vf;
1007 u16 subsystem_vendor_id;
1008 u16 subsystem_device_id;
1014 #include "e1000_82541.h"
1015 #include "e1000_82543.h"
1016 #include "e1000_82571.h"
1017 #include "e1000_80003es2lan.h"
1018 #include "e1000_ich8lan.h"
1019 #include "e1000_82575.h"
1020 #include "e1000_i210.h"
1022 /* These functions must be implemented by drivers */
1023 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1024 void e1000_pci_set_mwi(struct e1000_hw *hw);
1025 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1026 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1027 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1028 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);