1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001 - 2015 Intel Corporation
5 /* 82562G 10/100 Network Connection
6 * 82562G-2 10/100 Network Connection
7 * 82562GT 10/100 Network Connection
8 * 82562GT-2 10/100 Network Connection
9 * 82562V 10/100 Network Connection
10 * 82562V-2 10/100 Network Connection
11 * 82566DC-2 Gigabit Network Connection
12 * 82566DC Gigabit Network Connection
13 * 82566DM-2 Gigabit Network Connection
14 * 82566DM Gigabit Network Connection
15 * 82566MC Gigabit Network Connection
16 * 82566MM Gigabit Network Connection
17 * 82567LM Gigabit Network Connection
18 * 82567LF Gigabit Network Connection
19 * 82567V Gigabit Network Connection
20 * 82567LM-2 Gigabit Network Connection
21 * 82567LF-2 Gigabit Network Connection
22 * 82567V-2 Gigabit Network Connection
23 * 82567LF-3 Gigabit Network Connection
24 * 82567LM-3 Gigabit Network Connection
25 * 82567LM-4 Gigabit Network Connection
26 * 82577LM Gigabit Network Connection
27 * 82577LC Gigabit Network Connection
28 * 82578DM Gigabit Network Connection
29 * 82578DC Gigabit Network Connection
30 * 82579LM Gigabit Network Connection
31 * 82579V Gigabit Network Connection
32 * Ethernet Connection I217-LM
33 * Ethernet Connection I217-V
34 * Ethernet Connection I218-V
35 * Ethernet Connection I218-LM
36 * Ethernet Connection (2) I218-LM
37 * Ethernet Connection (2) I218-V
38 * Ethernet Connection (3) I218-LM
39 * Ethernet Connection (3) I218-V
42 #include "e1000_api.h"
44 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
45 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
46 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
47 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
48 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
49 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
50 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
51 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
52 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
53 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
54 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
55 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
58 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
59 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
60 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
61 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
62 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
64 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
66 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
67 u16 words, u16 *data);
68 STATIC s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
70 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
71 u16 words, u16 *data);
72 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
73 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
74 STATIC s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
75 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
77 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
78 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
79 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
80 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
81 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
82 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
83 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
84 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
85 u16 *speed, u16 *duplex);
86 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
87 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
88 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
89 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
90 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
91 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
92 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw);
93 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw);
94 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
95 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
96 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
97 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
98 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
99 u32 offset, u8 *data);
100 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
102 STATIC s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
104 STATIC s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
105 u32 offset, u32 *data);
106 STATIC s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
107 u32 offset, u32 data);
108 STATIC s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
109 u32 offset, u32 dword);
110 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
111 u32 offset, u16 *data);
112 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
113 u32 offset, u8 byte);
114 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
115 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
116 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
117 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
118 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
119 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
121 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
122 /* Offset 04h HSFSTS */
123 union ich8_hws_flash_status {
125 u16 flcdone:1; /* bit 0 Flash Cycle Done */
126 u16 flcerr:1; /* bit 1 Flash Cycle Error */
127 u16 dael:1; /* bit 2 Direct Access error Log */
128 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
129 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
130 u16 reserved1:2; /* bit 13:6 Reserved */
131 u16 reserved2:6; /* bit 13:6 Reserved */
132 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
133 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
138 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
139 /* Offset 06h FLCTL */
140 union ich8_hws_flash_ctrl {
141 struct ich8_hsflctl {
142 u16 flcgo:1; /* 0 Flash Cycle Go */
143 u16 flcycle:2; /* 2:1 Flash Cycle */
144 u16 reserved:5; /* 7:3 Reserved */
145 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
146 u16 flockdn:6; /* 15:10 Reserved */
151 /* ICH Flash Region Access Permissions */
152 union ich8_hws_flash_regacc {
154 u32 grra:8; /* 0:7 GbE region Read Access */
155 u32 grwa:8; /* 8:15 GbE region Write Access */
156 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
157 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
163 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
164 * @hw: pointer to the HW structure
166 * Test access to the PHY registers by reading the PHY ID registers. If
167 * the PHY ID is already known (e.g. resume path) compare it with known ID,
168 * otherwise assume the read PHY ID is correct if it is valid.
170 * Assumes the sw/fw/hw semaphore is already acquired.
172 STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
180 for (retry_count = 0; retry_count < 2; retry_count++) {
181 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
182 if (ret_val || (phy_reg == 0xFFFF))
184 phy_id = (u32)(phy_reg << 16);
186 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
187 if (ret_val || (phy_reg == 0xFFFF)) {
191 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
196 if (hw->phy.id == phy_id)
200 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
204 /* In case the PHY needs to be in mdio slow mode,
205 * set slow mode and try to get the PHY id again.
207 if (hw->mac.type < e1000_pch_lpt) {
208 hw->phy.ops.release(hw);
209 ret_val = e1000_set_mdio_slow_mode_hv(hw);
211 ret_val = e1000_get_phy_id(hw);
212 hw->phy.ops.acquire(hw);
218 if (hw->mac.type >= e1000_pch_lpt) {
219 /* Only unforce SMBus if ME is not active */
220 if (!(E1000_READ_REG(hw, E1000_FWSM) &
221 E1000_ICH_FWSM_FW_VALID)) {
222 /* Unforce SMBus mode in PHY */
223 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
224 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
225 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
227 /* Unforce SMBus mode in MAC */
228 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
229 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
230 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
238 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
239 * @hw: pointer to the HW structure
241 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
242 * used to reset the PHY to a quiescent state when necessary.
244 STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
248 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
250 /* Set Phy Config Counter to 50msec */
251 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
252 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
253 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
254 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
256 /* Toggle LANPHYPC Value bit */
257 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
258 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
259 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
260 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
261 E1000_WRITE_FLUSH(hw);
263 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
264 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
265 E1000_WRITE_FLUSH(hw);
267 if (hw->mac.type < e1000_pch_lpt) {
274 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
275 E1000_CTRL_EXT_LPCD) && count--);
282 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
283 * @hw: pointer to the HW structure
285 * Workarounds/flow necessary for PHY initialization during driver load
288 STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
290 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
293 DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
295 /* Gate automatic PHY configuration by hardware on managed and
296 * non-managed 82579 and newer adapters.
298 e1000_gate_hw_phy_config_ich8lan(hw, true);
301 /* It is not possible to be certain of the current state of ULP
302 * so forcibly disable it.
304 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
306 #endif /* ULP_SUPPORT */
307 ret_val = hw->phy.ops.acquire(hw);
309 DEBUGOUT("Failed to initialize PHY flow\n");
313 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
314 * inaccessible and resetting the PHY is not blocked, toggle the
315 * LANPHYPC Value bit to force the interconnect to PCIe mode.
317 switch (hw->mac.type) {
321 if (e1000_phy_is_accessible_pchlan(hw))
324 /* Before toggling LANPHYPC, see if PHY is accessible by
325 * forcing MAC to SMBus mode first.
327 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
328 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
329 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
331 /* Wait 50 milliseconds for MAC to finish any retries
332 * that it might be trying to perform from previous
333 * attempts to acknowledge any phy read requests.
339 if (e1000_phy_is_accessible_pchlan(hw))
344 if ((hw->mac.type == e1000_pchlan) &&
345 (fwsm & E1000_ICH_FWSM_FW_VALID))
348 if (hw->phy.ops.check_reset_block(hw)) {
349 DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
350 ret_val = -E1000_ERR_PHY;
354 /* Toggle LANPHYPC Value bit */
355 e1000_toggle_lanphypc_pch_lpt(hw);
356 if (hw->mac.type >= e1000_pch_lpt) {
357 if (e1000_phy_is_accessible_pchlan(hw))
360 /* Toggling LANPHYPC brings the PHY out of SMBus mode
361 * so ensure that the MAC is also out of SMBus mode
363 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
364 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
365 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
367 if (e1000_phy_is_accessible_pchlan(hw))
370 ret_val = -E1000_ERR_PHY;
377 hw->phy.ops.release(hw);
380 /* Check to see if able to reset PHY. Print error if not */
381 if (hw->phy.ops.check_reset_block(hw)) {
382 ERROR_REPORT("Reset blocked by ME\n");
386 /* Reset the PHY before any access to it. Doing so, ensures
387 * that the PHY is in a known good state before we read/write
388 * PHY registers. The generic reset is sufficient here,
389 * because we haven't determined the PHY type yet.
391 ret_val = e1000_phy_hw_reset_generic(hw);
395 /* On a successful reset, possibly need to wait for the PHY
396 * to quiesce to an accessible state before returning control
397 * to the calling function. If the PHY does not quiesce, then
398 * return E1000E_BLK_PHY_RESET, as this is the condition that
401 ret_val = hw->phy.ops.check_reset_block(hw);
403 ERROR_REPORT("ME blocked access to PHY after reset\n");
407 /* Ungate automatic PHY configuration on non-managed 82579 */
408 if ((hw->mac.type == e1000_pch2lan) &&
409 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
411 e1000_gate_hw_phy_config_ich8lan(hw, false);
418 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
419 * @hw: pointer to the HW structure
421 * Initialize family-specific PHY parameters and function pointers.
423 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
425 struct e1000_phy_info *phy = &hw->phy;
428 DEBUGFUNC("e1000_init_phy_params_pchlan");
431 phy->reset_delay_us = 100;
433 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
434 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
435 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
436 phy->ops.set_page = e1000_set_page_igp;
437 phy->ops.read_reg = e1000_read_phy_reg_hv;
438 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
439 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
440 phy->ops.release = e1000_release_swflag_ich8lan;
441 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
442 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
443 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
444 phy->ops.write_reg = e1000_write_phy_reg_hv;
445 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
446 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
447 phy->ops.power_up = e1000_power_up_phy_copper;
448 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
449 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
451 phy->id = e1000_phy_unknown;
453 ret_val = e1000_init_phy_workarounds_pchlan(hw);
457 if (phy->id == e1000_phy_unknown)
458 switch (hw->mac.type) {
460 ret_val = e1000_get_phy_id(hw);
463 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
470 /* In case the PHY needs to be in mdio slow mode,
471 * set slow mode and try to get the PHY id again.
473 ret_val = e1000_set_mdio_slow_mode_hv(hw);
476 ret_val = e1000_get_phy_id(hw);
481 phy->type = e1000_get_phy_type_from_id(phy->id);
484 case e1000_phy_82577:
485 case e1000_phy_82579:
487 phy->ops.check_polarity = e1000_check_polarity_82577;
488 phy->ops.force_speed_duplex =
489 e1000_phy_force_speed_duplex_82577;
490 phy->ops.get_cable_length = e1000_get_cable_length_82577;
491 phy->ops.get_info = e1000_get_phy_info_82577;
492 phy->ops.commit = e1000_phy_sw_reset_generic;
494 case e1000_phy_82578:
495 phy->ops.check_polarity = e1000_check_polarity_m88;
496 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
497 phy->ops.get_cable_length = e1000_get_cable_length_m88;
498 phy->ops.get_info = e1000_get_phy_info_m88;
501 ret_val = -E1000_ERR_PHY;
509 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
510 * @hw: pointer to the HW structure
512 * Initialize family-specific PHY parameters and function pointers.
514 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
516 struct e1000_phy_info *phy = &hw->phy;
520 DEBUGFUNC("e1000_init_phy_params_ich8lan");
523 phy->reset_delay_us = 100;
525 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
526 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
527 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
528 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
529 phy->ops.read_reg = e1000_read_phy_reg_igp;
530 phy->ops.release = e1000_release_swflag_ich8lan;
531 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
532 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
533 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
534 phy->ops.write_reg = e1000_write_phy_reg_igp;
535 phy->ops.power_up = e1000_power_up_phy_copper;
536 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
538 /* We may need to do this twice - once for IGP and if that fails,
539 * we'll set BM func pointers and try again
541 ret_val = e1000_determine_phy_address(hw);
543 phy->ops.write_reg = e1000_write_phy_reg_bm;
544 phy->ops.read_reg = e1000_read_phy_reg_bm;
545 ret_val = e1000_determine_phy_address(hw);
547 DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
553 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
556 ret_val = e1000_get_phy_id(hw);
563 case IGP03E1000_E_PHY_ID:
564 phy->type = e1000_phy_igp_3;
565 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
566 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
567 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
568 phy->ops.get_info = e1000_get_phy_info_igp;
569 phy->ops.check_polarity = e1000_check_polarity_igp;
570 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
573 case IFE_PLUS_E_PHY_ID:
575 phy->type = e1000_phy_ife;
576 phy->autoneg_mask = E1000_ALL_NOT_GIG;
577 phy->ops.get_info = e1000_get_phy_info_ife;
578 phy->ops.check_polarity = e1000_check_polarity_ife;
579 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
581 case BME1000_E_PHY_ID:
582 phy->type = e1000_phy_bm;
583 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
584 phy->ops.read_reg = e1000_read_phy_reg_bm;
585 phy->ops.write_reg = e1000_write_phy_reg_bm;
586 phy->ops.commit = e1000_phy_sw_reset_generic;
587 phy->ops.get_info = e1000_get_phy_info_m88;
588 phy->ops.check_polarity = e1000_check_polarity_m88;
589 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
592 return -E1000_ERR_PHY;
596 return E1000_SUCCESS;
600 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
601 * @hw: pointer to the HW structure
603 * Initialize family-specific NVM parameters and function
606 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
608 struct e1000_nvm_info *nvm = &hw->nvm;
609 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
610 u32 gfpreg, sector_base_addr, sector_end_addr;
614 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
616 nvm->type = e1000_nvm_flash_sw;
618 if (hw->mac.type >= e1000_pch_spt) {
619 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
620 * STRAP register. This is because in SPT the GbE Flash region
621 * is no longer accessed through the flash registers. Instead,
622 * the mechanism has changed, and the Flash region access
623 * registers are now implemented in GbE memory space.
625 nvm->flash_base_addr = 0;
627 (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
628 * NVM_SIZE_MULTIPLIER;
629 nvm->flash_bank_size = nvm_size / 2;
630 /* Adjust to word count */
631 nvm->flash_bank_size /= sizeof(u16);
632 /* Set the base address for flash register access */
633 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
635 /* Can't read flash registers if register set isn't mapped. */
636 if (!hw->flash_address) {
637 DEBUGOUT("ERROR: Flash registers not mapped\n");
638 return -E1000_ERR_CONFIG;
641 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
643 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
644 * Add 1 to sector_end_addr since this sector is included in
647 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
648 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
650 /* flash_base_addr is byte-aligned */
651 nvm->flash_base_addr = sector_base_addr
652 << FLASH_SECTOR_ADDR_SHIFT;
654 /* find total size of the NVM, then cut in half since the total
655 * size represents two separate NVM banks.
657 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
658 << FLASH_SECTOR_ADDR_SHIFT);
659 nvm->flash_bank_size /= 2;
660 /* Adjust to word count */
661 nvm->flash_bank_size /= sizeof(u16);
664 nvm->word_size = E1000_SHADOW_RAM_WORDS;
666 /* Clear shadow ram */
667 for (i = 0; i < nvm->word_size; i++) {
668 dev_spec->shadow_ram[i].modified = false;
669 dev_spec->shadow_ram[i].value = 0xFFFF;
672 E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
673 E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
675 /* Function Pointers */
676 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
677 nvm->ops.release = e1000_release_nvm_ich8lan;
678 if (hw->mac.type >= e1000_pch_spt) {
679 nvm->ops.read = e1000_read_nvm_spt;
680 nvm->ops.update = e1000_update_nvm_checksum_spt;
682 nvm->ops.read = e1000_read_nvm_ich8lan;
683 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
685 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
686 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
687 nvm->ops.write = e1000_write_nvm_ich8lan;
689 return E1000_SUCCESS;
693 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
694 * @hw: pointer to the HW structure
696 * Initialize family-specific MAC parameters and function
699 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
701 struct e1000_mac_info *mac = &hw->mac;
702 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
704 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
706 DEBUGFUNC("e1000_init_mac_params_ich8lan");
708 /* Set media type function pointer */
709 hw->phy.media_type = e1000_media_type_copper;
711 /* Set mta register count */
712 mac->mta_reg_count = 32;
713 /* Set rar entry count */
714 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
715 if (mac->type == e1000_ich8lan)
716 mac->rar_entry_count--;
717 /* Set if part includes ASF firmware */
718 mac->asf_firmware_present = true;
720 mac->has_fwsm = true;
721 /* ARC subsystem not supported */
722 mac->arc_subsystem_valid = false;
723 /* Adaptive IFS supported */
724 mac->adaptive_ifs = true;
726 /* Function pointers */
728 /* bus type/speed/width */
729 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
731 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
733 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
734 /* hw initialization */
735 mac->ops.init_hw = e1000_init_hw_ich8lan;
737 mac->ops.setup_link = e1000_setup_link_ich8lan;
738 /* physical interface setup */
739 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
741 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
743 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
744 /* multicast address update */
745 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
746 /* clear hardware counters */
747 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
749 /* LED and other operations */
754 /* check management mode */
755 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
757 mac->ops.id_led_init = e1000_id_led_init_generic;
759 mac->ops.blink_led = e1000_blink_led_generic;
761 mac->ops.setup_led = e1000_setup_led_generic;
763 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
764 /* turn on/off LED */
765 mac->ops.led_on = e1000_led_on_ich8lan;
766 mac->ops.led_off = e1000_led_off_ich8lan;
769 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
770 mac->ops.rar_set = e1000_rar_set_pch2lan;
775 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
776 /* multicast address update for pch2 */
777 mac->ops.update_mc_addr_list =
778 e1000_update_mc_addr_list_pch2lan;
782 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
783 /* save PCH revision_id */
784 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
785 /* SPT uses full byte for revision ID,
786 * as opposed to previous generations
788 if (hw->mac.type >= e1000_pch_spt)
789 hw->revision_id = (u8)(pci_cfg &= 0x00FF);
791 hw->revision_id = (u8)(pci_cfg &= 0x000F);
792 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
793 /* check management mode */
794 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
796 mac->ops.id_led_init = e1000_id_led_init_pchlan;
798 mac->ops.setup_led = e1000_setup_led_pchlan;
800 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
801 /* turn on/off LED */
802 mac->ops.led_on = e1000_led_on_pchlan;
803 mac->ops.led_off = e1000_led_off_pchlan;
809 if (mac->type >= e1000_pch_lpt) {
810 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
811 mac->ops.rar_set = e1000_rar_set_pch_lpt;
812 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
815 /* Enable PCS Lock-loss workaround for ICH8 */
816 if (mac->type == e1000_ich8lan)
817 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
819 return E1000_SUCCESS;
823 * __e1000_access_emi_reg_locked - Read/write EMI register
824 * @hw: pointer to the HW structure
825 * @addr: EMI address to program
826 * @data: pointer to value to read/write from/to the EMI address
827 * @read: boolean flag to indicate read or write
829 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
831 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
832 u16 *data, bool read)
836 DEBUGFUNC("__e1000_access_emi_reg_locked");
838 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
843 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
846 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
853 * e1000_read_emi_reg_locked - Read Extended Management Interface register
854 * @hw: pointer to the HW structure
855 * @addr: EMI address to program
856 * @data: value to be read from the EMI address
858 * Assumes the SW/FW/HW Semaphore is already acquired.
860 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
862 DEBUGFUNC("e1000_read_emi_reg_locked");
864 return __e1000_access_emi_reg_locked(hw, addr, data, true);
868 * e1000_write_emi_reg_locked - Write Extended Management Interface register
869 * @hw: pointer to the HW structure
870 * @addr: EMI address to program
871 * @data: value to be written to the EMI address
873 * Assumes the SW/FW/HW Semaphore is already acquired.
875 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
877 DEBUGFUNC("e1000_read_emi_reg_locked");
879 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
883 * e1000_set_eee_pchlan - Enable/disable EEE support
884 * @hw: pointer to the HW structure
886 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
887 * the link and the EEE capabilities of the link partner. The LPI Control
888 * register bits will remain set only if/when link is up.
890 * EEE LPI must not be asserted earlier than one second after link is up.
891 * On 82579, EEE LPI should not be enabled until such time otherwise there
892 * can be link issues with some switches. Other devices can have EEE LPI
893 * enabled immediately upon link up since they have a timer in hardware which
894 * prevents LPI from being asserted too early.
896 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
898 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
900 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
902 DEBUGFUNC("e1000_set_eee_pchlan");
904 switch (hw->phy.type) {
905 case e1000_phy_82579:
906 lpa = I82579_EEE_LP_ABILITY;
907 pcs_status = I82579_EEE_PCS_STATUS;
908 adv_addr = I82579_EEE_ADVERTISEMENT;
911 lpa = I217_EEE_LP_ABILITY;
912 pcs_status = I217_EEE_PCS_STATUS;
913 adv_addr = I217_EEE_ADVERTISEMENT;
916 return E1000_SUCCESS;
919 ret_val = hw->phy.ops.acquire(hw);
923 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
927 /* Clear bits that enable EEE in various speeds */
928 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
930 /* Enable EEE if not disabled by user */
931 if (!dev_spec->eee_disable) {
932 /* Save off link partner's EEE ability */
933 ret_val = e1000_read_emi_reg_locked(hw, lpa,
934 &dev_spec->eee_lp_ability);
938 /* Read EEE advertisement */
939 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
943 /* Enable EEE only for speeds in which the link partner is
944 * EEE capable and for which we advertise EEE.
946 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
947 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
949 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
950 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
951 if (data & NWAY_LPAR_100TX_FD_CAPS)
952 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
954 /* EEE is not supported in 100Half, so ignore
955 * partner's EEE in 100 ability if full-duplex
958 dev_spec->eee_lp_ability &=
959 ~I82579_EEE_100_SUPPORTED;
963 if (hw->phy.type == e1000_phy_82579) {
964 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
969 data &= ~I82579_LPI_100_PLL_SHUT;
970 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
974 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
975 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
979 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
981 hw->phy.ops.release(hw);
987 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
988 * @hw: pointer to the HW structure
989 * @link: link up bool flag
991 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
992 * preventing further DMA write requests. Workaround the issue by disabling
993 * the de-assertion of the clock request when in 1Gpbs mode.
994 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
995 * speeds in order to avoid Tx hangs.
997 STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
999 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1000 u32 status = E1000_READ_REG(hw, E1000_STATUS);
1001 s32 ret_val = E1000_SUCCESS;
1004 if (link && (status & E1000_STATUS_SPEED_1000)) {
1005 ret_val = hw->phy.ops.acquire(hw);
1010 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1016 e1000_write_kmrn_reg_locked(hw,
1017 E1000_KMRNCTRLSTA_K1_CONFIG,
1019 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1025 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1026 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1029 e1000_write_kmrn_reg_locked(hw,
1030 E1000_KMRNCTRLSTA_K1_CONFIG,
1033 hw->phy.ops.release(hw);
1035 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1036 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1038 if ((hw->phy.revision > 5) || !link ||
1039 ((status & E1000_STATUS_SPEED_100) &&
1040 (status & E1000_STATUS_FD)))
1041 goto update_fextnvm6;
1043 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1047 /* Clear link status transmit timeout */
1048 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1050 if (status & E1000_STATUS_SPEED_100) {
1051 /* Set inband Tx timeout to 5x10us for 100Half */
1052 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1054 /* Do not extend the K1 entry latency for 100Half */
1055 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1057 /* Set inband Tx timeout to 50x10us for 10Full/Half */
1059 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1061 /* Extend the K1 entry latency for 10 Mbps */
1062 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1065 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1070 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1078 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1079 * @hw: pointer to the HW structure
1080 * @to_sx: boolean indicating a system power state transition to Sx
1082 * When link is down, configure ULP mode to significantly reduce the power
1083 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1084 * ME firmware to start the ULP configuration. If not on an ME enabled
1085 * system, configure the ULP mode by software.
1087 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1090 s32 ret_val = E1000_SUCCESS;
1094 if ((hw->mac.type < e1000_pch_lpt) ||
1095 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1096 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1097 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1098 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1099 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1104 /* Poll up to 5 seconds for Cable Disconnected indication */
1105 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1106 E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1107 /* Bail if link is re-acquired */
1108 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1109 return -E1000_ERR_PHY;
1115 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1116 (E1000_READ_REG(hw, E1000_FEXT) &
1117 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1119 if (!(E1000_READ_REG(hw, E1000_FEXT) &
1120 E1000_FEXT_PHY_CABLE_DISCONNECTED))
1124 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1125 /* Request ME configure ULP mode in the PHY */
1126 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1127 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1128 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1133 ret_val = hw->phy.ops.acquire(hw);
1137 /* During S0 Idle keep the phy in PCI-E mode */
1138 if (hw->dev_spec.ich8lan.smbus_disable)
1141 /* Force SMBus mode in PHY */
1142 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1145 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1146 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1148 /* Force SMBus mode in MAC */
1149 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1150 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1151 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1153 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1154 * LPLU and disable Gig speed when entering ULP
1156 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1157 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1163 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1165 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1174 /* Change the 'Link Status Change' interrupt to trigger
1175 * on 'Cable Status Change'
1177 ret_val = e1000_read_kmrn_reg_locked(hw,
1178 E1000_KMRNCTRLSTA_OP_MODES,
1182 phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1183 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1187 /* Set Inband ULP Exit, Reset to SMBus mode and
1188 * Disable SMBus Release on PERST# in PHY
1190 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1193 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1194 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1196 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1197 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1199 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1201 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1202 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1204 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1205 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1206 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1208 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1210 /* Set Disable SMBus Release on PERST# in MAC */
1211 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1212 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1213 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1215 /* Commit ULP changes in PHY by starting auto ULP configuration */
1216 phy_reg |= I218_ULP_CONFIG1_START;
1217 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1220 /* Disable Tx so that the MAC doesn't send any (buffered)
1221 * packets to the PHY.
1223 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1224 mac_reg &= ~E1000_TCTL_EN;
1225 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1228 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1229 to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1230 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1237 hw->phy.ops.release(hw);
1240 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1242 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1248 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1249 * @hw: pointer to the HW structure
1250 * @force: boolean indicating whether or not to force disabling ULP
1252 * Un-configure ULP mode when link is up, the system is transitioned from
1253 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1254 * system, poll for an indication from ME that ULP has been un-configured.
1255 * If not on an ME enabled system, un-configure the ULP mode by software.
1257 * During nominal operation, this function is called when link is acquired
1258 * to disable ULP mode (force=false); otherwise, for example when unloading
1259 * the driver or during Sx->S0 transitions, this is called with force=true
1260 * to forcibly disable ULP.
1262 * When the cable is plugged in while the device is in D0, a Cable Status
1263 * Change interrupt is generated which causes this function to be called
1264 * to partially disable ULP mode and restart autonegotiation. This function
1265 * is then called again due to the resulting Link Status Change interrupt
1266 * to finish cleaning up after the ULP flow.
1268 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1270 s32 ret_val = E1000_SUCCESS;
1275 if ((hw->mac.type < e1000_pch_lpt) ||
1276 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1277 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1278 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1279 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1280 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1283 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1285 /* Request ME un-configure ULP mode in the PHY */
1286 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1287 mac_reg &= ~E1000_H2ME_ULP;
1288 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1289 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1292 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1293 while (E1000_READ_REG(hw, E1000_FWSM) &
1294 E1000_FWSM_ULP_CFG_DONE) {
1296 ret_val = -E1000_ERR_PHY;
1302 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1305 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1306 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1307 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1309 /* Clear H2ME.ULP after ME ULP configuration */
1310 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1311 mac_reg &= ~E1000_H2ME_ULP;
1312 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1314 /* Restore link speed advertisements and restart
1317 if (hw->mac.autoneg) {
1318 ret_val = e1000_phy_setup_autoneg(hw);
1322 ret_val = e1000_setup_copper_link_generic(hw);
1326 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1332 ret_val = hw->phy.ops.acquire(hw);
1336 /* Revert the change to the 'Link Status Change'
1337 * interrupt to trigger on 'Cable Status Change'
1339 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1343 phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1344 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
1347 /* Toggle LANPHYPC Value bit */
1348 e1000_toggle_lanphypc_pch_lpt(hw);
1350 /* Unforce SMBus mode in PHY */
1351 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1353 /* The MAC might be in PCIe mode, so temporarily force to
1354 * SMBus mode in order to access the PHY.
1356 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1357 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1358 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1362 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1367 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1368 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1370 /* Unforce SMBus mode in MAC */
1371 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1372 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1373 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1375 /* When ULP mode was previously entered, K1 was disabled by the
1376 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1378 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1381 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1382 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1384 /* Clear ULP enabled configuration */
1385 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1388 /* CSC interrupt received due to ULP Indication */
1389 if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
1390 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1391 I218_ULP_CONFIG1_STICKY_ULP |
1392 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1393 I218_ULP_CONFIG1_WOL_HOST |
1394 I218_ULP_CONFIG1_INBAND_EXIT |
1395 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1396 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1397 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1398 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1400 /* Commit ULP changes by starting auto ULP configuration */
1401 phy_reg |= I218_ULP_CONFIG1_START;
1402 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1404 /* Clear Disable SMBus Release on PERST# in MAC */
1405 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1406 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1407 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1410 hw->phy.ops.release(hw);
1412 if (hw->mac.autoneg)
1413 e1000_phy_setup_autoneg(hw);
1415 e1000_setup_copper_link_generic(hw);
1417 e1000_sw_lcd_config_ich8lan(hw);
1419 e1000_oem_bits_config_ich8lan(hw, true);
1421 /* Set ULP state to unknown and return non-zero to
1422 * indicate no link (yet) and re-enter on the next LSC
1423 * to finish disabling ULP flow.
1425 hw->dev_spec.ich8lan.ulp_state =
1426 e1000_ulp_state_unknown;
1433 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1434 mac_reg |= E1000_TCTL_EN;
1435 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1438 hw->phy.ops.release(hw);
1440 hw->phy.ops.reset(hw);
1445 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1447 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1452 #endif /* ULP_SUPPORT */
1456 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1457 * @hw: pointer to the HW structure
1459 * Checks to see of the link status of the hardware has changed. If a
1460 * change in link status has been detected, then we read the PHY registers
1461 * to get the current speed/duplex if link exists.
1463 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1465 struct e1000_mac_info *mac = &hw->mac;
1466 s32 ret_val, tipg_reg = 0;
1467 u16 emi_addr, emi_val = 0;
1471 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1473 /* We only want to go out to the PHY registers to see if Auto-Neg
1474 * has completed and/or if our link status has changed. The
1475 * get_link_status flag is set upon receiving a Link Status
1476 * Change or Rx Sequence Error interrupt.
1478 if (!mac->get_link_status)
1479 return E1000_SUCCESS;
1481 if ((hw->mac.type < e1000_pch_lpt) ||
1482 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1483 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
1484 /* First we want to see if the MII Status Register reports
1485 * link. If so, then we want to get the current speed/duplex
1488 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1492 /* Check the MAC's STATUS register to determine link state
1493 * since the PHY could be inaccessible while in ULP mode.
1495 link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
1497 ret_val = e1000_disable_ulp_lpt_lp(hw, false);
1499 ret_val = e1000_enable_ulp_lpt_lp(hw, false);
1504 if (hw->mac.type == e1000_pchlan) {
1505 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1510 /* When connected at 10Mbps half-duplex, some parts are excessively
1511 * aggressive resulting in many collisions. To avoid this, increase
1512 * the IPG and reduce Rx latency in the PHY.
1514 if ((hw->mac.type >= e1000_pch2lan) && link) {
1517 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1518 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1519 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1521 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1523 /* Reduce Rx latency in analog PHY */
1525 } else if (hw->mac.type >= e1000_pch_spt &&
1526 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1530 /* Roll back the default values */
1535 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1537 ret_val = hw->phy.ops.acquire(hw);
1541 if (hw->mac.type == e1000_pch2lan)
1542 emi_addr = I82579_RX_CONFIG;
1544 emi_addr = I217_RX_CONFIG;
1545 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1548 if (hw->mac.type >= e1000_pch_lpt) {
1551 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1553 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1554 if (speed == SPEED_100 || speed == SPEED_10)
1558 hw->phy.ops.write_reg_locked(hw,
1559 I217_PLL_CLOCK_GATE_REG,
1562 if (speed == SPEED_1000) {
1563 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1566 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1568 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1572 hw->phy.ops.release(hw);
1577 if (hw->mac.type >= e1000_pch_spt) {
1581 if (speed == SPEED_1000) {
1582 ret_val = hw->phy.ops.acquire(hw);
1586 ret_val = hw->phy.ops.read_reg_locked(hw,
1590 hw->phy.ops.release(hw);
1594 ptr_gap = (data & (0x3FF << 2)) >> 2;
1595 if (ptr_gap < 0x18) {
1596 data &= ~(0x3FF << 2);
1597 data |= (0x18 << 2);
1599 hw->phy.ops.write_reg_locked(hw,
1600 PHY_REG(776, 20), data);
1602 hw->phy.ops.release(hw);
1606 ret_val = hw->phy.ops.acquire(hw);
1610 ret_val = hw->phy.ops.write_reg_locked(hw,
1613 hw->phy.ops.release(hw);
1621 /* I217 Packet Loss issue:
1622 * ensure that FEXTNVM4 Beacon Duration is set correctly
1624 * Set the Beacon Duration for I217 to 8 usec
1626 if (hw->mac.type >= e1000_pch_lpt) {
1629 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1630 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1631 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1632 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1635 /* Work-around I218 hang issue */
1636 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1637 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1638 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1639 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1640 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1644 /* Clear link partner's EEE ability */
1645 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1647 /* Configure K0s minimum time */
1648 if (hw->mac.type >= e1000_pch_lpt) {
1649 e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
1652 if (hw->mac.type >= e1000_pch_lpt) {
1653 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1655 if (hw->mac.type == e1000_pch_spt) {
1656 /* FEXTNVM6 K1-off workaround - for SPT only */
1657 u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
1659 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1660 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1662 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1665 if (hw->dev_spec.ich8lan.disable_k1_off == true)
1666 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1668 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1672 return E1000_SUCCESS; /* No link detected */
1674 mac->get_link_status = false;
1676 switch (hw->mac.type) {
1678 ret_val = e1000_k1_workaround_lv(hw);
1683 if (hw->phy.type == e1000_phy_82578) {
1684 ret_val = e1000_link_stall_workaround_hv(hw);
1689 /* Workaround for PCHx parts in half-duplex:
1690 * Set the number of preambles removed from the packet
1691 * when it is passed from the PHY to the MAC to prevent
1692 * the MAC from misinterpreting the packet type.
1694 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1695 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1697 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1699 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1701 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1707 /* Check if there was DownShift, must be checked
1708 * immediately after link-up
1710 e1000_check_downshift_generic(hw);
1712 /* Enable/Disable EEE after link up */
1713 if (hw->phy.type > e1000_phy_82579) {
1714 ret_val = e1000_set_eee_pchlan(hw);
1719 /* If we are forcing speed/duplex, then we simply return since
1720 * we have already determined whether we have link or not.
1723 return -E1000_ERR_CONFIG;
1725 /* Auto-Neg is enabled. Auto Speed Detection takes care
1726 * of MAC speed/duplex configuration. So we only need to
1727 * configure Collision Distance in the MAC.
1729 mac->ops.config_collision_dist(hw);
1731 /* Configure Flow Control now that Auto-Neg has completed.
1732 * First, we need to restore the desired flow control
1733 * settings because we may have had to re-autoneg with a
1734 * different link partner.
1736 ret_val = e1000_config_fc_after_link_up_generic(hw);
1738 DEBUGOUT("Error configuring flow control\n");
1744 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1745 * @hw: pointer to the HW structure
1747 * Initialize family-specific function pointers for PHY, MAC, and NVM.
1749 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1751 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1753 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1754 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1755 switch (hw->mac.type) {
1758 case e1000_ich10lan:
1759 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1766 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1774 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1775 * @hw: pointer to the HW structure
1777 * Acquires the mutex for performing NVM operations.
1779 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1781 DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1783 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1785 return E1000_SUCCESS;
1789 * e1000_release_nvm_ich8lan - Release NVM mutex
1790 * @hw: pointer to the HW structure
1792 * Releases the mutex used while performing NVM operations.
1794 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1796 DEBUGFUNC("e1000_release_nvm_ich8lan");
1798 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1804 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1805 * @hw: pointer to the HW structure
1807 * Acquires the software control flag for performing PHY and select
1810 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1812 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1813 s32 ret_val = E1000_SUCCESS;
1815 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1817 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1820 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1821 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1829 DEBUGOUT("SW has already locked the resource.\n");
1830 ret_val = -E1000_ERR_CONFIG;
1834 timeout = SW_FLAG_TIMEOUT;
1836 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1837 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1840 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1841 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1849 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1850 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1851 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1852 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1853 ret_val = -E1000_ERR_CONFIG;
1859 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1865 * e1000_release_swflag_ich8lan - Release software control flag
1866 * @hw: pointer to the HW structure
1868 * Releases the software control flag for performing PHY and select
1871 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1875 DEBUGFUNC("e1000_release_swflag_ich8lan");
1877 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1879 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1880 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1881 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1883 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1886 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1892 * e1000_check_mng_mode_ich8lan - Checks management mode
1893 * @hw: pointer to the HW structure
1895 * This checks if the adapter has any manageability enabled.
1896 * This is a function pointer entry point only called by read/write
1897 * routines for the PHY and NVM parts.
1899 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1903 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1905 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1907 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1908 ((fwsm & E1000_FWSM_MODE_MASK) ==
1909 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1913 * e1000_check_mng_mode_pchlan - Checks management mode
1914 * @hw: pointer to the HW structure
1916 * This checks if the adapter has iAMT enabled.
1917 * This is a function pointer entry point only called by read/write
1918 * routines for the PHY and NVM parts.
1920 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1924 DEBUGFUNC("e1000_check_mng_mode_pchlan");
1926 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1928 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1929 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1933 * e1000_rar_set_pch2lan - Set receive address register
1934 * @hw: pointer to the HW structure
1935 * @addr: pointer to the receive address
1936 * @index: receive address array register
1938 * Sets the receive address array register at index to the address passed
1939 * in by addr. For 82579, RAR[0] is the base address register that is to
1940 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1941 * Use SHRA[0-3] in place of those reserved for ME.
1943 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1945 u32 rar_low, rar_high;
1947 DEBUGFUNC("e1000_rar_set_pch2lan");
1949 /* HW expects these in little endian so we reverse the byte order
1950 * from network order (big endian) to little endian
1952 rar_low = ((u32) addr[0] |
1953 ((u32) addr[1] << 8) |
1954 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1956 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1958 /* If MAC address zero, no need to set the AV bit */
1959 if (rar_low || rar_high)
1960 rar_high |= E1000_RAH_AV;
1963 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1964 E1000_WRITE_FLUSH(hw);
1965 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1966 E1000_WRITE_FLUSH(hw);
1967 return E1000_SUCCESS;
1970 /* RAR[1-6] are owned by manageability. Skip those and program the
1971 * next address into the SHRA register array.
1973 if (index < (u32) (hw->mac.rar_entry_count)) {
1976 ret_val = e1000_acquire_swflag_ich8lan(hw);
1980 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1981 E1000_WRITE_FLUSH(hw);
1982 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1983 E1000_WRITE_FLUSH(hw);
1985 e1000_release_swflag_ich8lan(hw);
1987 /* verify the register updates */
1988 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1989 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1990 return E1000_SUCCESS;
1992 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1993 (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1997 DEBUGOUT1("Failed to write receive address at index %d\n", index);
1998 return -E1000_ERR_CONFIG;
2002 * e1000_rar_set_pch_lpt - Set receive address registers
2003 * @hw: pointer to the HW structure
2004 * @addr: pointer to the receive address
2005 * @index: receive address array register
2007 * Sets the receive address register array at index to the address passed
2008 * in by addr. For LPT, RAR[0] is the base address register that is to
2009 * contain the MAC address. SHRA[0-10] are the shared receive address
2010 * registers that are shared between the Host and manageability engine (ME).
2012 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
2014 u32 rar_low, rar_high;
2017 DEBUGFUNC("e1000_rar_set_pch_lpt");
2019 /* HW expects these in little endian so we reverse the byte order
2020 * from network order (big endian) to little endian
2022 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
2023 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2025 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2027 /* If MAC address zero, no need to set the AV bit */
2028 if (rar_low || rar_high)
2029 rar_high |= E1000_RAH_AV;
2032 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2033 E1000_WRITE_FLUSH(hw);
2034 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2035 E1000_WRITE_FLUSH(hw);
2036 return E1000_SUCCESS;
2039 /* The manageability engine (ME) can lock certain SHRAR registers that
2040 * it is using - those registers are unavailable for use.
2042 if (index < hw->mac.rar_entry_count) {
2043 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
2044 E1000_FWSM_WLOCK_MAC_MASK;
2045 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2047 /* Check if all SHRAR registers are locked */
2051 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2054 ret_val = e1000_acquire_swflag_ich8lan(hw);
2059 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
2061 E1000_WRITE_FLUSH(hw);
2062 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
2064 E1000_WRITE_FLUSH(hw);
2066 e1000_release_swflag_ich8lan(hw);
2068 /* verify the register updates */
2069 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2070 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
2071 return E1000_SUCCESS;
2076 DEBUGOUT1("Failed to write receive address at index %d\n", index);
2077 return -E1000_ERR_CONFIG;
2080 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
2082 * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
2083 * @hw: pointer to the HW structure
2084 * @mc_addr_list: array of multicast addresses to program
2085 * @mc_addr_count: number of multicast addresses to program
2087 * Updates entire Multicast Table Array of the PCH2 MAC and PHY.
2088 * The caller must have a packed mc_addr_list of multicast addresses.
2090 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
2098 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
2100 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
2102 ret_val = hw->phy.ops.acquire(hw);
2106 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2110 for (i = 0; i < hw->mac.mta_reg_count; i++) {
2111 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
2112 (u16)(hw->mac.mta_shadow[i] &
2114 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
2115 (u16)((hw->mac.mta_shadow[i] >> 16) &
2119 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2122 hw->phy.ops.release(hw);
2125 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
2127 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2128 * @hw: pointer to the HW structure
2130 * Checks if firmware is blocking the reset of the PHY.
2131 * This is a function pointer entry point only called by
2134 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2137 bool blocked = false;
2140 DEBUGFUNC("e1000_check_reset_block_ich8lan");
2143 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2144 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2150 } while (blocked && (i++ < 30));
2151 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2155 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2156 * @hw: pointer to the HW structure
2158 * Assumes semaphore already acquired.
2161 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2164 u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2165 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2166 E1000_STRAP_SMT_FREQ_SHIFT;
2169 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2171 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2175 phy_data &= ~HV_SMB_ADDR_MASK;
2176 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2177 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2179 if (hw->phy.type == e1000_phy_i217) {
2180 /* Restore SMBus frequency */
2182 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2183 phy_data |= (freq & (1 << 0)) <<
2184 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2185 phy_data |= (freq & (1 << 1)) <<
2186 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2188 DEBUGOUT("Unsupported SMB frequency in PHY\n");
2192 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2196 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2197 * @hw: pointer to the HW structure
2199 * SW should configure the LCD from the NVM extended configuration region
2200 * as a workaround for certain parts.
2202 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2204 struct e1000_phy_info *phy = &hw->phy;
2205 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2206 s32 ret_val = E1000_SUCCESS;
2207 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2209 DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2211 /* Initialize the PHY from the NVM on ICH platforms. This
2212 * is needed due to an issue where the NVM configuration is
2213 * not properly autoloaded after power transitions.
2214 * Therefore, after each PHY reset, we will load the
2215 * configuration data out of the NVM manually.
2217 switch (hw->mac.type) {
2219 if (phy->type != e1000_phy_igp_3)
2222 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2223 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2224 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2233 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2239 ret_val = hw->phy.ops.acquire(hw);
2243 data = E1000_READ_REG(hw, E1000_FEXTNVM);
2244 if (!(data & sw_cfg_mask))
2247 /* Make sure HW does not configure LCD from PHY
2248 * extended configuration before SW configuration
2250 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2251 if ((hw->mac.type < e1000_pch2lan) &&
2252 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2255 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2256 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2257 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2261 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2262 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2264 if (((hw->mac.type == e1000_pchlan) &&
2265 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2266 (hw->mac.type > e1000_pchlan)) {
2267 /* HW configures the SMBus address and LEDs when the
2268 * OEM and LCD Write Enable bits are set in the NVM.
2269 * When both NVM bits are cleared, SW will configure
2272 ret_val = e1000_write_smbus_addr(hw);
2276 data = E1000_READ_REG(hw, E1000_LEDCTL);
2277 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2283 /* Configure LCD from extended configuration region. */
2285 /* cnf_base_addr is in DWORD */
2286 word_addr = (u16)(cnf_base_addr << 1);
2288 for (i = 0; i < cnf_size; i++) {
2289 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2294 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2299 /* Save off the PHY page for future writes. */
2300 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2301 phy_page = reg_data;
2305 reg_addr &= PHY_REG_MASK;
2306 reg_addr |= phy_page;
2308 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2315 hw->phy.ops.release(hw);
2320 * e1000_k1_gig_workaround_hv - K1 Si workaround
2321 * @hw: pointer to the HW structure
2322 * @link: link up bool flag
2324 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2325 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2326 * If link is down, the function will restore the default K1 setting located
2329 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2331 s32 ret_val = E1000_SUCCESS;
2333 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2335 DEBUGFUNC("e1000_k1_gig_workaround_hv");
2337 if (hw->mac.type != e1000_pchlan)
2338 return E1000_SUCCESS;
2340 /* Wrap the whole flow with the sw flag */
2341 ret_val = hw->phy.ops.acquire(hw);
2345 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2347 if (hw->phy.type == e1000_phy_82578) {
2348 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2353 status_reg &= (BM_CS_STATUS_LINK_UP |
2354 BM_CS_STATUS_RESOLVED |
2355 BM_CS_STATUS_SPEED_MASK);
2357 if (status_reg == (BM_CS_STATUS_LINK_UP |
2358 BM_CS_STATUS_RESOLVED |
2359 BM_CS_STATUS_SPEED_1000))
2363 if (hw->phy.type == e1000_phy_82577) {
2364 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2369 status_reg &= (HV_M_STATUS_LINK_UP |
2370 HV_M_STATUS_AUTONEG_COMPLETE |
2371 HV_M_STATUS_SPEED_MASK);
2373 if (status_reg == (HV_M_STATUS_LINK_UP |
2374 HV_M_STATUS_AUTONEG_COMPLETE |
2375 HV_M_STATUS_SPEED_1000))
2379 /* Link stall fix for link up */
2380 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2386 /* Link stall fix for link down */
2387 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2393 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2396 hw->phy.ops.release(hw);
2402 * e1000_configure_k1_ich8lan - Configure K1 power state
2403 * @hw: pointer to the HW structure
2404 * @enable: K1 state to configure
2406 * Configure the K1 power state based on the provided parameter.
2407 * Assumes semaphore already acquired.
2409 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2411 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2419 DEBUGFUNC("e1000_configure_k1_ich8lan");
2421 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2427 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2429 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2431 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2437 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2438 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2440 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2441 reg |= E1000_CTRL_FRCSPD;
2442 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2444 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2445 E1000_WRITE_FLUSH(hw);
2447 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2448 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2449 E1000_WRITE_FLUSH(hw);
2452 return E1000_SUCCESS;
2456 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2457 * @hw: pointer to the HW structure
2458 * @d0_state: boolean if entering d0 or d3 device state
2460 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2461 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2462 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2464 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2470 DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2472 if (hw->mac.type < e1000_pchlan)
2475 ret_val = hw->phy.ops.acquire(hw);
2479 if (hw->mac.type == e1000_pchlan) {
2480 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2481 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2485 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2486 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2489 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2491 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2495 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2498 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2499 oem_reg |= HV_OEM_BITS_GBE_DIS;
2501 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2502 oem_reg |= HV_OEM_BITS_LPLU;
2504 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2505 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2506 oem_reg |= HV_OEM_BITS_GBE_DIS;
2508 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2509 E1000_PHY_CTRL_NOND0A_LPLU))
2510 oem_reg |= HV_OEM_BITS_LPLU;
2513 /* Set Restart auto-neg to activate the bits */
2514 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2515 !hw->phy.ops.check_reset_block(hw))
2516 oem_reg |= HV_OEM_BITS_RESTART_AN;
2518 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2521 hw->phy.ops.release(hw);
2528 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2529 * @hw: pointer to the HW structure
2531 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2536 DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2538 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2542 data |= HV_KMRN_MDIO_SLOW;
2544 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2550 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2551 * done after every PHY reset.
2553 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2555 s32 ret_val = E1000_SUCCESS;
2558 DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2560 if (hw->mac.type != e1000_pchlan)
2561 return E1000_SUCCESS;
2563 /* Set MDIO slow mode before any other MDIO access */
2564 if (hw->phy.type == e1000_phy_82577) {
2565 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2570 if (((hw->phy.type == e1000_phy_82577) &&
2571 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2572 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2573 /* Disable generation of early preamble */
2574 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2578 /* Preamble tuning for SSC */
2579 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2585 if (hw->phy.type == e1000_phy_82578) {
2586 /* Return registers to default by doing a soft reset then
2587 * writing 0x3140 to the control register.
2589 if (hw->phy.revision < 2) {
2590 e1000_phy_sw_reset_generic(hw);
2591 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2597 ret_val = hw->phy.ops.acquire(hw);
2602 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2603 hw->phy.ops.release(hw);
2607 /* Configure the K1 Si workaround during phy reset assuming there is
2608 * link so that it disables K1 if link is in 1Gbps.
2610 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2614 /* Workaround for link disconnects on a busy hub in half duplex */
2615 ret_val = hw->phy.ops.acquire(hw);
2618 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2621 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2626 /* set MSE higher to enable link to stay up when noise is high */
2627 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2629 hw->phy.ops.release(hw);
2635 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2636 * @hw: pointer to the HW structure
2638 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2644 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2646 ret_val = hw->phy.ops.acquire(hw);
2649 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2653 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2654 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2655 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2656 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2657 (u16)(mac_reg & 0xFFFF));
2658 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2659 (u16)((mac_reg >> 16) & 0xFFFF));
2661 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2662 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2663 (u16)(mac_reg & 0xFFFF));
2664 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2665 (u16)((mac_reg & E1000_RAH_AV)
2669 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2672 hw->phy.ops.release(hw);
2675 #ifndef CRC32_OS_SUPPORT
2676 STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
2678 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
2679 u32 i, j, mask, crc;
2681 DEBUGFUNC("e1000_calc_rx_da_crc");
2684 for (i = 0; i < 6; i++) {
2686 for (j = 8; j > 0; j--) {
2687 mask = (crc & 1) * (-1);
2688 crc = (crc >> 1) ^ (poly & mask);
2694 #endif /* CRC32_OS_SUPPORT */
2696 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2698 * @hw: pointer to the HW structure
2699 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2701 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2703 s32 ret_val = E1000_SUCCESS;
2708 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2710 if (hw->mac.type < e1000_pch2lan)
2711 return E1000_SUCCESS;
2713 /* disable Rx path while enabling/disabling workaround */
2714 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2715 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2716 phy_reg | (1 << 14));
2721 /* Write Rx addresses (rar_entry_count for RAL/H, and
2722 * SHRAL/H) and initial CRC values to the MAC
2724 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2725 u8 mac_addr[ETH_ADDR_LEN] = {0};
2726 u32 addr_high, addr_low;
2728 addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2729 if (!(addr_high & E1000_RAH_AV))
2731 addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2732 mac_addr[0] = (addr_low & 0xFF);
2733 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2734 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2735 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2736 mac_addr[4] = (addr_high & 0xFF);
2737 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2739 #ifndef CRC32_OS_SUPPORT
2740 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2741 e1000_calc_rx_da_crc(mac_addr));
2742 #else /* CRC32_OS_SUPPORT */
2743 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2744 E1000_CRC32(ETH_ADDR_LEN, mac_addr));
2745 #endif /* CRC32_OS_SUPPORT */
2748 /* Write Rx addresses to the PHY */
2749 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2751 /* Enable jumbo frame workaround in the MAC */
2752 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2753 mac_reg &= ~(1 << 14);
2754 mac_reg |= (7 << 15);
2755 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2757 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2758 mac_reg |= E1000_RCTL_SECRC;
2759 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2761 ret_val = e1000_read_kmrn_reg_generic(hw,
2762 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2766 ret_val = e1000_write_kmrn_reg_generic(hw,
2767 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2771 ret_val = e1000_read_kmrn_reg_generic(hw,
2772 E1000_KMRNCTRLSTA_HD_CTRL,
2776 data &= ~(0xF << 8);
2778 ret_val = e1000_write_kmrn_reg_generic(hw,
2779 E1000_KMRNCTRLSTA_HD_CTRL,
2784 /* Enable jumbo frame workaround in the PHY */
2785 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2786 data &= ~(0x7F << 5);
2787 data |= (0x37 << 5);
2788 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2791 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2793 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2796 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2797 data &= ~(0x3FF << 2);
2798 data |= (E1000_TX_PTR_GAP << 2);
2799 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2802 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2805 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2806 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2811 /* Write MAC register values back to h/w defaults */
2812 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2813 mac_reg &= ~(0xF << 14);
2814 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2816 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2817 mac_reg &= ~E1000_RCTL_SECRC;
2818 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2820 ret_val = e1000_read_kmrn_reg_generic(hw,
2821 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2825 ret_val = e1000_write_kmrn_reg_generic(hw,
2826 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2830 ret_val = e1000_read_kmrn_reg_generic(hw,
2831 E1000_KMRNCTRLSTA_HD_CTRL,
2835 data &= ~(0xF << 8);
2837 ret_val = e1000_write_kmrn_reg_generic(hw,
2838 E1000_KMRNCTRLSTA_HD_CTRL,
2843 /* Write PHY register values back to h/w defaults */
2844 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2845 data &= ~(0x7F << 5);
2846 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2849 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2851 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2854 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2855 data &= ~(0x3FF << 2);
2857 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2860 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2863 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2864 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2870 /* re-enable Rx path after enabling/disabling workaround */
2871 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2876 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2877 * done after every PHY reset.
2879 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2881 s32 ret_val = E1000_SUCCESS;
2883 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2885 if (hw->mac.type != e1000_pch2lan)
2886 return E1000_SUCCESS;
2888 /* Set MDIO slow mode before any other MDIO access */
2889 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2893 ret_val = hw->phy.ops.acquire(hw);
2896 /* set MSE higher to enable link to stay up when noise is high */
2897 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2900 /* drop link after 5 times MSE threshold was reached */
2901 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2903 hw->phy.ops.release(hw);
2909 * e1000_k1_gig_workaround_lv - K1 Si workaround
2910 * @hw: pointer to the HW structure
2912 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2913 * Disable K1 for 1000 and 100 speeds
2915 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2917 s32 ret_val = E1000_SUCCESS;
2920 DEBUGFUNC("e1000_k1_workaround_lv");
2922 if (hw->mac.type != e1000_pch2lan)
2923 return E1000_SUCCESS;
2925 /* Set K1 beacon duration based on 10Mbs speed */
2926 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2930 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2931 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2933 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2936 /* LV 1G/100 Packet drop issue wa */
2937 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2941 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2942 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2948 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2949 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2950 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2951 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2959 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2960 * @hw: pointer to the HW structure
2961 * @gate: boolean set to true to gate, false to ungate
2963 * Gate/ungate the automatic PHY configuration via hardware; perform
2964 * the configuration via software instead.
2966 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2970 DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2972 if (hw->mac.type < e1000_pch2lan)
2975 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2978 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2980 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2982 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2986 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2987 * @hw: pointer to the HW structure
2989 * Check the appropriate indication the MAC has finished configuring the
2990 * PHY after a software reset.
2992 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2994 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2996 DEBUGFUNC("e1000_lan_init_done_ich8lan");
2998 /* Wait for basic configuration completes before proceeding */
3000 data = E1000_READ_REG(hw, E1000_STATUS);
3001 data &= E1000_STATUS_LAN_INIT_DONE;
3003 } while ((!data) && --loop);
3005 /* If basic configuration is incomplete before the above loop
3006 * count reaches 0, loading the configuration from NVM will
3007 * leave the PHY in a bad state possibly resulting in no link.
3010 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
3012 /* Clear the Init Done bit for the next init event */
3013 data = E1000_READ_REG(hw, E1000_STATUS);
3014 data &= ~E1000_STATUS_LAN_INIT_DONE;
3015 E1000_WRITE_REG(hw, E1000_STATUS, data);
3019 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
3020 * @hw: pointer to the HW structure
3022 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
3024 s32 ret_val = E1000_SUCCESS;
3027 DEBUGFUNC("e1000_post_phy_reset_ich8lan");
3029 if (hw->phy.ops.check_reset_block(hw))
3030 return E1000_SUCCESS;
3032 /* Allow time for h/w to get to quiescent state after reset */
3035 /* Perform any necessary post-reset workarounds */
3036 switch (hw->mac.type) {
3038 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3043 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3051 /* Clear the host wakeup bit after lcd reset */
3052 if (hw->mac.type >= e1000_pchlan) {
3053 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®);
3054 reg &= ~BM_WUC_HOST_WU_BIT;
3055 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
3058 /* Configure the LCD with the extended configuration region in NVM */
3059 ret_val = e1000_sw_lcd_config_ich8lan(hw);
3063 /* Configure the LCD with the OEM bits in NVM */
3064 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
3066 if (hw->mac.type == e1000_pch2lan) {
3067 /* Ungate automatic PHY configuration on non-managed 82579 */
3068 if (!(E1000_READ_REG(hw, E1000_FWSM) &
3069 E1000_ICH_FWSM_FW_VALID)) {
3071 e1000_gate_hw_phy_config_ich8lan(hw, false);
3074 /* Set EEE LPI Update Timer to 200usec */
3075 ret_val = hw->phy.ops.acquire(hw);
3078 ret_val = e1000_write_emi_reg_locked(hw,
3079 I82579_LPI_UPDATE_TIMER,
3081 hw->phy.ops.release(hw);
3088 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
3089 * @hw: pointer to the HW structure
3092 * This is a function pointer entry point called by drivers
3093 * or other shared routines.
3095 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
3097 s32 ret_val = E1000_SUCCESS;
3099 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
3101 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
3102 if ((hw->mac.type == e1000_pch2lan) &&
3103 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3104 e1000_gate_hw_phy_config_ich8lan(hw, true);
3106 ret_val = e1000_phy_hw_reset_generic(hw);
3110 return e1000_post_phy_reset_ich8lan(hw);
3114 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
3115 * @hw: pointer to the HW structure
3116 * @active: true to enable LPLU, false to disable
3118 * Sets the LPLU state according to the active flag. For PCH, if OEM write
3119 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
3120 * the phy speed. This function will manually set the LPLU bit and restart
3121 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
3122 * since it configures the same bit.
3124 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
3129 DEBUGFUNC("e1000_set_lplu_state_pchlan");
3130 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3135 oem_reg |= HV_OEM_BITS_LPLU;
3137 oem_reg &= ~HV_OEM_BITS_LPLU;
3139 if (!hw->phy.ops.check_reset_block(hw))
3140 oem_reg |= HV_OEM_BITS_RESTART_AN;
3142 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3146 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3147 * @hw: pointer to the HW structure
3148 * @active: true to enable LPLU, false to disable
3150 * Sets the LPLU D0 state according to the active flag. When
3151 * activating LPLU this function also disables smart speed
3152 * and vice versa. LPLU will not be activated unless the
3153 * device autonegotiation advertisement meets standards of
3154 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3155 * This is a function pointer entry point only called by
3156 * PHY setup routines.
3158 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3160 struct e1000_phy_info *phy = &hw->phy;
3162 s32 ret_val = E1000_SUCCESS;
3165 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3167 if (phy->type == e1000_phy_ife)
3168 return E1000_SUCCESS;
3170 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3173 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3174 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3176 if (phy->type != e1000_phy_igp_3)
3177 return E1000_SUCCESS;
3179 /* Call gig speed drop workaround on LPLU before accessing
3182 if (hw->mac.type == e1000_ich8lan)
3183 e1000_gig_downshift_workaround_ich8lan(hw);
3185 /* When LPLU is enabled, we should disable SmartSpeed */
3186 ret_val = phy->ops.read_reg(hw,
3187 IGP01E1000_PHY_PORT_CONFIG,
3191 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3192 ret_val = phy->ops.write_reg(hw,
3193 IGP01E1000_PHY_PORT_CONFIG,
3198 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3199 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3201 if (phy->type != e1000_phy_igp_3)
3202 return E1000_SUCCESS;
3204 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3205 * during Dx states where the power conservation is most
3206 * important. During driver activity we should enable
3207 * SmartSpeed, so performance is maintained.
3209 if (phy->smart_speed == e1000_smart_speed_on) {
3210 ret_val = phy->ops.read_reg(hw,
3211 IGP01E1000_PHY_PORT_CONFIG,
3216 data |= IGP01E1000_PSCFR_SMART_SPEED;
3217 ret_val = phy->ops.write_reg(hw,
3218 IGP01E1000_PHY_PORT_CONFIG,
3222 } else if (phy->smart_speed == e1000_smart_speed_off) {
3223 ret_val = phy->ops.read_reg(hw,
3224 IGP01E1000_PHY_PORT_CONFIG,
3229 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3230 ret_val = phy->ops.write_reg(hw,
3231 IGP01E1000_PHY_PORT_CONFIG,
3238 return E1000_SUCCESS;
3242 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3243 * @hw: pointer to the HW structure
3244 * @active: true to enable LPLU, false to disable
3246 * Sets the LPLU D3 state according to the active flag. When
3247 * activating LPLU this function also disables smart speed
3248 * and vice versa. LPLU will not be activated unless the
3249 * device autonegotiation advertisement meets standards of
3250 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3251 * This is a function pointer entry point only called by
3252 * PHY setup routines.
3254 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3256 struct e1000_phy_info *phy = &hw->phy;
3258 s32 ret_val = E1000_SUCCESS;
3261 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3263 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3266 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3267 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3269 if (phy->type != e1000_phy_igp_3)
3270 return E1000_SUCCESS;
3272 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3273 * during Dx states where the power conservation is most
3274 * important. During driver activity we should enable
3275 * SmartSpeed, so performance is maintained.
3277 if (phy->smart_speed == e1000_smart_speed_on) {
3278 ret_val = phy->ops.read_reg(hw,
3279 IGP01E1000_PHY_PORT_CONFIG,
3284 data |= IGP01E1000_PSCFR_SMART_SPEED;
3285 ret_val = phy->ops.write_reg(hw,
3286 IGP01E1000_PHY_PORT_CONFIG,
3290 } else if (phy->smart_speed == e1000_smart_speed_off) {
3291 ret_val = phy->ops.read_reg(hw,
3292 IGP01E1000_PHY_PORT_CONFIG,
3297 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3298 ret_val = phy->ops.write_reg(hw,
3299 IGP01E1000_PHY_PORT_CONFIG,
3304 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3305 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3306 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3307 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3308 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3310 if (phy->type != e1000_phy_igp_3)
3311 return E1000_SUCCESS;
3313 /* Call gig speed drop workaround on LPLU before accessing
3316 if (hw->mac.type == e1000_ich8lan)
3317 e1000_gig_downshift_workaround_ich8lan(hw);
3319 /* When LPLU is enabled, we should disable SmartSpeed */
3320 ret_val = phy->ops.read_reg(hw,
3321 IGP01E1000_PHY_PORT_CONFIG,
3326 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3327 ret_val = phy->ops.write_reg(hw,
3328 IGP01E1000_PHY_PORT_CONFIG,
3336 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3337 * @hw: pointer to the HW structure
3338 * @bank: pointer to the variable that returns the active bank
3340 * Reads signature byte from the NVM using the flash access registers.
3341 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3343 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3346 struct e1000_nvm_info *nvm = &hw->nvm;
3347 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3348 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3353 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3355 switch (hw->mac.type) {
3358 bank1_offset = nvm->flash_bank_size;
3359 act_offset = E1000_ICH_NVM_SIG_WORD;
3361 /* set bank to 0 in case flash read fails */
3365 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3369 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3370 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3371 E1000_ICH_NVM_SIG_VALUE) {
3373 return E1000_SUCCESS;
3377 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3382 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3383 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3384 E1000_ICH_NVM_SIG_VALUE) {
3386 return E1000_SUCCESS;
3389 DEBUGOUT("ERROR: No valid NVM bank present\n");
3390 return -E1000_ERR_NVM;
3393 eecd = E1000_READ_REG(hw, E1000_EECD);
3394 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3395 E1000_EECD_SEC1VAL_VALID_MASK) {
3396 if (eecd & E1000_EECD_SEC1VAL)
3401 return E1000_SUCCESS;
3403 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3406 /* set bank to 0 in case flash read fails */
3410 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3414 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3415 E1000_ICH_NVM_SIG_VALUE) {
3417 return E1000_SUCCESS;
3421 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3426 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3427 E1000_ICH_NVM_SIG_VALUE) {
3429 return E1000_SUCCESS;
3432 DEBUGOUT("ERROR: No valid NVM bank present\n");
3433 return -E1000_ERR_NVM;
3438 * e1000_read_nvm_spt - NVM access for SPT
3439 * @hw: pointer to the HW structure
3440 * @offset: The offset (in bytes) of the word(s) to read.
3441 * @words: Size of data to read in words.
3442 * @data: pointer to the word(s) to read at offset.
3444 * Reads a word(s) from the NVM
3446 STATIC s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3449 struct e1000_nvm_info *nvm = &hw->nvm;
3450 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3452 s32 ret_val = E1000_SUCCESS;
3458 DEBUGFUNC("e1000_read_nvm_spt");
3460 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3462 DEBUGOUT("nvm parameter(s) out of bounds\n");
3463 ret_val = -E1000_ERR_NVM;
3467 nvm->ops.acquire(hw);
3469 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3470 if (ret_val != E1000_SUCCESS) {
3471 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3475 act_offset = (bank) ? nvm->flash_bank_size : 0;
3476 act_offset += offset;
3478 ret_val = E1000_SUCCESS;
3480 for (i = 0; i < words; i += 2) {
3481 if (words - i == 1) {
3482 if (dev_spec->shadow_ram[offset+i].modified) {
3483 data[i] = dev_spec->shadow_ram[offset+i].value;
3485 offset_to_read = act_offset + i -
3486 ((act_offset + i) % 2);
3488 e1000_read_flash_dword_ich8lan(hw,
3493 if ((act_offset + i) % 2 == 0)
3494 data[i] = (u16)(dword & 0xFFFF);
3496 data[i] = (u16)((dword >> 16) & 0xFFFF);
3499 offset_to_read = act_offset + i;
3500 if (!(dev_spec->shadow_ram[offset+i].modified) ||
3501 !(dev_spec->shadow_ram[offset+i+1].modified)) {
3503 e1000_read_flash_dword_ich8lan(hw,
3509 if (dev_spec->shadow_ram[offset+i].modified)
3510 data[i] = dev_spec->shadow_ram[offset+i].value;
3512 data[i] = (u16) (dword & 0xFFFF);
3513 if (dev_spec->shadow_ram[offset+i].modified)
3515 dev_spec->shadow_ram[offset+i+1].value;
3517 data[i+1] = (u16) (dword >> 16 & 0xFFFF);
3521 nvm->ops.release(hw);
3525 DEBUGOUT1("NVM read error: %d\n", ret_val);
3531 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3532 * @hw: pointer to the HW structure
3533 * @offset: The offset (in bytes) of the word(s) to read.
3534 * @words: Size of data to read in words
3535 * @data: Pointer to the word(s) to read at offset.
3537 * Reads a word(s) from the NVM using the flash access registers.
3539 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3542 struct e1000_nvm_info *nvm = &hw->nvm;
3543 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3545 s32 ret_val = E1000_SUCCESS;
3549 DEBUGFUNC("e1000_read_nvm_ich8lan");
3551 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3553 DEBUGOUT("nvm parameter(s) out of bounds\n");
3554 ret_val = -E1000_ERR_NVM;
3558 nvm->ops.acquire(hw);
3560 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3561 if (ret_val != E1000_SUCCESS) {
3562 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3566 act_offset = (bank) ? nvm->flash_bank_size : 0;
3567 act_offset += offset;
3569 ret_val = E1000_SUCCESS;
3570 for (i = 0; i < words; i++) {
3571 if (dev_spec->shadow_ram[offset+i].modified) {
3572 data[i] = dev_spec->shadow_ram[offset+i].value;
3574 ret_val = e1000_read_flash_word_ich8lan(hw,
3583 nvm->ops.release(hw);
3587 DEBUGOUT1("NVM read error: %d\n", ret_val);
3593 * e1000_flash_cycle_init_ich8lan - Initialize flash
3594 * @hw: pointer to the HW structure
3596 * This function does initial flash setup so that a new read/write/erase cycle
3599 STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3601 union ich8_hws_flash_status hsfsts;
3602 s32 ret_val = -E1000_ERR_NVM;
3604 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3606 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3608 /* Check if the flash descriptor is valid */
3609 if (!hsfsts.hsf_status.fldesvalid) {
3610 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
3611 return -E1000_ERR_NVM;
3614 /* Clear FCERR and DAEL in hw status by writing 1 */
3615 hsfsts.hsf_status.flcerr = 1;
3616 hsfsts.hsf_status.dael = 1;
3617 if (hw->mac.type >= e1000_pch_spt)
3618 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3619 hsfsts.regval & 0xFFFF);
3621 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3623 /* Either we should have a hardware SPI cycle in progress
3624 * bit to check against, in order to start a new cycle or
3625 * FDONE bit should be changed in the hardware so that it
3626 * is 1 after hardware reset, which can then be used as an
3627 * indication whether a cycle is in progress or has been
3631 if (!hsfsts.hsf_status.flcinprog) {
3632 /* There is no cycle running at present,
3633 * so we can start a cycle.
3634 * Begin by setting Flash Cycle Done.
3636 hsfsts.hsf_status.flcdone = 1;
3637 if (hw->mac.type >= e1000_pch_spt)
3638 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3639 hsfsts.regval & 0xFFFF);
3641 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3643 ret_val = E1000_SUCCESS;
3647 /* Otherwise poll for sometime so the current
3648 * cycle has a chance to end before giving up.
3650 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3651 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3653 if (!hsfsts.hsf_status.flcinprog) {
3654 ret_val = E1000_SUCCESS;
3659 if (ret_val == E1000_SUCCESS) {
3660 /* Successful in waiting for previous cycle to timeout,
3661 * now set the Flash Cycle Done.
3663 hsfsts.hsf_status.flcdone = 1;
3664 if (hw->mac.type >= e1000_pch_spt)
3665 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3666 hsfsts.regval & 0xFFFF);
3668 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3671 DEBUGOUT("Flash controller busy, cannot get access\n");
3679 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3680 * @hw: pointer to the HW structure
3681 * @timeout: maximum time to wait for completion
3683 * This function starts a flash cycle and waits for its completion.
3685 STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3687 union ich8_hws_flash_ctrl hsflctl;
3688 union ich8_hws_flash_status hsfsts;
3691 DEBUGFUNC("e1000_flash_cycle_ich8lan");
3693 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3694 if (hw->mac.type >= e1000_pch_spt)
3695 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3697 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3698 hsflctl.hsf_ctrl.flcgo = 1;
3700 if (hw->mac.type >= e1000_pch_spt)
3701 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3702 hsflctl.regval << 16);
3704 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3706 /* wait till FDONE bit is set to 1 */
3708 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3709 if (hsfsts.hsf_status.flcdone)
3712 } while (i++ < timeout);
3714 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3715 return E1000_SUCCESS;
3717 return -E1000_ERR_NVM;
3721 * e1000_read_flash_dword_ich8lan - Read dword from flash
3722 * @hw: pointer to the HW structure
3723 * @offset: offset to data location
3724 * @data: pointer to the location for storing the data
3726 * Reads the flash dword at offset into data. Offset is converted
3727 * to bytes before read.
3729 STATIC s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3732 DEBUGFUNC("e1000_read_flash_dword_ich8lan");
3735 return -E1000_ERR_NVM;
3737 /* Must convert word offset into bytes. */
3740 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3744 * e1000_read_flash_word_ich8lan - Read word from flash
3745 * @hw: pointer to the HW structure
3746 * @offset: offset to data location
3747 * @data: pointer to the location for storing the data
3749 * Reads the flash word at offset into data. Offset is converted
3750 * to bytes before read.
3752 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3755 DEBUGFUNC("e1000_read_flash_word_ich8lan");
3758 return -E1000_ERR_NVM;
3760 /* Must convert offset into bytes. */
3763 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3767 * e1000_read_flash_byte_ich8lan - Read byte from flash
3768 * @hw: pointer to the HW structure
3769 * @offset: The offset of the byte to read.
3770 * @data: Pointer to a byte to store the value read.
3772 * Reads a single byte from the NVM using the flash access registers.
3774 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3780 /* In SPT, only 32 bits access is supported,
3781 * so this function should not be called.
3783 if (hw->mac.type >= e1000_pch_spt)
3784 return -E1000_ERR_NVM;
3786 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3793 return E1000_SUCCESS;
3797 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3798 * @hw: pointer to the HW structure
3799 * @offset: The offset (in bytes) of the byte or word to read.
3800 * @size: Size of data to read, 1=byte 2=word
3801 * @data: Pointer to the word to store the value read.
3803 * Reads a byte or word from the NVM using the flash access registers.
3805 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3808 union ich8_hws_flash_status hsfsts;
3809 union ich8_hws_flash_ctrl hsflctl;
3810 u32 flash_linear_addr;
3812 s32 ret_val = -E1000_ERR_NVM;
3815 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3817 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3818 return -E1000_ERR_NVM;
3819 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3820 hw->nvm.flash_base_addr);
3825 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3826 if (ret_val != E1000_SUCCESS)
3828 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3830 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3831 hsflctl.hsf_ctrl.fldbcount = size - 1;
3832 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3833 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3834 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3836 ret_val = e1000_flash_cycle_ich8lan(hw,
3837 ICH_FLASH_READ_COMMAND_TIMEOUT);
3839 /* Check if FCERR is set to 1, if set to 1, clear it
3840 * and try the whole sequence a few more times, else
3841 * read in (shift in) the Flash Data0, the order is
3842 * least significant byte first msb to lsb
3844 if (ret_val == E1000_SUCCESS) {
3845 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3847 *data = (u8)(flash_data & 0x000000FF);
3849 *data = (u16)(flash_data & 0x0000FFFF);
3852 /* If we've gotten here, then things are probably
3853 * completely hosed, but if the error condition is
3854 * detected, it won't hurt to give it another try...
3855 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3857 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3859 if (hsfsts.hsf_status.flcerr) {
3860 /* Repeat for some time before giving up. */
3862 } else if (!hsfsts.hsf_status.flcdone) {
3863 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3867 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3873 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3874 * @hw: pointer to the HW structure
3875 * @offset: The offset (in bytes) of the dword to read.
3876 * @data: Pointer to the dword to store the value read.
3878 * Reads a byte or word from the NVM using the flash access registers.
3880 STATIC s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3883 union ich8_hws_flash_status hsfsts;
3884 union ich8_hws_flash_ctrl hsflctl;
3885 u32 flash_linear_addr;
3886 s32 ret_val = -E1000_ERR_NVM;
3889 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3891 if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3892 hw->mac.type < e1000_pch_spt)
3893 return -E1000_ERR_NVM;
3894 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3895 hw->nvm.flash_base_addr);
3900 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3901 if (ret_val != E1000_SUCCESS)
3903 /* In SPT, This register is in Lan memory space, not flash.
3904 * Therefore, only 32 bit access is supported
3906 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3908 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3909 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3910 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3911 /* In SPT, This register is in Lan memory space, not flash.
3912 * Therefore, only 32 bit access is supported
3914 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3915 (u32)hsflctl.regval << 16);
3916 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3918 ret_val = e1000_flash_cycle_ich8lan(hw,
3919 ICH_FLASH_READ_COMMAND_TIMEOUT);
3921 /* Check if FCERR is set to 1, if set to 1, clear it
3922 * and try the whole sequence a few more times, else
3923 * read in (shift in) the Flash Data0, the order is
3924 * least significant byte first msb to lsb
3926 if (ret_val == E1000_SUCCESS) {
3927 *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3930 /* If we've gotten here, then things are probably
3931 * completely hosed, but if the error condition is
3932 * detected, it won't hurt to give it another try...
3933 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3935 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3937 if (hsfsts.hsf_status.flcerr) {
3938 /* Repeat for some time before giving up. */
3940 } else if (!hsfsts.hsf_status.flcdone) {
3941 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3945 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3951 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3952 * @hw: pointer to the HW structure
3953 * @offset: The offset (in bytes) of the word(s) to write.
3954 * @words: Size of data to write in words
3955 * @data: Pointer to the word(s) to write at offset.
3957 * Writes a byte or word to the NVM using the flash access registers.
3959 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3962 struct e1000_nvm_info *nvm = &hw->nvm;
3963 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3966 DEBUGFUNC("e1000_write_nvm_ich8lan");
3968 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3970 DEBUGOUT("nvm parameter(s) out of bounds\n");
3971 return -E1000_ERR_NVM;
3974 nvm->ops.acquire(hw);
3976 for (i = 0; i < words; i++) {
3977 dev_spec->shadow_ram[offset+i].modified = true;
3978 dev_spec->shadow_ram[offset+i].value = data[i];
3981 nvm->ops.release(hw);
3983 return E1000_SUCCESS;
3987 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3988 * @hw: pointer to the HW structure
3990 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3991 * which writes the checksum to the shadow ram. The changes in the shadow
3992 * ram are then committed to the EEPROM by processing each bank at a time
3993 * checking for the modified bit and writing only the pending changes.
3994 * After a successful commit, the shadow ram is cleared and is ready for
3997 STATIC s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3999 struct e1000_nvm_info *nvm = &hw->nvm;
4000 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4001 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4005 DEBUGFUNC("e1000_update_nvm_checksum_spt");
4007 ret_val = e1000_update_nvm_checksum_generic(hw);
4011 if (nvm->type != e1000_nvm_flash_sw)
4014 nvm->ops.acquire(hw);
4016 /* We're writing to the opposite bank so if we're on bank 1,
4017 * write to bank 0 etc. We also need to erase the segment that
4018 * is going to be written
4020 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4021 if (ret_val != E1000_SUCCESS) {
4022 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4027 new_bank_offset = nvm->flash_bank_size;
4028 old_bank_offset = 0;
4029 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4033 old_bank_offset = nvm->flash_bank_size;
4034 new_bank_offset = 0;
4035 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4039 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {
4040 /* Determine whether to write the value stored
4041 * in the other NVM bank or a modified value stored
4044 ret_val = e1000_read_flash_dword_ich8lan(hw,
4045 i + old_bank_offset,
4048 if (dev_spec->shadow_ram[i].modified) {
4049 dword &= 0xffff0000;
4050 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
4052 if (dev_spec->shadow_ram[i + 1].modified) {
4053 dword &= 0x0000ffff;
4054 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
4060 /* If the word is 0x13, then make sure the signature bits
4061 * (15:14) are 11b until the commit has completed.
4062 * This will allow us to write 10b which indicates the
4063 * signature is valid. We want to do this after the write
4064 * has completed so that we don't mark the segment valid
4065 * while the write is still in progress
4067 if (i == E1000_ICH_NVM_SIG_WORD - 1)
4068 dword |= E1000_ICH_NVM_SIG_MASK << 16;
4070 /* Convert offset to bytes. */
4071 act_offset = (i + new_bank_offset) << 1;
4075 /* Write the data to the new bank. Offset in words*/
4076 act_offset = i + new_bank_offset;
4077 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4083 /* Don't bother writing the segment valid bits if sector
4084 * programming failed.
4087 DEBUGOUT("Flash commit failed.\n");
4091 /* Finally validate the new segment by setting bit 15:14
4092 * to 10b in word 0x13 , this can be done without an
4093 * erase as well since these bits are 11 to start with
4094 * and we need to change bit 14 to 0b
4096 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4098 /*offset in words but we read dword*/
4100 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4105 dword &= 0xBFFFFFFF;
4106 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4111 /* And invalidate the previously valid segment by setting
4112 * its signature word (0x13) high_byte to 0b. This can be
4113 * done without an erase because flash erase sets all bits
4114 * to 1's. We can write 1's to 0's without an erase
4116 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4118 /* offset in words but we read dword*/
4119 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
4120 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4125 dword &= 0x00FFFFFF;
4126 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4131 /* Great! Everything worked, we can now clear the cached entries. */
4132 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4133 dev_spec->shadow_ram[i].modified = false;
4134 dev_spec->shadow_ram[i].value = 0xFFFF;
4138 nvm->ops.release(hw);
4140 /* Reload the EEPROM, or else modifications will not appear
4141 * until after the next adapter reset.
4144 nvm->ops.reload(hw);
4150 DEBUGOUT1("NVM update error: %d\n", ret_val);
4156 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
4157 * @hw: pointer to the HW structure
4159 * The NVM checksum is updated by calling the generic update_nvm_checksum,
4160 * which writes the checksum to the shadow ram. The changes in the shadow
4161 * ram are then committed to the EEPROM by processing each bank at a time
4162 * checking for the modified bit and writing only the pending changes.
4163 * After a successful commit, the shadow ram is cleared and is ready for
4166 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
4168 struct e1000_nvm_info *nvm = &hw->nvm;
4169 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4170 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4174 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
4176 ret_val = e1000_update_nvm_checksum_generic(hw);
4180 if (nvm->type != e1000_nvm_flash_sw)
4183 nvm->ops.acquire(hw);
4185 /* We're writing to the opposite bank so if we're on bank 1,
4186 * write to bank 0 etc. We also need to erase the segment that
4187 * is going to be written
4189 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4190 if (ret_val != E1000_SUCCESS) {
4191 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4196 new_bank_offset = nvm->flash_bank_size;
4197 old_bank_offset = 0;
4198 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4202 old_bank_offset = nvm->flash_bank_size;
4203 new_bank_offset = 0;
4204 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4208 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4209 if (dev_spec->shadow_ram[i].modified) {
4210 data = dev_spec->shadow_ram[i].value;
4212 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4218 /* If the word is 0x13, then make sure the signature bits
4219 * (15:14) are 11b until the commit has completed.
4220 * This will allow us to write 10b which indicates the
4221 * signature is valid. We want to do this after the write
4222 * has completed so that we don't mark the segment valid
4223 * while the write is still in progress
4225 if (i == E1000_ICH_NVM_SIG_WORD)
4226 data |= E1000_ICH_NVM_SIG_MASK;
4228 /* Convert offset to bytes. */
4229 act_offset = (i + new_bank_offset) << 1;
4233 /* Write the bytes to the new bank. */
4234 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4241 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4248 /* Don't bother writing the segment valid bits if sector
4249 * programming failed.
4252 DEBUGOUT("Flash commit failed.\n");
4256 /* Finally validate the new segment by setting bit 15:14
4257 * to 10b in word 0x13 , this can be done without an
4258 * erase as well since these bits are 11 to start with
4259 * and we need to change bit 14 to 0b
4261 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4262 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4267 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4272 /* And invalidate the previously valid segment by setting
4273 * its signature word (0x13) high_byte to 0b. This can be
4274 * done without an erase because flash erase sets all bits
4275 * to 1's. We can write 1's to 0's without an erase
4277 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4279 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4284 /* Great! Everything worked, we can now clear the cached entries. */
4285 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4286 dev_spec->shadow_ram[i].modified = false;
4287 dev_spec->shadow_ram[i].value = 0xFFFF;
4291 nvm->ops.release(hw);
4293 /* Reload the EEPROM, or else modifications will not appear
4294 * until after the next adapter reset.
4297 nvm->ops.reload(hw);
4303 DEBUGOUT1("NVM update error: %d\n", ret_val);
4309 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4310 * @hw: pointer to the HW structure
4312 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4313 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4314 * calculated, in which case we need to calculate the checksum and set bit 6.
4316 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4321 u16 valid_csum_mask;
4323 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
4325 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4326 * the checksum needs to be fixed. This bit is an indication that
4327 * the NVM was prepared by OEM software and did not calculate
4328 * the checksum...a likely scenario.
4330 switch (hw->mac.type) {
4335 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4338 word = NVM_FUTURE_INIT_WORD1;
4339 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4343 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4347 if (!(data & valid_csum_mask)) {
4348 data |= valid_csum_mask;
4349 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4352 ret_val = hw->nvm.ops.update(hw);
4357 return e1000_validate_nvm_checksum_generic(hw);
4361 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4362 * @hw: pointer to the HW structure
4363 * @offset: The offset (in bytes) of the byte/word to read.
4364 * @size: Size of data to read, 1=byte 2=word
4365 * @data: The byte(s) to write to the NVM.
4367 * Writes one/two bytes to the NVM using the flash access registers.
4369 STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4372 union ich8_hws_flash_status hsfsts;
4373 union ich8_hws_flash_ctrl hsflctl;
4374 u32 flash_linear_addr;
4379 DEBUGFUNC("e1000_write_ich8_data");
4381 if (hw->mac.type >= e1000_pch_spt) {
4382 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4383 return -E1000_ERR_NVM;
4385 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4386 return -E1000_ERR_NVM;
4389 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4390 hw->nvm.flash_base_addr);
4395 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4396 if (ret_val != E1000_SUCCESS)
4398 /* In SPT, This register is in Lan memory space, not
4399 * flash. Therefore, only 32 bit access is supported
4401 if (hw->mac.type >= e1000_pch_spt)
4403 E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4406 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4408 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4409 hsflctl.hsf_ctrl.fldbcount = size - 1;
4410 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4411 /* In SPT, This register is in Lan memory space,
4412 * not flash. Therefore, only 32 bit access is
4415 if (hw->mac.type >= e1000_pch_spt)
4416 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4417 hsflctl.regval << 16);
4419 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4422 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4425 flash_data = (u32)data & 0x00FF;
4427 flash_data = (u32)data;
4429 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
4431 /* check if FCERR is set to 1 , if set to 1, clear it
4432 * and try the whole sequence a few more times else done
4435 e1000_flash_cycle_ich8lan(hw,
4436 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4437 if (ret_val == E1000_SUCCESS)
4440 /* If we're here, then things are most likely
4441 * completely hosed, but if the error condition
4442 * is detected, it won't hurt to give it another
4443 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4445 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4446 if (hsfsts.hsf_status.flcerr)
4447 /* Repeat for some time before giving up. */
4449 if (!hsfsts.hsf_status.flcdone) {
4450 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4453 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4459 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4460 * @hw: pointer to the HW structure
4461 * @offset: The offset (in bytes) of the dwords to read.
4462 * @data: The 4 bytes to write to the NVM.
4464 * Writes one/two/four bytes to the NVM using the flash access registers.
4466 STATIC s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4469 union ich8_hws_flash_status hsfsts;
4470 union ich8_hws_flash_ctrl hsflctl;
4471 u32 flash_linear_addr;
4475 DEBUGFUNC("e1000_write_flash_data32_ich8lan");
4477 if (hw->mac.type >= e1000_pch_spt) {
4478 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4479 return -E1000_ERR_NVM;
4481 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4482 hw->nvm.flash_base_addr);
4486 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4487 if (ret_val != E1000_SUCCESS)
4490 /* In SPT, This register is in Lan memory space, not
4491 * flash. Therefore, only 32 bit access is supported
4493 if (hw->mac.type >= e1000_pch_spt)
4494 hsflctl.regval = E1000_READ_FLASH_REG(hw,
4498 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4501 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4502 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4504 /* In SPT, This register is in Lan memory space,
4505 * not flash. Therefore, only 32 bit access is
4508 if (hw->mac.type >= e1000_pch_spt)
4509 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4510 hsflctl.regval << 16);
4512 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4515 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4517 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
4519 /* check if FCERR is set to 1 , if set to 1, clear it
4520 * and try the whole sequence a few more times else done
4522 ret_val = e1000_flash_cycle_ich8lan(hw,
4523 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4525 if (ret_val == E1000_SUCCESS)
4528 /* If we're here, then things are most likely
4529 * completely hosed, but if the error condition
4530 * is detected, it won't hurt to give it another
4531 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4533 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4535 if (hsfsts.hsf_status.flcerr)
4536 /* Repeat for some time before giving up. */
4538 if (!hsfsts.hsf_status.flcdone) {
4539 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4542 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4548 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4549 * @hw: pointer to the HW structure
4550 * @offset: The index of the byte to read.
4551 * @data: The byte to write to the NVM.
4553 * Writes a single byte to the NVM using the flash access registers.
4555 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4558 u16 word = (u16)data;
4560 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
4562 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4566 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4567 * @hw: pointer to the HW structure
4568 * @offset: The offset of the word to write.
4569 * @dword: The dword to write to the NVM.
4571 * Writes a single dword to the NVM using the flash access registers.
4572 * Goes through a retry algorithm before giving up.
4574 STATIC s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4575 u32 offset, u32 dword)
4578 u16 program_retries;
4580 DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan");
4582 /* Must convert word offset into bytes. */
4585 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4589 for (program_retries = 0; program_retries < 100; program_retries++) {
4590 DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset);
4592 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4593 if (ret_val == E1000_SUCCESS)
4596 if (program_retries == 100)
4597 return -E1000_ERR_NVM;
4599 return E1000_SUCCESS;
4603 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4604 * @hw: pointer to the HW structure
4605 * @offset: The offset of the byte to write.
4606 * @byte: The byte to write to the NVM.
4608 * Writes a single byte to the NVM using the flash access registers.
4609 * Goes through a retry algorithm before giving up.
4611 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4612 u32 offset, u8 byte)
4615 u16 program_retries;
4617 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
4619 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4623 for (program_retries = 0; program_retries < 100; program_retries++) {
4624 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
4626 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4627 if (ret_val == E1000_SUCCESS)
4630 if (program_retries == 100)
4631 return -E1000_ERR_NVM;
4633 return E1000_SUCCESS;
4637 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4638 * @hw: pointer to the HW structure
4639 * @bank: 0 for first bank, 1 for second bank, etc.
4641 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4642 * bank N is 4096 * N + flash_reg_addr.
4644 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4646 struct e1000_nvm_info *nvm = &hw->nvm;
4647 union ich8_hws_flash_status hsfsts;
4648 union ich8_hws_flash_ctrl hsflctl;
4649 u32 flash_linear_addr;
4650 /* bank size is in 16bit words - adjust to bytes */
4651 u32 flash_bank_size = nvm->flash_bank_size * 2;
4654 s32 j, iteration, sector_size;
4656 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
4658 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4660 /* Determine HW Sector size: Read BERASE bits of hw flash status
4662 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4663 * consecutive sectors. The start index for the nth Hw sector
4664 * can be calculated as = bank * 4096 + n * 256
4665 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4666 * The start index for the nth Hw sector can be calculated
4668 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4669 * (ich9 only, otherwise error condition)
4670 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4672 switch (hsfsts.hsf_status.berasesz) {
4674 /* Hw sector size 256 */
4675 sector_size = ICH_FLASH_SEG_SIZE_256;
4676 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4679 sector_size = ICH_FLASH_SEG_SIZE_4K;
4683 sector_size = ICH_FLASH_SEG_SIZE_8K;
4687 sector_size = ICH_FLASH_SEG_SIZE_64K;
4691 return -E1000_ERR_NVM;
4694 /* Start with the base address, then add the sector offset. */
4695 flash_linear_addr = hw->nvm.flash_base_addr;
4696 flash_linear_addr += (bank) ? flash_bank_size : 0;
4698 for (j = 0; j < iteration; j++) {
4700 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4703 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4707 /* Write a value 11 (block Erase) in Flash
4708 * Cycle field in hw flash control
4710 if (hw->mac.type >= e1000_pch_spt)
4712 E1000_READ_FLASH_REG(hw,
4713 ICH_FLASH_HSFSTS)>>16;
4716 E1000_READ_FLASH_REG16(hw,
4719 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4720 if (hw->mac.type >= e1000_pch_spt)
4721 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4722 hsflctl.regval << 16);
4724 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4727 /* Write the last 24 bits of an index within the
4728 * block into Flash Linear address field in Flash
4731 flash_linear_addr += (j * sector_size);
4732 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4735 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4736 if (ret_val == E1000_SUCCESS)
4739 /* Check if FCERR is set to 1. If 1,
4740 * clear it and try the whole sequence
4741 * a few more times else Done
4743 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4745 if (hsfsts.hsf_status.flcerr)
4746 /* repeat for some time before giving up */
4748 else if (!hsfsts.hsf_status.flcdone)
4750 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4753 return E1000_SUCCESS;
4757 * e1000_valid_led_default_ich8lan - Set the default LED settings
4758 * @hw: pointer to the HW structure
4759 * @data: Pointer to the LED settings
4761 * Reads the LED default settings from the NVM to data. If the NVM LED
4762 * settings is all 0's or F's, set the LED default to a valid LED default
4765 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4769 DEBUGFUNC("e1000_valid_led_default_ich8lan");
4771 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4773 DEBUGOUT("NVM Read Error\n");
4777 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4778 *data = ID_LED_DEFAULT_ICH8LAN;
4780 return E1000_SUCCESS;
4784 * e1000_id_led_init_pchlan - store LED configurations
4785 * @hw: pointer to the HW structure
4787 * PCH does not control LEDs via the LEDCTL register, rather it uses
4788 * the PHY LED configuration register.
4790 * PCH also does not have an "always on" or "always off" mode which
4791 * complicates the ID feature. Instead of using the "on" mode to indicate
4792 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4793 * use "link_up" mode. The LEDs will still ID on request if there is no
4794 * link based on logic in e1000_led_[on|off]_pchlan().
4796 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4798 struct e1000_mac_info *mac = &hw->mac;
4800 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4801 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4802 u16 data, i, temp, shift;
4804 DEBUGFUNC("e1000_id_led_init_pchlan");
4806 /* Get default ID LED modes */
4807 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4811 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4812 mac->ledctl_mode1 = mac->ledctl_default;
4813 mac->ledctl_mode2 = mac->ledctl_default;
4815 for (i = 0; i < 4; i++) {
4816 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4819 case ID_LED_ON1_DEF2:
4820 case ID_LED_ON1_ON2:
4821 case ID_LED_ON1_OFF2:
4822 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4823 mac->ledctl_mode1 |= (ledctl_on << shift);
4825 case ID_LED_OFF1_DEF2:
4826 case ID_LED_OFF1_ON2:
4827 case ID_LED_OFF1_OFF2:
4828 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4829 mac->ledctl_mode1 |= (ledctl_off << shift);
4836 case ID_LED_DEF1_ON2:
4837 case ID_LED_ON1_ON2:
4838 case ID_LED_OFF1_ON2:
4839 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4840 mac->ledctl_mode2 |= (ledctl_on << shift);
4842 case ID_LED_DEF1_OFF2:
4843 case ID_LED_ON1_OFF2:
4844 case ID_LED_OFF1_OFF2:
4845 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4846 mac->ledctl_mode2 |= (ledctl_off << shift);
4854 return E1000_SUCCESS;
4858 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4859 * @hw: pointer to the HW structure
4861 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4862 * register, so the bus width is hard coded.
4864 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4866 struct e1000_bus_info *bus = &hw->bus;
4869 DEBUGFUNC("e1000_get_bus_info_ich8lan");
4871 ret_val = e1000_get_bus_info_pcie_generic(hw);
4873 /* ICH devices are "PCI Express"-ish. They have
4874 * a configuration space, but do not contain
4875 * PCI Express Capability registers, so bus width
4876 * must be hardcoded.
4878 if (bus->width == e1000_bus_width_unknown)
4879 bus->width = e1000_bus_width_pcie_x1;
4885 * e1000_reset_hw_ich8lan - Reset the hardware
4886 * @hw: pointer to the HW structure
4888 * Does a full reset of the hardware which includes a reset of the PHY and
4891 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4893 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4898 DEBUGFUNC("e1000_reset_hw_ich8lan");
4900 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4901 * on the last TLP read/write transaction when MAC is reset.
4903 ret_val = e1000_disable_pcie_master_generic(hw);
4905 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4907 DEBUGOUT("Masking off all interrupts\n");
4908 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4910 /* Disable the Transmit and Receive units. Then delay to allow
4911 * any pending transactions to complete before we hit the MAC
4912 * with the global reset.
4914 E1000_WRITE_REG(hw, E1000_RCTL, 0);
4915 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4916 E1000_WRITE_FLUSH(hw);
4920 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4921 if (hw->mac.type == e1000_ich8lan) {
4922 /* Set Tx and Rx buffer allocation to 8k apiece. */
4923 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4924 /* Set Packet Buffer Size to 16k. */
4925 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4928 if (hw->mac.type == e1000_pchlan) {
4929 /* Save the NVM K1 bit setting*/
4930 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4934 if (kum_cfg & E1000_NVM_K1_ENABLE)
4935 dev_spec->nvm_k1_enabled = true;
4937 dev_spec->nvm_k1_enabled = false;
4940 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4942 if (!hw->phy.ops.check_reset_block(hw)) {
4943 /* Full-chip reset requires MAC and PHY reset at the same
4944 * time to make sure the interface between MAC and the
4945 * external PHY is reset.
4947 ctrl |= E1000_CTRL_PHY_RST;
4949 /* Gate automatic PHY configuration by hardware on
4952 if ((hw->mac.type == e1000_pch2lan) &&
4953 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4954 e1000_gate_hw_phy_config_ich8lan(hw, true);
4956 ret_val = e1000_acquire_swflag_ich8lan(hw);
4957 DEBUGOUT("Issuing a global reset to ich8lan\n");
4958 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4959 /* cannot issue a flush here because it hangs the hardware */
4962 /* Set Phy Config Counter to 50msec */
4963 if (hw->mac.type == e1000_pch2lan) {
4964 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4965 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4966 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4967 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4971 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4973 if (ctrl & E1000_CTRL_PHY_RST) {
4974 ret_val = hw->phy.ops.get_cfg_done(hw);
4978 ret_val = e1000_post_phy_reset_ich8lan(hw);
4983 /* For PCH, this write will make sure that any noise
4984 * will be detected as a CRC error and be dropped rather than show up
4985 * as a bad packet to the DMA engine.
4987 if (hw->mac.type == e1000_pchlan)
4988 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
4990 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4991 E1000_READ_REG(hw, E1000_ICR);
4993 reg = E1000_READ_REG(hw, E1000_KABGTXD);
4994 reg |= E1000_KABGTXD_BGSQLBIAS;
4995 E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
4997 return E1000_SUCCESS;
5001 * e1000_init_hw_ich8lan - Initialize the hardware
5002 * @hw: pointer to the HW structure
5004 * Prepares the hardware for transmit and receive by doing the following:
5005 * - initialize hardware bits
5006 * - initialize LED identification
5007 * - setup receive address registers
5008 * - setup flow control
5009 * - setup transmit descriptors
5010 * - clear statistics
5012 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
5014 struct e1000_mac_info *mac = &hw->mac;
5015 u32 ctrl_ext, txdctl, snoop;
5019 DEBUGFUNC("e1000_init_hw_ich8lan");
5021 e1000_initialize_hw_bits_ich8lan(hw);
5023 /* Initialize identification LED */
5024 ret_val = mac->ops.id_led_init(hw);
5025 /* An error is not fatal and we should not stop init due to this */
5027 DEBUGOUT("Error initializing identification LED\n");
5029 /* Setup the receive address. */
5030 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
5032 /* Zero out the Multicast HASH table */
5033 DEBUGOUT("Zeroing the MTA\n");
5034 for (i = 0; i < mac->mta_reg_count; i++)
5035 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
5037 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
5038 * the ME. Disable wakeup by clearing the host wakeup bit.
5039 * Reset the phy after disabling host wakeup to reset the Rx buffer.
5041 if (hw->phy.type == e1000_phy_82578) {
5042 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
5043 i &= ~BM_WUC_HOST_WU_BIT;
5044 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
5045 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5050 /* Setup link and flow control */
5051 ret_val = mac->ops.setup_link(hw);
5053 /* Set the transmit descriptor write-back policy for both queues */
5054 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
5055 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5056 E1000_TXDCTL_FULL_TX_DESC_WB);
5057 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5058 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5059 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
5060 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
5061 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5062 E1000_TXDCTL_FULL_TX_DESC_WB);
5063 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5064 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5065 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
5067 /* ICH8 has opposite polarity of no_snoop bits.
5068 * By default, we should use snoop behavior.
5070 if (mac->type == e1000_ich8lan)
5071 snoop = PCIE_ICH8_SNOOP_ALL;
5073 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
5074 e1000_set_pcie_no_snoop_generic(hw, snoop);
5076 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5077 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
5078 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5080 /* Clear all of the statistics registers (clear on read). It is
5081 * important that we do this after we have tried to establish link
5082 * because the symbol error count will increment wildly if there
5085 e1000_clear_hw_cntrs_ich8lan(hw);
5091 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
5092 * @hw: pointer to the HW structure
5094 * Sets/Clears required hardware bits necessary for correctly setting up the
5095 * hardware for transmit and receive.
5097 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
5101 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
5103 /* Extended Device Control */
5104 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
5106 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
5107 if (hw->mac.type >= e1000_pchlan)
5108 reg |= E1000_CTRL_EXT_PHYPDEN;
5109 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
5111 /* Transmit Descriptor Control 0 */
5112 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
5114 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
5116 /* Transmit Descriptor Control 1 */
5117 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
5119 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
5121 /* Transmit Arbitration Control 0 */
5122 reg = E1000_READ_REG(hw, E1000_TARC(0));
5123 if (hw->mac.type == e1000_ich8lan)
5124 reg |= (1 << 28) | (1 << 29);
5125 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
5126 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
5128 /* Transmit Arbitration Control 1 */
5129 reg = E1000_READ_REG(hw, E1000_TARC(1));
5130 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
5134 reg |= (1 << 24) | (1 << 26) | (1 << 30);
5135 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
5138 if (hw->mac.type == e1000_ich8lan) {
5139 reg = E1000_READ_REG(hw, E1000_STATUS);
5141 E1000_WRITE_REG(hw, E1000_STATUS, reg);
5144 /* work-around descriptor data corruption issue during nfs v2 udp
5145 * traffic, just disable the nfs filtering capability
5147 reg = E1000_READ_REG(hw, E1000_RFCTL);
5148 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
5150 /* Disable IPv6 extension header parsing because some malformed
5151 * IPv6 headers can hang the Rx.
5153 if (hw->mac.type == e1000_ich8lan)
5154 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
5155 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
5157 /* Enable ECC on Lynxpoint */
5158 if (hw->mac.type >= e1000_pch_lpt) {
5159 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
5160 reg |= E1000_PBECCSTS_ECC_ENABLE;
5161 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
5163 reg = E1000_READ_REG(hw, E1000_CTRL);
5164 reg |= E1000_CTRL_MEHE;
5165 E1000_WRITE_REG(hw, E1000_CTRL, reg);
5172 * e1000_setup_link_ich8lan - Setup flow control and link settings
5173 * @hw: pointer to the HW structure
5175 * Determines which flow control settings to use, then configures flow
5176 * control. Calls the appropriate media-specific link configuration
5177 * function. Assuming the adapter has a valid link partner, a valid link
5178 * should be established. Assumes the hardware has previously been reset
5179 * and the transmitter and receiver are not enabled.
5181 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5185 DEBUGFUNC("e1000_setup_link_ich8lan");
5187 if (hw->phy.ops.check_reset_block(hw))
5188 return E1000_SUCCESS;
5190 /* ICH parts do not have a word in the NVM to determine
5191 * the default flow control setting, so we explicitly
5194 if (hw->fc.requested_mode == e1000_fc_default)
5195 hw->fc.requested_mode = e1000_fc_full;
5197 /* Save off the requested flow control mode for use later. Depending
5198 * on the link partner's capabilities, we may or may not use this mode.
5200 hw->fc.current_mode = hw->fc.requested_mode;
5202 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
5203 hw->fc.current_mode);
5205 /* Continue to configure the copper link. */
5206 ret_val = hw->mac.ops.setup_physical_interface(hw);
5210 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
5211 if ((hw->phy.type == e1000_phy_82578) ||
5212 (hw->phy.type == e1000_phy_82579) ||
5213 (hw->phy.type == e1000_phy_i217) ||
5214 (hw->phy.type == e1000_phy_82577)) {
5215 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
5217 ret_val = hw->phy.ops.write_reg(hw,
5218 PHY_REG(BM_PORT_CTRL_PAGE, 27),
5224 return e1000_set_fc_watermarks_generic(hw);
5228 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5229 * @hw: pointer to the HW structure
5231 * Configures the kumeran interface to the PHY to wait the appropriate time
5232 * when polling the PHY, then call the generic setup_copper_link to finish
5233 * configuring the copper link.
5235 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5241 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
5243 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5244 ctrl |= E1000_CTRL_SLU;
5245 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5246 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5248 /* Set the mac to wait the maximum time between each iteration
5249 * and increase the max iterations when polling the phy;
5250 * this fixes erroneous timeouts at 10Mbps.
5252 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5256 ret_val = e1000_read_kmrn_reg_generic(hw,
5257 E1000_KMRNCTRLSTA_INBAND_PARAM,
5262 ret_val = e1000_write_kmrn_reg_generic(hw,
5263 E1000_KMRNCTRLSTA_INBAND_PARAM,
5268 switch (hw->phy.type) {
5269 case e1000_phy_igp_3:
5270 ret_val = e1000_copper_link_setup_igp(hw);
5275 case e1000_phy_82578:
5276 ret_val = e1000_copper_link_setup_m88(hw);
5280 case e1000_phy_82577:
5281 case e1000_phy_82579:
5282 ret_val = e1000_copper_link_setup_82577(hw);
5287 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5292 reg_data &= ~IFE_PMC_AUTO_MDIX;
5294 switch (hw->phy.mdix) {
5296 reg_data &= ~IFE_PMC_FORCE_MDIX;
5299 reg_data |= IFE_PMC_FORCE_MDIX;
5303 reg_data |= IFE_PMC_AUTO_MDIX;
5306 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5315 return e1000_setup_copper_link_generic(hw);
5319 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5320 * @hw: pointer to the HW structure
5322 * Calls the PHY specific link setup function and then calls the
5323 * generic setup_copper_link to finish configuring the link for
5324 * Lynxpoint PCH devices
5326 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5331 DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
5333 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5334 ctrl |= E1000_CTRL_SLU;
5335 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5336 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5338 ret_val = e1000_copper_link_setup_82577(hw);
5342 return e1000_setup_copper_link_generic(hw);
5346 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5347 * @hw: pointer to the HW structure
5348 * @speed: pointer to store current link speed
5349 * @duplex: pointer to store the current link duplex
5351 * Calls the generic get_speed_and_duplex to retrieve the current link
5352 * information and then calls the Kumeran lock loss workaround for links at
5355 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5360 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
5362 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5366 if ((hw->mac.type == e1000_ich8lan) &&
5367 (hw->phy.type == e1000_phy_igp_3) &&
5368 (*speed == SPEED_1000)) {
5369 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5376 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5377 * @hw: pointer to the HW structure
5379 * Work-around for 82566 Kumeran PCS lock loss:
5380 * On link status change (i.e. PCI reset, speed change) and link is up and
5382 * 0) if workaround is optionally disabled do nothing
5383 * 1) wait 1ms for Kumeran link to come up
5384 * 2) check Kumeran Diagnostic register PCS lock loss bit
5385 * 3) if not set the link is locked (all is good), otherwise...
5387 * 5) repeat up to 10 times
5388 * Note: this is only called for IGP3 copper when speed is 1gb.
5390 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5392 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5398 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
5400 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5401 return E1000_SUCCESS;
5403 /* Make sure link is up before proceeding. If not just return.
5404 * Attempting this while link is negotiating fouled up link
5407 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5409 return E1000_SUCCESS;
5411 for (i = 0; i < 10; i++) {
5412 /* read once to clear */
5413 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5416 /* and again to get new status */
5417 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5421 /* check for PCS lock */
5422 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5423 return E1000_SUCCESS;
5425 /* Issue PHY reset */
5426 hw->phy.ops.reset(hw);
5429 /* Disable GigE link negotiation */
5430 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5431 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5432 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5433 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5435 /* Call gig speed drop workaround on Gig disable before accessing
5438 e1000_gig_downshift_workaround_ich8lan(hw);
5440 /* unable to acquire PCS lock */
5441 return -E1000_ERR_PHY;
5445 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5446 * @hw: pointer to the HW structure
5447 * @state: boolean value used to set the current Kumeran workaround state
5449 * If ICH8, set the current Kumeran workaround state (enabled - true
5450 * /disabled - false).
5452 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5455 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5457 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
5459 if (hw->mac.type != e1000_ich8lan) {
5460 DEBUGOUT("Workaround applies to ICH8 only.\n");
5464 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5470 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5471 * @hw: pointer to the HW structure
5473 * Workaround for 82566 power-down on D3 entry:
5474 * 1) disable gigabit link
5475 * 2) write VR power-down enable
5477 * Continue if successful, else issue LCD reset and repeat
5479 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5485 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
5487 if (hw->phy.type != e1000_phy_igp_3)
5490 /* Try the workaround twice (if needed) */
5493 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
5494 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5495 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5496 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
5498 /* Call gig speed drop workaround on Gig disable before
5499 * accessing any PHY registers
5501 if (hw->mac.type == e1000_ich8lan)
5502 e1000_gig_downshift_workaround_ich8lan(hw);
5504 /* Write VR power-down enable */
5505 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5506 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5507 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
5508 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5510 /* Read it back and test */
5511 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5512 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5513 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5516 /* Issue PHY reset and repeat at most one more time */
5517 reg = E1000_READ_REG(hw, E1000_CTRL);
5518 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
5524 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5525 * @hw: pointer to the HW structure
5527 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5528 * LPLU, Gig disable, MDIC PHY reset):
5529 * 1) Set Kumeran Near-end loopback
5530 * 2) Clear Kumeran Near-end loopback
5531 * Should only be called for ICH8[m] devices with any 1G Phy.
5533 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5538 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
5540 if ((hw->mac.type != e1000_ich8lan) ||
5541 (hw->phy.type == e1000_phy_ife))
5544 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5548 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5549 ret_val = e1000_write_kmrn_reg_generic(hw,
5550 E1000_KMRNCTRLSTA_DIAG_OFFSET,
5554 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5555 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5560 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5561 * @hw: pointer to the HW structure
5563 * During S0 to Sx transition, it is possible the link remains at gig
5564 * instead of negotiating to a lower speed. Before going to Sx, set
5565 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5566 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5567 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5568 * needs to be written.
5569 * Parts that support (and are linked to a partner which support) EEE in
5570 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5571 * than 10Mbps w/o EEE.
5573 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5575 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5579 DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
5581 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5582 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5584 if (hw->phy.type == e1000_phy_i217) {
5585 u16 phy_reg, device_id = hw->device_id;
5587 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5588 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5589 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5590 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5591 (hw->mac.type >= e1000_pch_spt)) {
5592 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
5594 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
5595 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5598 ret_val = hw->phy.ops.acquire(hw);
5602 if (!dev_spec->eee_disable) {
5606 e1000_read_emi_reg_locked(hw,
5607 I217_EEE_ADVERTISEMENT,
5612 /* Disable LPLU if both link partners support 100BaseT
5613 * EEE and 100Full is advertised on both ends of the
5614 * link, and enable Auto Enable LPI since there will
5615 * be no driver to enable LPI while in Sx.
5617 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5618 (dev_spec->eee_lp_ability &
5619 I82579_EEE_100_SUPPORTED) &&
5620 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5621 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5622 E1000_PHY_CTRL_NOND0A_LPLU);
5624 /* Set Auto Enable LPI after link up */
5625 hw->phy.ops.read_reg_locked(hw,
5628 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5629 hw->phy.ops.write_reg_locked(hw,
5635 /* For i217 Intel Rapid Start Technology support,
5636 * when the system is going into Sx and no manageability engine
5637 * is present, the driver must configure proxy to reset only on
5638 * power good. LPI (Low Power Idle) state must also reset only
5639 * on power good, as well as the MTA (Multicast table array).
5640 * The SMBus release must also be disabled on LCD reset.
5642 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5643 E1000_ICH_FWSM_FW_VALID)) {
5644 /* Enable proxy to reset only on power good. */
5645 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
5647 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5648 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
5651 /* Set bit enable LPI (EEE) to reset only on
5654 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
5655 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5656 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
5658 /* Disable the SMB release on LCD reset. */
5659 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
5660 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5661 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5664 /* Enable MTA to reset for Intel Rapid Start Technology
5667 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
5668 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5669 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5672 hw->phy.ops.release(hw);
5675 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5677 if (hw->mac.type == e1000_ich8lan)
5678 e1000_gig_downshift_workaround_ich8lan(hw);
5680 if (hw->mac.type >= e1000_pchlan) {
5681 e1000_oem_bits_config_ich8lan(hw, false);
5683 /* Reset PHY to activate OEM bits on 82577/8 */
5684 if (hw->mac.type == e1000_pchlan)
5685 e1000_phy_hw_reset_generic(hw);
5687 ret_val = hw->phy.ops.acquire(hw);
5690 e1000_write_smbus_addr(hw);
5691 hw->phy.ops.release(hw);
5698 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5699 * @hw: pointer to the HW structure
5701 * During Sx to S0 transitions on non-managed devices or managed devices
5702 * on which PHY resets are not blocked, if the PHY registers cannot be
5703 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5705 * On i217, setup Intel Rapid Start Technology.
5707 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5711 DEBUGFUNC("e1000_resume_workarounds_pchlan");
5712 if (hw->mac.type < e1000_pch2lan)
5713 return E1000_SUCCESS;
5715 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5717 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5721 /* For i217 Intel Rapid Start Technology support when the system
5722 * is transitioning from Sx and no manageability engine is present
5723 * configure SMBus to restore on reset, disable proxy, and enable
5724 * the reset on MTA (Multicast table array).
5726 if (hw->phy.type == e1000_phy_i217) {
5729 ret_val = hw->phy.ops.acquire(hw);
5731 DEBUGOUT("Failed to setup iRST\n");
5735 /* Clear Auto Enable LPI after link up */
5736 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5737 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5738 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5740 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5741 E1000_ICH_FWSM_FW_VALID)) {
5742 /* Restore clear on SMB if no manageability engine
5745 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5749 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5750 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5753 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5755 /* Enable reset on MTA */
5756 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5760 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5761 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5764 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5765 hw->phy.ops.release(hw);
5768 return E1000_SUCCESS;
5772 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5773 * @hw: pointer to the HW structure
5775 * Return the LED back to the default configuration.
5777 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5779 DEBUGFUNC("e1000_cleanup_led_ich8lan");
5781 if (hw->phy.type == e1000_phy_ife)
5782 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5785 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5786 return E1000_SUCCESS;
5790 * e1000_led_on_ich8lan - Turn LEDs on
5791 * @hw: pointer to the HW structure
5795 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5797 DEBUGFUNC("e1000_led_on_ich8lan");
5799 if (hw->phy.type == e1000_phy_ife)
5800 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5801 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5803 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5804 return E1000_SUCCESS;
5808 * e1000_led_off_ich8lan - Turn LEDs off
5809 * @hw: pointer to the HW structure
5811 * Turn off the LEDs.
5813 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5815 DEBUGFUNC("e1000_led_off_ich8lan");
5817 if (hw->phy.type == e1000_phy_ife)
5818 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5819 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5821 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5822 return E1000_SUCCESS;
5826 * e1000_setup_led_pchlan - Configures SW controllable LED
5827 * @hw: pointer to the HW structure
5829 * This prepares the SW controllable LED for use.
5831 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5833 DEBUGFUNC("e1000_setup_led_pchlan");
5835 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5836 (u16)hw->mac.ledctl_mode1);
5840 * e1000_cleanup_led_pchlan - Restore the default LED operation
5841 * @hw: pointer to the HW structure
5843 * Return the LED back to the default configuration.
5845 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5847 DEBUGFUNC("e1000_cleanup_led_pchlan");
5849 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5850 (u16)hw->mac.ledctl_default);
5854 * e1000_led_on_pchlan - Turn LEDs on
5855 * @hw: pointer to the HW structure
5859 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5861 u16 data = (u16)hw->mac.ledctl_mode2;
5864 DEBUGFUNC("e1000_led_on_pchlan");
5866 /* If no link, then turn LED on by setting the invert bit
5867 * for each LED that's mode is "link_up" in ledctl_mode2.
5869 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5870 for (i = 0; i < 3; i++) {
5871 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5872 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5873 E1000_LEDCTL_MODE_LINK_UP)
5875 if (led & E1000_PHY_LED0_IVRT)
5876 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5878 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5882 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5886 * e1000_led_off_pchlan - Turn LEDs off
5887 * @hw: pointer to the HW structure
5889 * Turn off the LEDs.
5891 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5893 u16 data = (u16)hw->mac.ledctl_mode1;
5896 DEBUGFUNC("e1000_led_off_pchlan");
5898 /* If no link, then turn LED off by clearing the invert bit
5899 * for each LED that's mode is "link_up" in ledctl_mode1.
5901 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5902 for (i = 0; i < 3; i++) {
5903 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5904 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5905 E1000_LEDCTL_MODE_LINK_UP)
5907 if (led & E1000_PHY_LED0_IVRT)
5908 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5910 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5914 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5918 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5919 * @hw: pointer to the HW structure
5921 * Read appropriate register for the config done bit for completion status
5922 * and configure the PHY through s/w for EEPROM-less parts.
5924 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5925 * config done bit, so only an error is logged and continues. If we were
5926 * to return with error, EEPROM-less silicon would not be able to be reset
5929 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5931 s32 ret_val = E1000_SUCCESS;
5935 DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5937 e1000_get_cfg_done_generic(hw);
5939 /* Wait for indication from h/w that it has completed basic config */
5940 if (hw->mac.type >= e1000_ich10lan) {
5941 e1000_lan_init_done_ich8lan(hw);
5943 ret_val = e1000_get_auto_rd_done_generic(hw);
5945 /* When auto config read does not complete, do not
5946 * return with an error. This can happen in situations
5947 * where there is no eeprom and prevents getting link.
5949 DEBUGOUT("Auto Read Done did not complete\n");
5950 ret_val = E1000_SUCCESS;
5954 /* Clear PHY Reset Asserted bit */
5955 status = E1000_READ_REG(hw, E1000_STATUS);
5956 if (status & E1000_STATUS_PHYRA)
5957 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5959 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5961 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5962 if (hw->mac.type <= e1000_ich9lan) {
5963 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5964 (hw->phy.type == e1000_phy_igp_3)) {
5965 e1000_phy_init_script_igp3(hw);
5968 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5969 /* Maybe we should do a basic PHY config */
5970 DEBUGOUT("EEPROM not present\n");
5971 ret_val = -E1000_ERR_CONFIG;
5979 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5980 * @hw: pointer to the HW structure
5982 * In the case of a PHY power down to save power, or to turn off link during a
5983 * driver unload, or wake on lan is not enabled, remove the link.
5985 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5987 /* If the management interface is not enabled, then power down */
5988 if (!(hw->mac.ops.check_mng_mode(hw) ||
5989 hw->phy.ops.check_reset_block(hw)))
5990 e1000_power_down_phy_copper(hw);
5996 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5997 * @hw: pointer to the HW structure
5999 * Clears hardware counters specific to the silicon family and calls
6000 * clear_hw_cntrs_generic to clear all general purpose counters.
6002 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
6007 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
6009 e1000_clear_hw_cntrs_base_generic(hw);
6011 E1000_READ_REG(hw, E1000_ALGNERRC);
6012 E1000_READ_REG(hw, E1000_RXERRC);
6013 E1000_READ_REG(hw, E1000_TNCRS);
6014 E1000_READ_REG(hw, E1000_CEXTERR);
6015 E1000_READ_REG(hw, E1000_TSCTC);
6016 E1000_READ_REG(hw, E1000_TSCTFC);
6018 E1000_READ_REG(hw, E1000_MGTPRC);
6019 E1000_READ_REG(hw, E1000_MGTPDC);
6020 E1000_READ_REG(hw, E1000_MGTPTC);
6022 E1000_READ_REG(hw, E1000_IAC);
6023 E1000_READ_REG(hw, E1000_ICRXOC);
6025 /* Clear PHY statistics registers */
6026 if ((hw->phy.type == e1000_phy_82578) ||
6027 (hw->phy.type == e1000_phy_82579) ||
6028 (hw->phy.type == e1000_phy_i217) ||
6029 (hw->phy.type == e1000_phy_82577)) {
6030 ret_val = hw->phy.ops.acquire(hw);
6033 ret_val = hw->phy.ops.set_page(hw,
6034 HV_STATS_PAGE << IGP_PAGE_SHIFT);
6037 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
6038 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
6039 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
6040 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
6041 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
6042 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
6043 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
6044 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
6045 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
6046 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
6047 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
6048 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
6049 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
6050 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
6052 hw->phy.ops.release(hw);
6057 * e1000_configure_k0s_lpt - Configure K0s power state
6058 * @hw: pointer to the HW structure
6059 * @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
6060 * 0 corresponds to 128ns, each value over 0 doubles the duration.
6061 * @min_time: Minimum Tx idle period allowed - valid values are 0 to 4.
6062 * 0 corresponds to 128ns, each value over 0 doubles the duration.
6064 * Configure the K1 power state based on the provided parameter.
6065 * Assumes semaphore already acquired.
6067 * Success returns 0, Failure returns:
6068 * -E1000_ERR_PHY (-2) in case of access error
6069 * -E1000_ERR_PARAM (-4) in case of parameters error
6071 s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
6076 DEBUGFUNC("e1000_configure_k0s_lpt");
6078 if (entry_latency > 3 || min_time > 4)
6079 return -E1000_ERR_PARAM;
6081 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6086 /* for now don't touch the latency */
6087 kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
6088 kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
6090 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
6095 return E1000_SUCCESS;