1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001 - 2015 Intel Corporation
5 #ifndef _E1000_ICH8LAN_H_
6 #define _E1000_ICH8LAN_H_
8 #define ICH_FLASH_GFPREG 0x0000
9 #define ICH_FLASH_HSFSTS 0x0004
10 #define ICH_FLASH_HSFCTL 0x0006
11 #define ICH_FLASH_FADDR 0x0008
12 #define ICH_FLASH_FDATA0 0x0010
14 /* Requires up to 10 seconds when MNG might be accessing part. */
15 #define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000
16 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000
17 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000
18 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
19 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
21 #define ICH_CYCLE_READ 0
22 #define ICH_CYCLE_WRITE 2
23 #define ICH_CYCLE_ERASE 3
25 #define FLASH_GFPREG_BASE_MASK 0x1FFF
26 #define FLASH_SECTOR_ADDR_SHIFT 12
28 #define ICH_FLASH_SEG_SIZE_256 256
29 #define ICH_FLASH_SEG_SIZE_4K 4096
30 #define ICH_FLASH_SEG_SIZE_8K 8192
31 #define ICH_FLASH_SEG_SIZE_64K 65536
33 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
34 /* FW established a valid mode */
35 #define E1000_ICH_FWSM_FW_VALID 0x00008000
36 #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
37 #define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000
39 #define E1000_ICH_MNG_IAMT_MODE 0x2
41 #define E1000_FWSM_WLOCK_MAC_MASK 0x0380
42 #define E1000_FWSM_WLOCK_MAC_SHIFT 7
43 #if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT)
44 #define E1000_FWSM_ULP_CFG_DONE 0x00000400 /* Low power cfg done */
45 #endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */
47 /* Shared Receive Address Registers */
48 #define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8))
49 #define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8))
51 #if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT)
52 #define E1000_H2ME 0x05B50 /* Host to ME */
53 #endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */
54 #if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT)
55 #define E1000_H2ME_ULP 0x00000800 /* ULP Indication Bit */
56 #define E1000_H2ME_ENFORCE_SETTINGS 0x00001000 /* Enforce Settings */
58 #endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */
59 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
60 (ID_LED_OFF1_OFF2 << 8) | \
61 (ID_LED_OFF1_ON2 << 4) | \
64 #define E1000_ICH_NVM_SIG_WORD 0x13
65 #define E1000_ICH_NVM_SIG_MASK 0xC000
66 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
67 #define E1000_ICH_NVM_SIG_VALUE 0x80
69 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
71 #if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT)
72 /* FEXT register bit definition */
73 #define E1000_FEXT_PHY_CABLE_DISCONNECTED 0x00000004
75 #endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */
76 #define E1000_FEXTNVM_SW_CONFIG 1
77 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* different on ICH8M */
79 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000
80 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000
82 #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
83 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
84 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
86 #define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100
87 #define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200
88 #define E1000_FEXTNVM6_K1_OFF_ENABLE 0x80000000
89 /* bit for disabling packet buffer read */
90 #define E1000_FEXTNVM7_DISABLE_PB_READ 0x00040000
91 #define E1000_FEXTNVM7_SIDE_CLK_UNGATE 0x00000004
92 #if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT)
93 #define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020
94 #endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */
95 #define E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS 0x00000800
96 #define E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS 0x00001000
97 #define E1000_FEXTNVM11_DISABLE_PB_READ 0x00000200
98 #define E1000_FEXTNVM11_DISABLE_MULR_FIX 0x00002000
100 /* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
101 #define E1000_RXDCTL_THRESH_UNIT_DESC 0x01000000
103 #define NVM_SIZE_MULTIPLIER 4096 /*multiplier for NVMS field*/
104 #define E1000_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs*/
105 #define E1000_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */
106 #define E1000_TARC0_CB_MULTIQ_3_REQ (1 << 28 | 1 << 29)
107 #define E1000_TARC0_CB_MULTIQ_2_REQ (1 << 29)
108 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
110 #define E1000_ICH_RAR_ENTRIES 7
111 #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
112 #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
114 #define PHY_PAGE_SHIFT 5
115 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
116 ((reg) & MAX_PHY_REG_ADDRESS))
117 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
118 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
120 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
121 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
122 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
124 /* PHY Wakeup Registers and defines */
125 #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
126 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
127 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
128 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
129 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
130 #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
131 #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
132 #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
133 #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
134 #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
136 #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
137 #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
138 #define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
139 #define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
140 #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
141 #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
142 #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
144 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
145 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
146 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
147 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
148 #define HV_STATS_PAGE 778
149 /* Half-duplex collision counts */
150 #define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision */
151 #define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17)
152 #define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */
153 #define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19)
154 #define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */
155 #define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21)
156 #define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */
157 #define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
158 #define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision */
159 #define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26)
160 #define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
161 #define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28)
162 #define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */
163 #define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30)
165 #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
167 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
168 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
169 #define K1_ENTRY_LATENCY 0
170 #define K1_MIN_TIME 1
172 /* SMBus Control Phy Register */
173 #define CV_SMB_CTRL PHY_REG(769, 23)
174 #define CV_SMB_CTRL_FORCE_SMBUS 0x0001
176 #if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT)
177 /* I218 Ultra Low Power Configuration 1 Register */
178 #define I218_ULP_CONFIG1 PHY_REG(779, 16)
179 #define I218_ULP_CONFIG1_START 0x0001 /* Start auto ULP config */
180 #define I218_ULP_CONFIG1_IND 0x0004 /* Pwr up from ULP indication */
181 #define I218_ULP_CONFIG1_STICKY_ULP 0x0010 /* Set sticky ULP mode */
182 #define I218_ULP_CONFIG1_INBAND_EXIT 0x0020 /* Inband on ULP exit */
183 #define I218_ULP_CONFIG1_WOL_HOST 0x0040 /* WoL Host on ULP exit */
184 #define I218_ULP_CONFIG1_RESET_TO_SMBUS 0x0100 /* Reset to SMBus mode */
185 /* enable ULP even if when phy powered down via lanphypc */
186 #define I218_ULP_CONFIG1_EN_ULP_LANPHYPC 0x0400
187 /* disable clear of sticky ULP on PERST */
188 #define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST 0x0800
189 #define I218_ULP_CONFIG1_DISABLE_SMB_PERST 0x1000 /* Disable on PERST# */
191 #endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */
192 /* SMBus Address Phy Register */
193 #define HV_SMB_ADDR PHY_REG(768, 26)
194 #define HV_SMB_ADDR_MASK 0x007F
195 #define HV_SMB_ADDR_PEC_EN 0x0200
196 #define HV_SMB_ADDR_VALID 0x0080
197 #define HV_SMB_ADDR_FREQ_MASK 0x1100
198 #define HV_SMB_ADDR_FREQ_LOW_SHIFT 8
199 #define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12
201 /* Strapping Option Register - RO */
202 #define E1000_STRAP 0x0000C
203 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
204 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
205 #define E1000_STRAP_SMT_FREQ_MASK 0x00003000
206 #define E1000_STRAP_SMT_FREQ_SHIFT 12
208 /* OEM Bits Phy Register */
209 #define HV_OEM_BITS PHY_REG(768, 25)
210 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
211 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
212 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
214 /* KMRN Mode Control */
215 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
216 #define HV_KMRN_MDIO_SLOW 0x0400
218 /* KMRN FIFO Control and Status */
219 #define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16)
220 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000
221 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12
223 /* PHY Power Management Control */
224 #define HV_PM_CTRL PHY_REG(770, 17)
225 #define HV_PM_CTRL_K1_CLK_REQ 0x200
226 #define HV_PM_CTRL_K1_ENABLE 0x4000
228 #define I217_PLL_CLOCK_GATE_REG PHY_REG(772, 28)
229 #define I217_PLL_CLOCK_GATE_MASK 0x07FF
231 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */
234 #define I217_INBAND_CTRL PHY_REG(770, 18)
235 #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK 0x3F00
236 #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT 8
238 /* Low Power Idle GPIO Control */
239 #define I217_LPI_GPIO_CTRL PHY_REG(772, 18)
240 #define I217_LPI_GPIO_CTRL_AUTO_EN_LPI 0x0800
242 /* PHY Low Power Idle Control */
243 #define I82579_LPI_CTRL PHY_REG(772, 20)
244 #define I82579_LPI_CTRL_100_ENABLE 0x2000
245 #define I82579_LPI_CTRL_1000_ENABLE 0x4000
246 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000
248 /* 82579 DFT Control */
249 #define I82579_DFT_CTRL PHY_REG(769, 20)
250 #define I82579_DFT_CTRL_GATE_PHY_RESET 0x0040 /* Gate PHY Reset on MAC Reset */
252 /* Extended Management Interface (EMI) Registers */
253 #define I82579_EMI_ADDR 0x10
254 #define I82579_EMI_DATA 0x11
255 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
256 #define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */
257 #define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */
258 #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */
259 #define I82579_RX_CONFIG 0x3412 /* Receive configuration */
260 #define I82579_LPI_PLL_SHUT 0x4412 /* LPI PLL Shut Enable */
261 #define I82579_EEE_PCS_STATUS 0x182E /* IEEE MMD Register 3.1 >> 8 */
262 #define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */
263 #define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */
264 #define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */
265 #define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE */
266 #define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE */
267 #define I82579_LPI_100_PLL_SHUT (1 << 2) /* 100M LPI PLL Shut Enabled */
268 #define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */
269 #define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */
270 #define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */
271 #define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */
272 #define I217_RX_CONFIG 0xB20C /* Receive configuration */
274 #define E1000_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */
275 #define E1000_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */
277 /* Intel Rapid Start Technology Support */
278 #define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70)
279 #define I217_PROXY_CTRL_AUTO_DISABLE 0x0080
280 #define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28)
281 #define I217_SxCTRL_ENABLE_LPI_RESET 0x1000
282 #define I217_CGFREG PHY_REG(772, 29)
283 #define I217_CGFREG_ENABLE_MTA_RESET 0x0002
284 #define I217_MEMPWR PHY_REG(772, 26)
285 #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010
287 /* Receive Address Initial CRC Calculation */
288 #define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4))
290 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
291 #define E1000_PCI_REVISION_ID_REG 0x08
292 #endif /* defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT) */
293 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
295 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
296 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
297 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
298 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
299 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
300 s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time);
301 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
302 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
303 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
304 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data);
305 s32 e1000_set_eee_pchlan(struct e1000_hw *hw);
307 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx);
308 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
309 #endif /* ULP_SUPPORT */
310 #endif /* _E1000_ICH8LAN_H_ */
311 void e1000_demote_ltr(struct e1000_hw *hw, bool demote, bool link);