1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "e1000_api.h"
36 STATIC s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
37 STATIC void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
38 STATIC void e1000_config_collision_dist_generic(struct e1000_hw *hw);
39 STATIC void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
42 * e1000_init_mac_ops_generic - Initialize MAC function pointers
43 * @hw: pointer to the HW structure
45 * Setups up the function pointers to no-op functions
47 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
49 struct e1000_mac_info *mac = &hw->mac;
50 DEBUGFUNC("e1000_init_mac_ops_generic");
53 mac->ops.init_params = e1000_null_ops_generic;
54 mac->ops.init_hw = e1000_null_ops_generic;
55 mac->ops.reset_hw = e1000_null_ops_generic;
56 mac->ops.setup_physical_interface = e1000_null_ops_generic;
57 mac->ops.get_bus_info = e1000_null_ops_generic;
58 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
59 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
60 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
61 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
63 mac->ops.cleanup_led = e1000_null_ops_generic;
64 mac->ops.setup_led = e1000_null_ops_generic;
65 mac->ops.blink_led = e1000_null_ops_generic;
66 mac->ops.led_on = e1000_null_ops_generic;
67 mac->ops.led_off = e1000_null_ops_generic;
69 mac->ops.setup_link = e1000_null_ops_generic;
70 mac->ops.get_link_up_info = e1000_null_link_info;
71 mac->ops.check_for_link = e1000_null_ops_generic;
72 mac->ops.wait_autoneg = e1000_wait_autoneg_generic;
74 mac->ops.check_mng_mode = e1000_null_mng_mode;
75 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic;
76 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic;
77 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic;
79 mac->ops.update_mc_addr_list = e1000_null_update_mc;
80 mac->ops.clear_vfta = e1000_null_mac_generic;
81 mac->ops.write_vfta = e1000_null_write_vfta;
82 mac->ops.rar_set = e1000_rar_set_generic;
83 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
87 * e1000_null_ops_generic - No-op function, returns 0
88 * @hw: pointer to the HW structure
90 s32 e1000_null_ops_generic(struct e1000_hw *hw)
92 DEBUGFUNC("e1000_null_ops_generic");
97 * e1000_null_mac_generic - No-op function, return void
98 * @hw: pointer to the HW structure
100 void e1000_null_mac_generic(struct e1000_hw *hw)
102 DEBUGFUNC("e1000_null_mac_generic");
107 * e1000_null_link_info - No-op function, return 0
108 * @hw: pointer to the HW structure
110 s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d)
112 DEBUGFUNC("e1000_null_link_info");
113 return E1000_SUCCESS;
117 * e1000_null_mng_mode - No-op function, return false
118 * @hw: pointer to the HW structure
120 bool e1000_null_mng_mode(struct e1000_hw *hw)
122 DEBUGFUNC("e1000_null_mng_mode");
127 * e1000_null_update_mc - No-op function, return void
128 * @hw: pointer to the HW structure
130 void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a)
132 DEBUGFUNC("e1000_null_update_mc");
137 * e1000_null_write_vfta - No-op function, return void
138 * @hw: pointer to the HW structure
140 void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b)
142 DEBUGFUNC("e1000_null_write_vfta");
147 * e1000_null_rar_set - No-op function, return void
148 * @hw: pointer to the HW structure
150 void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a)
152 DEBUGFUNC("e1000_null_rar_set");
157 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
158 * @hw: pointer to the HW structure
160 * Determines and stores the system bus information for a particular
161 * network interface. The following bus information is determined and stored:
162 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
164 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
166 struct e1000_mac_info *mac = &hw->mac;
167 struct e1000_bus_info *bus = &hw->bus;
168 u32 status = E1000_READ_REG(hw, E1000_STATUS);
169 s32 ret_val = E1000_SUCCESS;
171 DEBUGFUNC("e1000_get_bus_info_pci_generic");
174 bus->type = (status & E1000_STATUS_PCIX_MODE)
175 ? e1000_bus_type_pcix
176 : e1000_bus_type_pci;
179 if (bus->type == e1000_bus_type_pci) {
180 bus->speed = (status & E1000_STATUS_PCI66)
182 : e1000_bus_speed_33;
184 switch (status & E1000_STATUS_PCIX_SPEED) {
185 case E1000_STATUS_PCIX_SPEED_66:
186 bus->speed = e1000_bus_speed_66;
188 case E1000_STATUS_PCIX_SPEED_100:
189 bus->speed = e1000_bus_speed_100;
191 case E1000_STATUS_PCIX_SPEED_133:
192 bus->speed = e1000_bus_speed_133;
195 bus->speed = e1000_bus_speed_reserved;
201 bus->width = (status & E1000_STATUS_BUS64)
203 : e1000_bus_width_32;
205 /* Which PCI(-X) function? */
206 mac->ops.set_lan_id(hw);
212 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
213 * @hw: pointer to the HW structure
215 * Determines and stores the system bus information for a particular
216 * network interface. The following bus information is determined and stored:
217 * bus speed, bus width, type (PCIe), and PCIe function.
219 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
221 struct e1000_mac_info *mac = &hw->mac;
222 struct e1000_bus_info *bus = &hw->bus;
224 u16 pcie_link_status;
226 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
228 bus->type = e1000_bus_type_pci_express;
230 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
233 bus->width = e1000_bus_width_unknown;
234 bus->speed = e1000_bus_speed_unknown;
236 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
237 case PCIE_LINK_SPEED_2500:
238 bus->speed = e1000_bus_speed_2500;
240 case PCIE_LINK_SPEED_5000:
241 bus->speed = e1000_bus_speed_5000;
244 bus->speed = e1000_bus_speed_unknown;
248 bus->width = (enum e1000_bus_width)((pcie_link_status &
249 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);
252 mac->ops.set_lan_id(hw);
254 return E1000_SUCCESS;
258 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
260 * @hw: pointer to the HW structure
262 * Determines the LAN function id by reading memory-mapped registers
263 * and swaps the port value if requested.
265 STATIC void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
267 struct e1000_bus_info *bus = &hw->bus;
271 * The status register reports the correct function number
272 * for the device regardless of function swap state.
274 reg = E1000_READ_REG(hw, E1000_STATUS);
275 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
279 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
280 * @hw: pointer to the HW structure
282 * Determines the LAN function id by reading PCI config space.
284 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
286 struct e1000_bus_info *bus = &hw->bus;
290 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
291 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
292 status = E1000_READ_REG(hw, E1000_STATUS);
293 bus->func = (status & E1000_STATUS_FUNC_MASK)
294 >> E1000_STATUS_FUNC_SHIFT;
301 * e1000_set_lan_id_single_port - Set LAN id for a single port device
302 * @hw: pointer to the HW structure
304 * Sets the LAN function id to zero for a single port device.
306 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
308 struct e1000_bus_info *bus = &hw->bus;
314 * e1000_clear_vfta_generic - Clear VLAN filter table
315 * @hw: pointer to the HW structure
317 * Clears the register array which contains the VLAN filter table by
318 * setting all the values to 0.
320 void e1000_clear_vfta_generic(struct e1000_hw *hw)
324 DEBUGFUNC("e1000_clear_vfta_generic");
326 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
327 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
328 E1000_WRITE_FLUSH(hw);
333 * e1000_write_vfta_generic - Write value to VLAN filter table
334 * @hw: pointer to the HW structure
335 * @offset: register offset in VLAN filter table
336 * @value: register value written to VLAN filter table
338 * Writes value at the given offset in the register array which stores
339 * the VLAN filter table.
341 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
343 DEBUGFUNC("e1000_write_vfta_generic");
345 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
346 E1000_WRITE_FLUSH(hw);
350 * e1000_init_rx_addrs_generic - Initialize receive address's
351 * @hw: pointer to the HW structure
352 * @rar_count: receive address registers
354 * Setup the receive address registers by setting the base receive address
355 * register to the devices MAC address and clearing all the other receive
356 * address registers to 0.
358 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
361 u8 mac_addr[ETH_ADDR_LEN] = {0};
363 DEBUGFUNC("e1000_init_rx_addrs_generic");
365 /* Setup the receive address */
366 DEBUGOUT("Programming MAC Address into RAR[0]\n");
368 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
370 /* Zero out the other (rar_entry_count - 1) receive addresses */
371 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
372 for (i = 1; i < rar_count; i++)
373 hw->mac.ops.rar_set(hw, mac_addr, i);
377 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
378 * @hw: pointer to the HW structure
380 * Checks the nvm for an alternate MAC address. An alternate MAC address
381 * can be setup by pre-boot software and must be treated like a permanent
382 * address and must override the actual permanent MAC address. If an
383 * alternate MAC address is found it is programmed into RAR0, replacing
384 * the permanent address that was installed into RAR0 by the Si on reset.
385 * This function will return SUCCESS unless it encounters an error while
386 * reading the EEPROM.
388 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
391 s32 ret_val = E1000_SUCCESS;
392 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
393 u8 alt_mac_addr[ETH_ADDR_LEN];
395 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
397 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
401 /* not supported on older hardware or 82573 */
402 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))
403 return E1000_SUCCESS;
406 * Alternate MAC address is handled by the option ROM for 82580
407 * and newer. SW support not required.
409 if (hw->mac.type >= e1000_82580)
410 return E1000_SUCCESS;
412 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
413 &nvm_alt_mac_addr_offset);
415 DEBUGOUT("NVM Read Error\n");
419 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
420 (nvm_alt_mac_addr_offset == 0x0000))
421 /* There is no Alternate MAC Address */
422 return E1000_SUCCESS;
424 if (hw->bus.func == E1000_FUNC_1)
425 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
426 if (hw->bus.func == E1000_FUNC_2)
427 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
429 if (hw->bus.func == E1000_FUNC_3)
430 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
431 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
432 offset = nvm_alt_mac_addr_offset + (i >> 1);
433 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
435 DEBUGOUT("NVM Read Error\n");
439 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
440 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
443 /* if multicast bit is set, the alternate address will not be used */
444 if (alt_mac_addr[0] & 0x01) {
445 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
446 return E1000_SUCCESS;
450 * We have a valid alternate MAC address, and we want to treat it the
451 * same as the normal permanent MAC address stored by the HW into the
452 * RAR. Do this by mapping this address into RAR0.
454 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
456 return E1000_SUCCESS;
460 * e1000_rar_set_generic - Set receive address register
461 * @hw: pointer to the HW structure
462 * @addr: pointer to the receive address
463 * @index: receive address array register
465 * Sets the receive address array register at index to the address passed
468 STATIC void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
470 u32 rar_low, rar_high;
472 DEBUGFUNC("e1000_rar_set_generic");
475 * HW expects these in little endian so we reverse the byte order
476 * from network order (big endian) to little endian
478 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
479 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
481 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
483 /* If MAC address zero, no need to set the AV bit */
484 if (rar_low || rar_high)
485 rar_high |= E1000_RAH_AV;
488 * Some bridges will combine consecutive 32-bit writes into
489 * a single burst write, which will malfunction on some parts.
490 * The flushes avoid this.
492 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
493 E1000_WRITE_FLUSH(hw);
494 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
495 E1000_WRITE_FLUSH(hw);
499 * e1000_hash_mc_addr_generic - Generate a multicast hash value
500 * @hw: pointer to the HW structure
501 * @mc_addr: pointer to a multicast address
503 * Generates a multicast address hash value which is used to determine
504 * the multicast filter table array address and new table value.
506 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
508 u32 hash_value, hash_mask;
511 DEBUGFUNC("e1000_hash_mc_addr_generic");
513 /* Register count multiplied by bits per register */
514 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
517 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
518 * where 0xFF would still fall within the hash mask.
520 while (hash_mask >> bit_shift != 0xFF)
524 * The portion of the address that is used for the hash table
525 * is determined by the mc_filter_type setting.
526 * The algorithm is such that there is a total of 8 bits of shifting.
527 * The bit_shift for a mc_filter_type of 0 represents the number of
528 * left-shifts where the MSB of mc_addr[5] would still fall within
529 * the hash_mask. Case 0 does this exactly. Since there are a total
530 * of 8 bits of shifting, then mc_addr[4] will shift right the
531 * remaining number of bits. Thus 8 - bit_shift. The rest of the
532 * cases are a variation of this algorithm...essentially raising the
533 * number of bits to shift mc_addr[5] left, while still keeping the
534 * 8-bit shifting total.
536 * For example, given the following Destination MAC Address and an
537 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
538 * we can see that the bit_shift for case 0 is 4. These are the hash
539 * values resulting from each mc_filter_type...
540 * [0] [1] [2] [3] [4] [5]
544 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
545 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
546 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
547 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
549 switch (hw->mac.mc_filter_type) {
564 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
565 (((u16) mc_addr[5]) << bit_shift)));
571 * e1000_update_mc_addr_list_generic - Update Multicast addresses
572 * @hw: pointer to the HW structure
573 * @mc_addr_list: array of multicast addresses to program
574 * @mc_addr_count: number of multicast addresses to program
576 * Updates entire Multicast Table Array.
577 * The caller must have a packed mc_addr_list of multicast addresses.
579 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
580 u8 *mc_addr_list, u32 mc_addr_count)
582 u32 hash_value, hash_bit, hash_reg;
585 DEBUGFUNC("e1000_update_mc_addr_list_generic");
587 /* clear mta_shadow */
588 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
590 /* update mta_shadow from mc_addr_list */
591 for (i = 0; (u32) i < mc_addr_count; i++) {
592 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
594 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
595 hash_bit = hash_value & 0x1F;
597 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
598 mc_addr_list += (ETH_ADDR_LEN);
601 /* replace the entire MTA table */
602 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
603 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
604 E1000_WRITE_FLUSH(hw);
608 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
609 * @hw: pointer to the HW structure
611 * In certain situations, a system BIOS may report that the PCIx maximum
612 * memory read byte count (MMRBC) value is higher than than the actual
613 * value. We check the PCIx command register with the current PCIx status
616 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
620 u16 pcix_stat_hi_word;
623 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
625 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
626 if (hw->bus.type != e1000_bus_type_pcix)
629 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
630 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
631 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
632 PCIX_COMMAND_MMRBC_SHIFT;
633 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
634 PCIX_STATUS_HI_MMRBC_SHIFT;
635 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
636 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
637 if (cmd_mmrbc > stat_mmrbc) {
638 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
639 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
640 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
645 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
646 * @hw: pointer to the HW structure
648 * Clears the base hardware counters by reading the counter registers.
650 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
652 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
654 E1000_READ_REG(hw, E1000_CRCERRS);
655 E1000_READ_REG(hw, E1000_SYMERRS);
656 E1000_READ_REG(hw, E1000_MPC);
657 E1000_READ_REG(hw, E1000_SCC);
658 E1000_READ_REG(hw, E1000_ECOL);
659 E1000_READ_REG(hw, E1000_MCC);
660 E1000_READ_REG(hw, E1000_LATECOL);
661 E1000_READ_REG(hw, E1000_COLC);
662 E1000_READ_REG(hw, E1000_DC);
663 E1000_READ_REG(hw, E1000_SEC);
664 E1000_READ_REG(hw, E1000_RLEC);
665 E1000_READ_REG(hw, E1000_XONRXC);
666 E1000_READ_REG(hw, E1000_XONTXC);
667 E1000_READ_REG(hw, E1000_XOFFRXC);
668 E1000_READ_REG(hw, E1000_XOFFTXC);
669 E1000_READ_REG(hw, E1000_FCRUC);
670 E1000_READ_REG(hw, E1000_GPRC);
671 E1000_READ_REG(hw, E1000_BPRC);
672 E1000_READ_REG(hw, E1000_MPRC);
673 E1000_READ_REG(hw, E1000_GPTC);
674 E1000_READ_REG(hw, E1000_GORCL);
675 E1000_READ_REG(hw, E1000_GORCH);
676 E1000_READ_REG(hw, E1000_GOTCL);
677 E1000_READ_REG(hw, E1000_GOTCH);
678 E1000_READ_REG(hw, E1000_RNBC);
679 E1000_READ_REG(hw, E1000_RUC);
680 E1000_READ_REG(hw, E1000_RFC);
681 E1000_READ_REG(hw, E1000_ROC);
682 E1000_READ_REG(hw, E1000_RJC);
683 E1000_READ_REG(hw, E1000_TORL);
684 E1000_READ_REG(hw, E1000_TORH);
685 E1000_READ_REG(hw, E1000_TOTL);
686 E1000_READ_REG(hw, E1000_TOTH);
687 E1000_READ_REG(hw, E1000_TPR);
688 E1000_READ_REG(hw, E1000_TPT);
689 E1000_READ_REG(hw, E1000_MPTC);
690 E1000_READ_REG(hw, E1000_BPTC);
694 * e1000_check_for_copper_link_generic - Check for link (Copper)
695 * @hw: pointer to the HW structure
697 * Checks to see of the link status of the hardware has changed. If a
698 * change in link status has been detected, then we read the PHY registers
699 * to get the current speed/duplex if link exists.
701 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
703 struct e1000_mac_info *mac = &hw->mac;
707 DEBUGFUNC("e1000_check_for_copper_link");
710 * We only want to go out to the PHY registers to see if Auto-Neg
711 * has completed and/or if our link status has changed. The
712 * get_link_status flag is set upon receiving a Link Status
713 * Change or Rx Sequence Error interrupt.
715 if (!mac->get_link_status)
716 return E1000_SUCCESS;
719 * First we want to see if the MII Status Register reports
720 * link. If so, then we want to get the current speed/duplex
723 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
728 return E1000_SUCCESS; /* No link detected */
730 mac->get_link_status = false;
733 * Check if there was DownShift, must be checked
734 * immediately after link-up
736 e1000_check_downshift_generic(hw);
739 * If we are forcing speed/duplex, then we simply return since
740 * we have already determined whether we have link or not.
743 return -E1000_ERR_CONFIG;
746 * Auto-Neg is enabled. Auto Speed Detection takes care
747 * of MAC speed/duplex configuration. So we only need to
748 * configure Collision Distance in the MAC.
750 mac->ops.config_collision_dist(hw);
753 * Configure Flow Control now that Auto-Neg has completed.
754 * First, we need to restore the desired flow control
755 * settings because we may have had to re-autoneg with a
756 * different link partner.
758 ret_val = e1000_config_fc_after_link_up_generic(hw);
760 DEBUGOUT("Error configuring flow control\n");
766 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
767 * @hw: pointer to the HW structure
769 * Checks for link up on the hardware. If link is not up and we have
770 * a signal, then we need to force link up.
772 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
774 struct e1000_mac_info *mac = &hw->mac;
780 DEBUGFUNC("e1000_check_for_fiber_link_generic");
782 ctrl = E1000_READ_REG(hw, E1000_CTRL);
783 status = E1000_READ_REG(hw, E1000_STATUS);
784 rxcw = E1000_READ_REG(hw, E1000_RXCW);
787 * If we don't have link (auto-negotiation failed or link partner
788 * cannot auto-negotiate), the cable is plugged in (we have signal),
789 * and our link partner is not trying to auto-negotiate with us (we
790 * are receiving idles or data), we need to force link up. We also
791 * need to give auto-negotiation time to complete, in case the cable
792 * was just plugged in. The autoneg_failed flag does this.
794 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
795 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
796 !(rxcw & E1000_RXCW_C)) {
797 if (!mac->autoneg_failed) {
798 mac->autoneg_failed = true;
799 return E1000_SUCCESS;
801 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
803 /* Disable auto-negotiation in the TXCW register */
804 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
806 /* Force link-up and also force full-duplex. */
807 ctrl = E1000_READ_REG(hw, E1000_CTRL);
808 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
809 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
811 /* Configure Flow Control after forcing link up. */
812 ret_val = e1000_config_fc_after_link_up_generic(hw);
814 DEBUGOUT("Error configuring flow control\n");
817 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
819 * If we are forcing link and we are receiving /C/ ordered
820 * sets, re-enable auto-negotiation in the TXCW register
821 * and disable forced link in the Device Control register
822 * in an attempt to auto-negotiate with our link partner.
824 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
825 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
826 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
828 mac->serdes_has_link = true;
831 return E1000_SUCCESS;
835 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
836 * @hw: pointer to the HW structure
838 * Checks for link up on the hardware. If link is not up and we have
839 * a signal, then we need to force link up.
841 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
843 struct e1000_mac_info *mac = &hw->mac;
849 DEBUGFUNC("e1000_check_for_serdes_link_generic");
851 ctrl = E1000_READ_REG(hw, E1000_CTRL);
852 status = E1000_READ_REG(hw, E1000_STATUS);
853 rxcw = E1000_READ_REG(hw, E1000_RXCW);
856 * If we don't have link (auto-negotiation failed or link partner
857 * cannot auto-negotiate), and our link partner is not trying to
858 * auto-negotiate with us (we are receiving idles or data),
859 * we need to force link up. We also need to give auto-negotiation
862 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
863 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {
864 if (!mac->autoneg_failed) {
865 mac->autoneg_failed = true;
866 return E1000_SUCCESS;
868 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
870 /* Disable auto-negotiation in the TXCW register */
871 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
873 /* Force link-up and also force full-duplex. */
874 ctrl = E1000_READ_REG(hw, E1000_CTRL);
875 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
876 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
878 /* Configure Flow Control after forcing link up. */
879 ret_val = e1000_config_fc_after_link_up_generic(hw);
881 DEBUGOUT("Error configuring flow control\n");
884 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
886 * If we are forcing link and we are receiving /C/ ordered
887 * sets, re-enable auto-negotiation in the TXCW register
888 * and disable forced link in the Device Control register
889 * in an attempt to auto-negotiate with our link partner.
891 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
892 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
893 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
895 mac->serdes_has_link = true;
896 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
898 * If we force link for non-auto-negotiation switch, check
899 * link status based on MAC synchronization for internal
902 /* SYNCH bit and IV bit are sticky. */
904 rxcw = E1000_READ_REG(hw, E1000_RXCW);
905 if (rxcw & E1000_RXCW_SYNCH) {
906 if (!(rxcw & E1000_RXCW_IV)) {
907 mac->serdes_has_link = true;
908 DEBUGOUT("SERDES: Link up - forced.\n");
911 mac->serdes_has_link = false;
912 DEBUGOUT("SERDES: Link down - force failed.\n");
916 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
917 status = E1000_READ_REG(hw, E1000_STATUS);
918 if (status & E1000_STATUS_LU) {
919 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
921 rxcw = E1000_READ_REG(hw, E1000_RXCW);
922 if (rxcw & E1000_RXCW_SYNCH) {
923 if (!(rxcw & E1000_RXCW_IV)) {
924 mac->serdes_has_link = true;
925 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n");
927 mac->serdes_has_link = false;
928 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n");
931 mac->serdes_has_link = false;
932 DEBUGOUT("SERDES: Link down - no sync.\n");
935 mac->serdes_has_link = false;
936 DEBUGOUT("SERDES: Link down - autoneg failed\n");
940 return E1000_SUCCESS;
944 * e1000_set_default_fc_generic - Set flow control default values
945 * @hw: pointer to the HW structure
947 * Read the EEPROM for the default values for flow control and store the
950 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
955 DEBUGFUNC("e1000_set_default_fc_generic");
958 * Read and store word 0x0F of the EEPROM. This word contains bits
959 * that determine the hardware's default PAUSE (flow control) mode,
960 * a bit that determines whether the HW defaults to enabling or
961 * disabling auto-negotiation, and the direction of the
962 * SW defined pins. If there is no SW over-ride of the flow
963 * control setting, then the variable hw->fc will
964 * be initialized based on a value in the EEPROM.
966 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
969 DEBUGOUT("NVM Read Error\n");
973 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
974 hw->fc.requested_mode = e1000_fc_none;
975 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
977 hw->fc.requested_mode = e1000_fc_tx_pause;
979 hw->fc.requested_mode = e1000_fc_full;
981 return E1000_SUCCESS;
985 * e1000_setup_link_generic - Setup flow control and link settings
986 * @hw: pointer to the HW structure
988 * Determines which flow control settings to use, then configures flow
989 * control. Calls the appropriate media-specific link configuration
990 * function. Assuming the adapter has a valid link partner, a valid link
991 * should be established. Assumes the hardware has previously been reset
992 * and the transmitter and receiver are not enabled.
994 s32 e1000_setup_link_generic(struct e1000_hw *hw)
998 DEBUGFUNC("e1000_setup_link_generic");
1001 * In the case of the phy reset being blocked, we already have a link.
1002 * We do not need to set it up again.
1004 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
1005 return E1000_SUCCESS;
1008 * If requested flow control is set to default, set flow control
1009 * based on the EEPROM flow control settings.
1011 if (hw->fc.requested_mode == e1000_fc_default) {
1012 ret_val = e1000_set_default_fc_generic(hw);
1018 * Save off the requested flow control mode for use later. Depending
1019 * on the link partner's capabilities, we may or may not use this mode.
1021 hw->fc.current_mode = hw->fc.requested_mode;
1023 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
1024 hw->fc.current_mode);
1026 /* Call the necessary media_type subroutine to configure the link. */
1027 ret_val = hw->mac.ops.setup_physical_interface(hw);
1032 * Initialize the flow control address, type, and PAUSE timer
1033 * registers to their default values. This is done even if flow
1034 * control is disabled, because it does not hurt anything to
1035 * initialize these registers.
1037 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1038 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1039 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1040 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1042 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1044 return e1000_set_fc_watermarks_generic(hw);
1048 * e1000_commit_fc_settings_generic - Configure flow control
1049 * @hw: pointer to the HW structure
1051 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1052 * base on the flow control settings in e1000_mac_info.
1054 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1056 struct e1000_mac_info *mac = &hw->mac;
1059 DEBUGFUNC("e1000_commit_fc_settings_generic");
1062 * Check for a software override of the flow control settings, and
1063 * setup the device accordingly. If auto-negotiation is enabled, then
1064 * software will have to set the "PAUSE" bits to the correct value in
1065 * the Transmit Config Word Register (TXCW) and re-start auto-
1066 * negotiation. However, if auto-negotiation is disabled, then
1067 * software will have to manually configure the two flow control enable
1068 * bits in the CTRL register.
1070 * The possible values of the "fc" parameter are:
1071 * 0: Flow control is completely disabled
1072 * 1: Rx flow control is enabled (we can receive pause frames,
1073 * but not send pause frames).
1074 * 2: Tx flow control is enabled (we can send pause frames but we
1075 * do not support receiving pause frames).
1076 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1078 switch (hw->fc.current_mode) {
1080 /* Flow control completely disabled by a software over-ride. */
1081 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1083 case e1000_fc_rx_pause:
1085 * Rx Flow control is enabled and Tx Flow control is disabled
1086 * by a software over-ride. Since there really isn't a way to
1087 * advertise that we are capable of Rx Pause ONLY, we will
1088 * advertise that we support both symmetric and asymmetric Rx
1089 * PAUSE. Later, we will disable the adapter's ability to send
1092 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1094 case e1000_fc_tx_pause:
1096 * Tx Flow control is enabled, and Rx Flow control is disabled,
1097 * by a software over-ride.
1099 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1103 * Flow control (both Rx and Tx) is enabled by a software
1106 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1109 DEBUGOUT("Flow control param set incorrectly\n");
1110 return -E1000_ERR_CONFIG;
1114 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1117 return E1000_SUCCESS;
1121 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1122 * @hw: pointer to the HW structure
1124 * Polls for link up by reading the status register, if link fails to come
1125 * up with auto-negotiation, then the link is forced if a signal is detected.
1127 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1129 struct e1000_mac_info *mac = &hw->mac;
1133 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1136 * If we have a signal (the cable is plugged in, or assumed true for
1137 * serdes media) then poll for a "Link-Up" indication in the Device
1138 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1139 * seconds (Auto-negotiation should complete in less than 500
1140 * milliseconds even if the other end is doing it in SW).
1142 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1144 status = E1000_READ_REG(hw, E1000_STATUS);
1145 if (status & E1000_STATUS_LU)
1148 if (i == FIBER_LINK_UP_LIMIT) {
1149 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1150 mac->autoneg_failed = true;
1152 * AutoNeg failed to achieve a link, so we'll call
1153 * mac->check_for_link. This routine will force the
1154 * link up if we detect a signal. This will allow us to
1155 * communicate with non-autonegotiating link partners.
1157 ret_val = mac->ops.check_for_link(hw);
1159 DEBUGOUT("Error while checking for link\n");
1162 mac->autoneg_failed = false;
1164 mac->autoneg_failed = false;
1165 DEBUGOUT("Valid Link Found\n");
1168 return E1000_SUCCESS;
1172 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1173 * @hw: pointer to the HW structure
1175 * Configures collision distance and flow control for fiber and serdes
1176 * links. Upon successful setup, poll for link.
1178 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1183 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1185 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1187 /* Take the link out of reset */
1188 ctrl &= ~E1000_CTRL_LRST;
1190 hw->mac.ops.config_collision_dist(hw);
1192 ret_val = e1000_commit_fc_settings_generic(hw);
1197 * Since auto-negotiation is enabled, take the link out of reset (the
1198 * link will be in reset, because we previously reset the chip). This
1199 * will restart auto-negotiation. If auto-negotiation is successful
1200 * then the link-up status bit will be set and the flow control enable
1201 * bits (RFCE and TFCE) will be set according to their negotiated value.
1203 DEBUGOUT("Auto-negotiation enabled\n");
1205 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1206 E1000_WRITE_FLUSH(hw);
1210 * For these adapters, the SW definable pin 1 is set when the optics
1211 * detect a signal. If we have a signal, then poll for a "Link-Up"
1214 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1215 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1216 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1218 DEBUGOUT("No signal detected\n");
1225 * e1000_config_collision_dist_generic - Configure collision distance
1226 * @hw: pointer to the HW structure
1228 * Configures the collision distance to the default value and is used
1229 * during link setup.
1231 STATIC void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1235 DEBUGFUNC("e1000_config_collision_dist_generic");
1237 tctl = E1000_READ_REG(hw, E1000_TCTL);
1239 tctl &= ~E1000_TCTL_COLD;
1240 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1242 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1243 E1000_WRITE_FLUSH(hw);
1247 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1248 * @hw: pointer to the HW structure
1250 * Sets the flow control high/low threshold (watermark) registers. If
1251 * flow control XON frame transmission is enabled, then set XON frame
1252 * transmission as well.
1254 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1256 u32 fcrtl = 0, fcrth = 0;
1258 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1261 * Set the flow control receive threshold registers. Normally,
1262 * these registers will be set to a default threshold that may be
1263 * adjusted later by the driver's runtime code. However, if the
1264 * ability to transmit pause frames is not enabled, then these
1265 * registers will be set to 0.
1267 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1269 * We need to set up the Receive Threshold high and low water
1270 * marks as well as (optionally) enabling the transmission of
1273 fcrtl = hw->fc.low_water;
1274 if (hw->fc.send_xon)
1275 fcrtl |= E1000_FCRTL_XONE;
1277 fcrth = hw->fc.high_water;
1279 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1280 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1282 return E1000_SUCCESS;
1286 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1287 * @hw: pointer to the HW structure
1289 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1290 * device control register to reflect the adapter settings. TFCE and RFCE
1291 * need to be explicitly set by software when a copper PHY is used because
1292 * autonegotiation is managed by the PHY rather than the MAC. Software must
1293 * also configure these bits when link is forced on a fiber connection.
1295 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1299 DEBUGFUNC("e1000_force_mac_fc_generic");
1301 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1304 * Because we didn't get link via the internal auto-negotiation
1305 * mechanism (we either forced link or we got link via PHY
1306 * auto-neg), we have to manually enable/disable transmit an
1307 * receive flow control.
1309 * The "Case" statement below enables/disable flow control
1310 * according to the "hw->fc.current_mode" parameter.
1312 * The possible values of the "fc" parameter are:
1313 * 0: Flow control is completely disabled
1314 * 1: Rx flow control is enabled (we can receive pause
1315 * frames but not send pause frames).
1316 * 2: Tx flow control is enabled (we can send pause frames
1317 * frames but we do not receive pause frames).
1318 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1319 * other: No other values should be possible at this point.
1321 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1323 switch (hw->fc.current_mode) {
1325 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1327 case e1000_fc_rx_pause:
1328 ctrl &= (~E1000_CTRL_TFCE);
1329 ctrl |= E1000_CTRL_RFCE;
1331 case e1000_fc_tx_pause:
1332 ctrl &= (~E1000_CTRL_RFCE);
1333 ctrl |= E1000_CTRL_TFCE;
1336 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1339 DEBUGOUT("Flow control param set incorrectly\n");
1340 return -E1000_ERR_CONFIG;
1343 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1345 return E1000_SUCCESS;
1349 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1350 * @hw: pointer to the HW structure
1352 * Checks the status of auto-negotiation after link up to ensure that the
1353 * speed and duplex were not forced. If the link needed to be forced, then
1354 * flow control needs to be forced also. If auto-negotiation is enabled
1355 * and did not fail, then we configure flow control based on our link
1358 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1360 struct e1000_mac_info *mac = &hw->mac;
1361 s32 ret_val = E1000_SUCCESS;
1362 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
1363 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1366 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1369 * Check for the case where we have fiber media and auto-neg failed
1370 * so we had to force link. In this case, we need to force the
1371 * configuration of the MAC to match the "fc" parameter.
1373 if (mac->autoneg_failed) {
1374 if (hw->phy.media_type == e1000_media_type_fiber ||
1375 hw->phy.media_type == e1000_media_type_internal_serdes)
1376 ret_val = e1000_force_mac_fc_generic(hw);
1378 if (hw->phy.media_type == e1000_media_type_copper)
1379 ret_val = e1000_force_mac_fc_generic(hw);
1383 DEBUGOUT("Error forcing flow control settings\n");
1388 * Check for the case where we have copper media and auto-neg is
1389 * enabled. In this case, we need to check and see if Auto-Neg
1390 * has completed, and if so, how the PHY and link partner has
1391 * flow control configured.
1393 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1395 * Read the MII Status Register and check to see if AutoNeg
1396 * has completed. We read this twice because this reg has
1397 * some "sticky" (latched) bits.
1399 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1402 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1406 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1407 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1412 * The AutoNeg process has completed, so we now need to
1413 * read both the Auto Negotiation Advertisement
1414 * Register (Address 4) and the Auto_Negotiation Base
1415 * Page Ability Register (Address 5) to determine how
1416 * flow control was negotiated.
1418 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1422 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1423 &mii_nway_lp_ability_reg);
1428 * Two bits in the Auto Negotiation Advertisement Register
1429 * (Address 4) and two bits in the Auto Negotiation Base
1430 * Page Ability Register (Address 5) determine flow control
1431 * for both the PHY and the link partner. The following
1432 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1433 * 1999, describes these PAUSE resolution bits and how flow
1434 * control is determined based upon these settings.
1435 * NOTE: DC = Don't Care
1437 * LOCAL DEVICE | LINK PARTNER
1438 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1439 *-------|---------|-------|---------|--------------------
1440 * 0 | 0 | DC | DC | e1000_fc_none
1441 * 0 | 1 | 0 | DC | e1000_fc_none
1442 * 0 | 1 | 1 | 0 | e1000_fc_none
1443 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1444 * 1 | 0 | 0 | DC | e1000_fc_none
1445 * 1 | DC | 1 | DC | e1000_fc_full
1446 * 1 | 1 | 0 | 0 | e1000_fc_none
1447 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1449 * Are both PAUSE bits set to 1? If so, this implies
1450 * Symmetric Flow Control is enabled at both ends. The
1451 * ASM_DIR bits are irrelevant per the spec.
1453 * For Symmetric Flow Control:
1455 * LOCAL DEVICE | LINK PARTNER
1456 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1457 *-------|---------|-------|---------|--------------------
1458 * 1 | DC | 1 | DC | E1000_fc_full
1461 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1462 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1464 * Now we need to check if the user selected Rx ONLY
1465 * of pause frames. In this case, we had to advertise
1466 * FULL flow control because we could not advertise Rx
1467 * ONLY. Hence, we must now check to see if we need to
1468 * turn OFF the TRANSMISSION of PAUSE frames.
1470 if (hw->fc.requested_mode == e1000_fc_full) {
1471 hw->fc.current_mode = e1000_fc_full;
1472 DEBUGOUT("Flow Control = FULL.\n");
1474 hw->fc.current_mode = e1000_fc_rx_pause;
1475 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1479 * For receiving PAUSE frames ONLY.
1481 * LOCAL DEVICE | LINK PARTNER
1482 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1483 *-------|---------|-------|---------|--------------------
1484 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1486 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1487 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1488 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1489 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1490 hw->fc.current_mode = e1000_fc_tx_pause;
1491 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1494 * For transmitting PAUSE frames ONLY.
1496 * LOCAL DEVICE | LINK PARTNER
1497 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1498 *-------|---------|-------|---------|--------------------
1499 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1501 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1502 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1503 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1504 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1505 hw->fc.current_mode = e1000_fc_rx_pause;
1506 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1509 * Per the IEEE spec, at this point flow control
1510 * should be disabled.
1512 hw->fc.current_mode = e1000_fc_none;
1513 DEBUGOUT("Flow Control = NONE.\n");
1517 * Now we need to do one last check... If we auto-
1518 * negotiated to HALF DUPLEX, flow control should not be
1519 * enabled per IEEE 802.3 spec.
1521 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1523 DEBUGOUT("Error getting link speed and duplex\n");
1527 if (duplex == HALF_DUPLEX)
1528 hw->fc.current_mode = e1000_fc_none;
1531 * Now we call a subroutine to actually force the MAC
1532 * controller to use the correct flow control settings.
1534 ret_val = e1000_force_mac_fc_generic(hw);
1536 DEBUGOUT("Error forcing flow control settings\n");
1542 * Check for the case where we have SerDes media and auto-neg is
1543 * enabled. In this case, we need to check and see if Auto-Neg
1544 * has completed, and if so, how the PHY and link partner has
1545 * flow control configured.
1547 if ((hw->phy.media_type == e1000_media_type_internal_serdes)
1550 * Read the PCS_LSTS and check to see if AutoNeg
1553 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1555 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1556 DEBUGOUT("PCS Auto Neg has not completed.\n");
1561 * The AutoNeg process has completed, so we now need to
1562 * read both the Auto Negotiation Advertisement
1563 * Register (PCS_ANADV) and the Auto_Negotiation Base
1564 * Page Ability Register (PCS_LPAB) to determine how
1565 * flow control was negotiated.
1567 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1568 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB);
1571 * Two bits in the Auto Negotiation Advertisement Register
1572 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1573 * Page Ability Register (PCS_LPAB) determine flow control
1574 * for both the PHY and the link partner. The following
1575 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1576 * 1999, describes these PAUSE resolution bits and how flow
1577 * control is determined based upon these settings.
1578 * NOTE: DC = Don't Care
1580 * LOCAL DEVICE | LINK PARTNER
1581 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1582 *-------|---------|-------|---------|--------------------
1583 * 0 | 0 | DC | DC | e1000_fc_none
1584 * 0 | 1 | 0 | DC | e1000_fc_none
1585 * 0 | 1 | 1 | 0 | e1000_fc_none
1586 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1587 * 1 | 0 | 0 | DC | e1000_fc_none
1588 * 1 | DC | 1 | DC | e1000_fc_full
1589 * 1 | 1 | 0 | 0 | e1000_fc_none
1590 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1592 * Are both PAUSE bits set to 1? If so, this implies
1593 * Symmetric Flow Control is enabled at both ends. The
1594 * ASM_DIR bits are irrelevant per the spec.
1596 * For Symmetric Flow Control:
1598 * LOCAL DEVICE | LINK PARTNER
1599 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1600 *-------|---------|-------|---------|--------------------
1601 * 1 | DC | 1 | DC | e1000_fc_full
1604 if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1605 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1607 * Now we need to check if the user selected Rx ONLY
1608 * of pause frames. In this case, we had to advertise
1609 * FULL flow control because we could not advertise Rx
1610 * ONLY. Hence, we must now check to see if we need to
1611 * turn OFF the TRANSMISSION of PAUSE frames.
1613 if (hw->fc.requested_mode == e1000_fc_full) {
1614 hw->fc.current_mode = e1000_fc_full;
1615 DEBUGOUT("Flow Control = FULL.\n");
1617 hw->fc.current_mode = e1000_fc_rx_pause;
1618 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1622 * For receiving PAUSE frames ONLY.
1624 * LOCAL DEVICE | LINK PARTNER
1625 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1626 *-------|---------|-------|---------|--------------------
1627 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1629 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1630 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1631 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1632 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1633 hw->fc.current_mode = e1000_fc_tx_pause;
1634 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1637 * For transmitting PAUSE frames ONLY.
1639 * LOCAL DEVICE | LINK PARTNER
1640 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1641 *-------|---------|-------|---------|--------------------
1642 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1644 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1645 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1646 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1647 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1648 hw->fc.current_mode = e1000_fc_rx_pause;
1649 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1652 * Per the IEEE spec, at this point flow control
1653 * should be disabled.
1655 hw->fc.current_mode = e1000_fc_none;
1656 DEBUGOUT("Flow Control = NONE.\n");
1660 * Now we call a subroutine to actually force the MAC
1661 * controller to use the correct flow control settings.
1663 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1664 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1665 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg);
1667 ret_val = e1000_force_mac_fc_generic(hw);
1669 DEBUGOUT("Error forcing flow control settings\n");
1674 return E1000_SUCCESS;
1678 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1679 * @hw: pointer to the HW structure
1680 * @speed: stores the current speed
1681 * @duplex: stores the current duplex
1683 * Read the status register for the current speed/duplex and store the current
1684 * speed and duplex for copper connections.
1686 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1691 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1693 status = E1000_READ_REG(hw, E1000_STATUS);
1694 if (status & E1000_STATUS_SPEED_1000) {
1695 *speed = SPEED_1000;
1696 DEBUGOUT("1000 Mbs, ");
1697 } else if (status & E1000_STATUS_SPEED_100) {
1699 DEBUGOUT("100 Mbs, ");
1702 DEBUGOUT("10 Mbs, ");
1705 if (status & E1000_STATUS_FD) {
1706 *duplex = FULL_DUPLEX;
1707 DEBUGOUT("Full Duplex\n");
1709 *duplex = HALF_DUPLEX;
1710 DEBUGOUT("Half Duplex\n");
1713 return E1000_SUCCESS;
1717 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1718 * @hw: pointer to the HW structure
1719 * @speed: stores the current speed
1720 * @duplex: stores the current duplex
1722 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1723 * for fiber/serdes links.
1725 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
1726 u16 *speed, u16 *duplex)
1728 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1730 *speed = SPEED_1000;
1731 *duplex = FULL_DUPLEX;
1733 return E1000_SUCCESS;
1737 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1738 * @hw: pointer to the HW structure
1740 * Acquire the HW semaphore to access the PHY or NVM
1742 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1745 s32 timeout = hw->nvm.word_size + 1;
1748 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1750 /* Get the SW semaphore */
1751 while (i < timeout) {
1752 swsm = E1000_READ_REG(hw, E1000_SWSM);
1753 if (!(swsm & E1000_SWSM_SMBI))
1761 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1762 return -E1000_ERR_NVM;
1765 /* Get the FW semaphore. */
1766 for (i = 0; i < timeout; i++) {
1767 swsm = E1000_READ_REG(hw, E1000_SWSM);
1768 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1770 /* Semaphore acquired if bit latched */
1771 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1778 /* Release semaphores */
1779 e1000_put_hw_semaphore_generic(hw);
1780 DEBUGOUT("Driver can't access the NVM\n");
1781 return -E1000_ERR_NVM;
1784 return E1000_SUCCESS;
1788 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1789 * @hw: pointer to the HW structure
1791 * Release hardware semaphore used to access the PHY or NVM
1793 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1797 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1799 swsm = E1000_READ_REG(hw, E1000_SWSM);
1801 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1803 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1807 * e1000_get_auto_rd_done_generic - Check for auto read completion
1808 * @hw: pointer to the HW structure
1810 * Check EEPROM for Auto Read done bit.
1812 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1816 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1818 while (i < AUTO_READ_DONE_TIMEOUT) {
1819 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1825 if (i == AUTO_READ_DONE_TIMEOUT) {
1826 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1827 return -E1000_ERR_RESET;
1830 return E1000_SUCCESS;
1834 * e1000_valid_led_default_generic - Verify a valid default LED config
1835 * @hw: pointer to the HW structure
1836 * @data: pointer to the NVM (EEPROM)
1838 * Read the EEPROM for the current default LED configuration. If the
1839 * LED configuration is not valid, set to a valid LED configuration.
1841 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1845 DEBUGFUNC("e1000_valid_led_default_generic");
1847 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1849 DEBUGOUT("NVM Read Error\n");
1853 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1854 *data = ID_LED_DEFAULT;
1856 return E1000_SUCCESS;
1860 * e1000_id_led_init_generic -
1861 * @hw: pointer to the HW structure
1864 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1866 struct e1000_mac_info *mac = &hw->mac;
1868 const u32 ledctl_mask = 0x000000FF;
1869 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1870 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1872 const u16 led_mask = 0x0F;
1874 DEBUGFUNC("e1000_id_led_init_generic");
1876 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1880 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1881 mac->ledctl_mode1 = mac->ledctl_default;
1882 mac->ledctl_mode2 = mac->ledctl_default;
1884 for (i = 0; i < 4; i++) {
1885 temp = (data >> (i << 2)) & led_mask;
1887 case ID_LED_ON1_DEF2:
1888 case ID_LED_ON1_ON2:
1889 case ID_LED_ON1_OFF2:
1890 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1891 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1893 case ID_LED_OFF1_DEF2:
1894 case ID_LED_OFF1_ON2:
1895 case ID_LED_OFF1_OFF2:
1896 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1897 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1904 case ID_LED_DEF1_ON2:
1905 case ID_LED_ON1_ON2:
1906 case ID_LED_OFF1_ON2:
1907 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1908 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1910 case ID_LED_DEF1_OFF2:
1911 case ID_LED_ON1_OFF2:
1912 case ID_LED_OFF1_OFF2:
1913 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1914 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1922 return E1000_SUCCESS;
1926 * e1000_setup_led_generic - Configures SW controllable LED
1927 * @hw: pointer to the HW structure
1929 * This prepares the SW controllable LED for use and saves the current state
1930 * of the LED so it can be later restored.
1932 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1936 DEBUGFUNC("e1000_setup_led_generic");
1938 if (hw->mac.ops.setup_led != e1000_setup_led_generic)
1939 return -E1000_ERR_CONFIG;
1941 if (hw->phy.media_type == e1000_media_type_fiber) {
1942 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1943 hw->mac.ledctl_default = ledctl;
1945 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1946 E1000_LEDCTL_LED0_MODE_MASK);
1947 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1948 E1000_LEDCTL_LED0_MODE_SHIFT);
1949 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1950 } else if (hw->phy.media_type == e1000_media_type_copper) {
1951 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1954 return E1000_SUCCESS;
1958 * e1000_cleanup_led_generic - Set LED config to default operation
1959 * @hw: pointer to the HW structure
1961 * Remove the current LED configuration and set the LED configuration
1962 * to the default value, saved from the EEPROM.
1964 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1966 DEBUGFUNC("e1000_cleanup_led_generic");
1968 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1969 return E1000_SUCCESS;
1973 * e1000_blink_led_generic - Blink LED
1974 * @hw: pointer to the HW structure
1976 * Blink the LEDs which are set to be on.
1978 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1980 u32 ledctl_blink = 0;
1983 DEBUGFUNC("e1000_blink_led_generic");
1985 if (hw->phy.media_type == e1000_media_type_fiber) {
1986 /* always blink LED0 for PCI-E fiber */
1987 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1988 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1991 * set the blink bit for each LED that's "on" (0x0E)
1994 ledctl_blink = hw->mac.ledctl_mode2;
1995 for (i = 0; i < 4; i++)
1996 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1997 E1000_LEDCTL_MODE_LED_ON)
1998 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
2002 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
2004 return E1000_SUCCESS;
2008 * e1000_led_on_generic - Turn LED on
2009 * @hw: pointer to the HW structure
2013 s32 e1000_led_on_generic(struct e1000_hw *hw)
2017 DEBUGFUNC("e1000_led_on_generic");
2019 switch (hw->phy.media_type) {
2020 case e1000_media_type_fiber:
2021 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2022 ctrl &= ~E1000_CTRL_SWDPIN0;
2023 ctrl |= E1000_CTRL_SWDPIO0;
2024 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2026 case e1000_media_type_copper:
2027 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
2033 return E1000_SUCCESS;
2037 * e1000_led_off_generic - Turn LED off
2038 * @hw: pointer to the HW structure
2042 s32 e1000_led_off_generic(struct e1000_hw *hw)
2046 DEBUGFUNC("e1000_led_off_generic");
2048 switch (hw->phy.media_type) {
2049 case e1000_media_type_fiber:
2050 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2051 ctrl |= E1000_CTRL_SWDPIN0;
2052 ctrl |= E1000_CTRL_SWDPIO0;
2053 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2055 case e1000_media_type_copper:
2056 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2062 return E1000_SUCCESS;
2066 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
2067 * @hw: pointer to the HW structure
2068 * @no_snoop: bitmap of snoop events
2070 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
2072 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
2076 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
2078 if (hw->bus.type != e1000_bus_type_pci_express)
2082 gcr = E1000_READ_REG(hw, E1000_GCR);
2083 gcr &= ~(PCIE_NO_SNOOP_ALL);
2085 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2090 * e1000_disable_pcie_master_generic - Disables PCI-express master access
2091 * @hw: pointer to the HW structure
2093 * Returns E1000_SUCCESS if successful, else returns -10
2094 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
2095 * the master requests to be disabled.
2097 * Disables PCI-Express master access and verifies there are no pending
2100 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2103 s32 timeout = MASTER_DISABLE_TIMEOUT;
2105 DEBUGFUNC("e1000_disable_pcie_master_generic");
2107 if (hw->bus.type != e1000_bus_type_pci_express)
2108 return E1000_SUCCESS;
2110 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2111 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2112 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2115 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2116 E1000_STATUS_GIO_MASTER_ENABLE))
2123 DEBUGOUT("Master requests are pending.\n");
2124 return -E1000_ERR_MASTER_REQUESTS_PENDING;
2127 return E1000_SUCCESS;
2131 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2132 * @hw: pointer to the HW structure
2134 * Reset the Adaptive Interframe Spacing throttle to default values.
2136 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2138 struct e1000_mac_info *mac = &hw->mac;
2140 DEBUGFUNC("e1000_reset_adaptive_generic");
2142 if (!mac->adaptive_ifs) {
2143 DEBUGOUT("Not in Adaptive IFS mode!\n");
2147 mac->current_ifs_val = 0;
2148 mac->ifs_min_val = IFS_MIN;
2149 mac->ifs_max_val = IFS_MAX;
2150 mac->ifs_step_size = IFS_STEP;
2151 mac->ifs_ratio = IFS_RATIO;
2153 mac->in_ifs_mode = false;
2154 E1000_WRITE_REG(hw, E1000_AIT, 0);
2158 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2159 * @hw: pointer to the HW structure
2161 * Update the Adaptive Interframe Spacing Throttle value based on the
2162 * time between transmitted packets and time between collisions.
2164 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2166 struct e1000_mac_info *mac = &hw->mac;
2168 DEBUGFUNC("e1000_update_adaptive_generic");
2170 if (!mac->adaptive_ifs) {
2171 DEBUGOUT("Not in Adaptive IFS mode!\n");
2175 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2176 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2177 mac->in_ifs_mode = true;
2178 if (mac->current_ifs_val < mac->ifs_max_val) {
2179 if (!mac->current_ifs_val)
2180 mac->current_ifs_val = mac->ifs_min_val;
2182 mac->current_ifs_val +=
2184 E1000_WRITE_REG(hw, E1000_AIT,
2185 mac->current_ifs_val);
2189 if (mac->in_ifs_mode &&
2190 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2191 mac->current_ifs_val = 0;
2192 mac->in_ifs_mode = false;
2193 E1000_WRITE_REG(hw, E1000_AIT, 0);
2199 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2200 * @hw: pointer to the HW structure
2202 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2203 * set, which is forced to MDI mode only.
2205 STATIC s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2207 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2209 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2210 DEBUGOUT("Invalid MDI setting detected\n");
2212 return -E1000_ERR_CONFIG;
2215 return E1000_SUCCESS;
2219 * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings
2220 * @hw: pointer to the HW structure
2222 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced
2225 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw *hw)
2227 DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic");
2229 return E1000_SUCCESS;
2233 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2234 * @hw: pointer to the HW structure
2235 * @reg: 32bit register offset such as E1000_SCTL
2236 * @offset: register offset to write to
2237 * @data: data to write at register offset
2239 * Writes an address/data control type register. There are several of these
2240 * and they all have the format address << 8 | data and bit 31 is polled for
2243 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2244 u32 offset, u8 data)
2246 u32 i, regvalue = 0;
2248 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2250 /* Set up the address and data */
2251 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
2252 E1000_WRITE_REG(hw, reg, regvalue);
2254 /* Poll the ready bit to see if the MDI read completed */
2255 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
2257 regvalue = E1000_READ_REG(hw, reg);
2258 if (regvalue & E1000_GEN_CTL_READY)
2261 if (!(regvalue & E1000_GEN_CTL_READY)) {
2262 DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2263 return -E1000_ERR_PHY;
2266 return E1000_SUCCESS;