1 // SPDX-License-Identifier: GPL-2.0
2 /*******************************************************************************
4 Intel(R) Gigabit Ethernet Linux driver
5 Copyright(c) 2007-2013 Intel Corporation.
8 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
9 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
11 *******************************************************************************/
13 #include "e1000_api.h"
16 * e1000_calculate_checksum - Calculate checksum for buffer
17 * @buffer: pointer to EEPROM
18 * @length: size of EEPROM to calculate a checksum for
20 * Calculates the checksum for some buffer on a specified length. The
21 * checksum calculated is returned.
23 u8 e1000_calculate_checksum(u8 *buffer, u32 length)
28 DEBUGFUNC("e1000_calculate_checksum");
33 for (i = 0; i < length; i++)
36 return (u8) (0 - sum);
40 * e1000_mng_enable_host_if_generic - Checks host interface is enabled
41 * @hw: pointer to the HW structure
43 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
45 * This function checks whether the HOST IF is enabled for command operation
46 * and also checks whether the previous command is completed. It busy waits
47 * in case of previous command is not completed.
49 s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw)
54 DEBUGFUNC("e1000_mng_enable_host_if_generic");
56 if (!hw->mac.arc_subsystem_valid) {
57 DEBUGOUT("ARC subsystem not valid.\n");
58 return -E1000_ERR_HOST_INTERFACE_COMMAND;
61 /* Check that the host interface is enabled. */
62 hicr = E1000_READ_REG(hw, E1000_HICR);
63 if (!(hicr & E1000_HICR_EN)) {
64 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
65 return -E1000_ERR_HOST_INTERFACE_COMMAND;
67 /* check the previous command is completed */
68 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
69 hicr = E1000_READ_REG(hw, E1000_HICR);
70 if (!(hicr & E1000_HICR_C))
75 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
76 DEBUGOUT("Previous command timeout failed .\n");
77 return -E1000_ERR_HOST_INTERFACE_COMMAND;
84 * e1000_check_mng_mode_generic - Generic check management mode
85 * @hw: pointer to the HW structure
87 * Reads the firmware semaphore register and returns true (>0) if
88 * manageability is enabled, else false (0).
90 bool e1000_check_mng_mode_generic(struct e1000_hw *hw)
92 u32 fwsm = E1000_READ_REG(hw, E1000_FWSM);
94 DEBUGFUNC("e1000_check_mng_mode_generic");
97 return (fwsm & E1000_FWSM_MODE_MASK) ==
98 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
102 * e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on Tx
103 * @hw: pointer to the HW structure
105 * Enables packet filtering on transmit packets if manageability is enabled
106 * and host interface is enabled.
108 bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw)
110 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
111 u32 *buffer = (u32 *)&hw->mng_cookie;
113 s32 ret_val, hdr_csum, csum;
116 DEBUGFUNC("e1000_enable_tx_pkt_filtering_generic");
118 hw->mac.tx_pkt_filtering = true;
120 /* No manageability, no filtering */
121 if (!hw->mac.ops.check_mng_mode(hw)) {
122 hw->mac.tx_pkt_filtering = false;
123 return hw->mac.tx_pkt_filtering;
126 /* If we can't read from the host interface for whatever
127 * reason, disable filtering.
129 ret_val = e1000_mng_enable_host_if_generic(hw);
130 if (ret_val != E1000_SUCCESS) {
131 hw->mac.tx_pkt_filtering = false;
132 return hw->mac.tx_pkt_filtering;
135 /* Read in the header. Length and offset are in dwords. */
136 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
137 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
138 for (i = 0; i < len; i++)
139 *(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF,
141 hdr_csum = hdr->checksum;
143 csum = e1000_calculate_checksum((u8 *)hdr,
144 E1000_MNG_DHCP_COOKIE_LENGTH);
145 /* If either the checksums or signature don't match, then
146 * the cookie area isn't considered valid, in which case we
147 * take the safe route of assuming Tx filtering is enabled.
149 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
150 hw->mac.tx_pkt_filtering = true;
151 return hw->mac.tx_pkt_filtering;
154 /* Cookie area is valid, make the final check for filtering. */
155 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
156 hw->mac.tx_pkt_filtering = false;
158 return hw->mac.tx_pkt_filtering;
162 * e1000_mng_write_cmd_header_generic - Writes manageability command header
163 * @hw: pointer to the HW structure
164 * @hdr: pointer to the host interface command header
166 * Writes the command header after does the checksum calculation.
168 s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
169 struct e1000_host_mng_command_header *hdr)
171 u16 i, length = sizeof(struct e1000_host_mng_command_header);
173 DEBUGFUNC("e1000_mng_write_cmd_header_generic");
175 /* Write the whole command header structure with new checksum. */
177 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
180 /* Write the relevant command block into the ram area. */
181 for (i = 0; i < length; i++) {
182 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
184 E1000_WRITE_FLUSH(hw);
187 return E1000_SUCCESS;
191 * e1000_mng_host_if_write_generic - Write to the manageability host interface
192 * @hw: pointer to the HW structure
193 * @buffer: pointer to the host interface buffer
194 * @length: size of the buffer
195 * @offset: location in the buffer to write to
196 * @sum: sum of the data (not checksum)
198 * This function writes the buffer content at the offset given on the host if.
199 * It also does alignment considerations to do the writes in most efficient
200 * way. Also fills up the sum of the buffer in *buffer parameter.
202 s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
203 u16 length, u16 offset, u8 *sum)
208 u16 remaining, i, j, prev_bytes;
210 DEBUGFUNC("e1000_mng_host_if_write_generic");
212 /* sum = only sum of the data and it is not checksum */
214 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
215 return -E1000_ERR_PARAM;
218 prev_bytes = offset & 0x3;
222 data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
223 for (j = prev_bytes; j < sizeof(u32); j++) {
224 *(tmp + j) = *bufptr++;
227 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);
228 length -= j - prev_bytes;
232 remaining = length & 0x3;
235 /* Calculate length in DWORDs */
238 /* The device driver writes the relevant command block into the
241 for (i = 0; i < length; i++) {
242 for (j = 0; j < sizeof(u32); j++) {
243 *(tmp + j) = *bufptr++;
247 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
251 for (j = 0; j < sizeof(u32); j++) {
253 *(tmp + j) = *bufptr++;
259 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
263 return E1000_SUCCESS;
267 * e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface
268 * @hw: pointer to the HW structure
269 * @buffer: pointer to the host interface
270 * @length: size of the buffer
272 * Writes the DHCP information to the host interface.
274 s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer,
277 struct e1000_host_mng_command_header hdr;
281 DEBUGFUNC("e1000_mng_write_dhcp_info_generic");
283 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
284 hdr.command_length = length;
289 /* Enable the host interface */
290 ret_val = e1000_mng_enable_host_if_generic(hw);
294 /* Populate the host interface with the contents of "buffer". */
295 ret_val = e1000_mng_host_if_write_generic(hw, buffer, length,
296 sizeof(hdr), &(hdr.checksum));
300 /* Write the manageability command header */
301 ret_val = e1000_mng_write_cmd_header_generic(hw, &hdr);
305 /* Tell the ARC a new command is pending. */
306 hicr = E1000_READ_REG(hw, E1000_HICR);
307 E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
309 return E1000_SUCCESS;
313 * e1000_enable_mng_pass_thru - Check if management passthrough is needed
314 * @hw: pointer to the HW structure
316 * Verifies the hardware needs to leave interface enabled so that frames can
317 * be directed to and from the management interface.
319 bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
324 DEBUGFUNC("e1000_enable_mng_pass_thru");
326 if (!hw->mac.asf_firmware_present)
329 manc = E1000_READ_REG(hw, E1000_MANC);
331 if (!(manc & E1000_MANC_RCV_TCO_EN))
334 if (hw->mac.has_fwsm) {
335 fwsm = E1000_READ_REG(hw, E1000_FWSM);
336 factps = E1000_READ_REG(hw, E1000_FACTPS);
338 if (!(factps & E1000_FACTPS_MNGCG) &&
339 ((fwsm & E1000_FWSM_MODE_MASK) ==
340 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)))
342 } else if ((manc & E1000_MANC_SMBUS_EN) &&
343 !(manc & E1000_MANC_ASF_EN)) {
351 * e1000_host_interface_command - Writes buffer to host interface
352 * @hw: pointer to the HW structure
353 * @buffer: contains a command to write
354 * @length: the byte length of the buffer, must be multiple of 4 bytes
356 * Writes a buffer to the Host Interface. Upon success, returns E1000_SUCCESS
357 * else returns E1000_ERR_HOST_INTERFACE_COMMAND.
359 s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length)
363 DEBUGFUNC("e1000_host_interface_command");
365 if (!(hw->mac.arc_subsystem_valid)) {
366 DEBUGOUT("Hardware doesn't support host interface command.\n");
367 return E1000_SUCCESS;
370 if (!hw->mac.asf_firmware_present) {
371 DEBUGOUT("Firmware is not present.\n");
372 return E1000_SUCCESS;
375 if (length == 0 || length & 0x3 ||
376 length > E1000_HI_MAX_BLOCK_BYTE_LENGTH) {
377 DEBUGOUT("Buffer length failure.\n");
378 return -E1000_ERR_HOST_INTERFACE_COMMAND;
381 /* Check that the host interface is enabled. */
382 hicr = E1000_READ_REG(hw, E1000_HICR);
383 if (!(hicr & E1000_HICR_EN)) {
384 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
385 return -E1000_ERR_HOST_INTERFACE_COMMAND;
388 /* Calculate length in DWORDs */
391 /* The device driver writes the relevant command block
394 for (i = 0; i < length; i++)
395 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
396 *((u32 *)buffer + i));
398 /* Setting this bit tells the ARC that a new command is pending. */
399 E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
401 for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
402 hicr = E1000_READ_REG(hw, E1000_HICR);
403 if (!(hicr & E1000_HICR_C))
408 /* Check command successful completion. */
409 if (i == E1000_HI_COMMAND_TIMEOUT ||
410 (!(E1000_READ_REG(hw, E1000_HICR) & E1000_HICR_SV))) {
411 DEBUGOUT("Command has failed with no status valid.\n");
412 return -E1000_ERR_HOST_INTERFACE_COMMAND;
415 for (i = 0; i < length; i++)
416 *((u32 *)buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
420 return E1000_SUCCESS;
423 * e1000_load_firmware - Writes proxy FW code buffer to host interface
425 * @hw: pointer to the HW structure
426 * @buffer: contains a firmware to write
427 * @length: the byte length of the buffer, must be multiple of 4 bytes
429 * Upon success returns E1000_SUCCESS, returns E1000_ERR_CONFIG if not enabled
430 * in HW else returns E1000_ERR_HOST_INTERFACE_COMMAND.
432 s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length)
434 u32 hicr, hibba, fwsm, icr, i;
436 DEBUGFUNC("e1000_load_firmware");
438 if (hw->mac.type < e1000_i210) {
439 DEBUGOUT("Hardware doesn't support loading FW by the driver\n");
440 return -E1000_ERR_CONFIG;
443 /* Check that the host interface is enabled. */
444 hicr = E1000_READ_REG(hw, E1000_HICR);
445 if (!(hicr & E1000_HICR_EN)) {
446 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
447 return -E1000_ERR_CONFIG;
449 if (!(hicr & E1000_HICR_MEMORY_BASE_EN)) {
450 DEBUGOUT("E1000_HICR_MEMORY_BASE_EN bit disabled.\n");
451 return -E1000_ERR_CONFIG;
454 if (length == 0 || length & 0x3 || length > E1000_HI_FW_MAX_LENGTH) {
455 DEBUGOUT("Buffer length failure.\n");
456 return -E1000_ERR_INVALID_ARGUMENT;
459 /* Clear notification from ROM-FW by reading ICR register */
460 icr = E1000_READ_REG(hw, E1000_ICR_V2);
463 hicr = E1000_READ_REG(hw, E1000_HICR);
464 hicr |= E1000_HICR_FW_RESET_ENABLE;
465 E1000_WRITE_REG(hw, E1000_HICR, hicr);
466 hicr |= E1000_HICR_FW_RESET;
467 E1000_WRITE_REG(hw, E1000_HICR, hicr);
468 E1000_WRITE_FLUSH(hw);
470 /* Wait till MAC notifies about its readiness after ROM-FW reset */
471 for (i = 0; i < (E1000_HI_COMMAND_TIMEOUT * 2); i++) {
472 icr = E1000_READ_REG(hw, E1000_ICR_V2);
473 if (icr & E1000_ICR_MNG)
478 /* Check for timeout */
479 if (i == E1000_HI_COMMAND_TIMEOUT) {
480 DEBUGOUT("FW reset failed.\n");
481 return -E1000_ERR_HOST_INTERFACE_COMMAND;
484 /* Wait till MAC is ready to accept new FW code */
485 for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
486 fwsm = E1000_READ_REG(hw, E1000_FWSM);
487 if ((fwsm & E1000_FWSM_FW_VALID) &&
488 ((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT ==
489 E1000_FWSM_HI_EN_ONLY_MODE))
494 /* Check for timeout */
495 if (i == E1000_HI_COMMAND_TIMEOUT) {
496 DEBUGOUT("FW reset failed.\n");
497 return -E1000_ERR_HOST_INTERFACE_COMMAND;
500 /* Calculate length in DWORDs */
503 /* The device driver writes the relevant FW code block
504 * into the ram area in DWORDs via 1kB ram addressing window.
506 for (i = 0; i < length; i++) {
507 if (!(i % E1000_HI_FW_BLOCK_DWORD_LENGTH)) {
508 /* Point to correct 1kB ram window */
509 hibba = E1000_HI_FW_BASE_ADDRESS +
510 ((E1000_HI_FW_BLOCK_DWORD_LENGTH << 2) *
511 (i / E1000_HI_FW_BLOCK_DWORD_LENGTH));
513 E1000_WRITE_REG(hw, E1000_HIBBA, hibba);
516 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF,
517 i % E1000_HI_FW_BLOCK_DWORD_LENGTH,
518 *((u32 *)buffer + i));
521 /* Setting this bit tells the ARC that a new FW is ready to execute. */
522 hicr = E1000_READ_REG(hw, E1000_HICR);
523 E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
525 for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
526 hicr = E1000_READ_REG(hw, E1000_HICR);
527 if (!(hicr & E1000_HICR_C))
532 /* Check for successful FW start. */
533 if (i == E1000_HI_COMMAND_TIMEOUT) {
534 DEBUGOUT("New FW did not start within timeout period.\n");
535 return -E1000_ERR_HOST_INTERFACE_COMMAND;
538 return E1000_SUCCESS;