1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*******************************************************************************
4 Intel(R) Gigabit Ethernet Linux driver
5 Copyright(c) 2007-2013 Intel Corporation.
8 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
9 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
11 *******************************************************************************/
14 /* glue for the OS independent part of e1000
15 * includes register access macros
18 #ifndef _E1000_OSDEP_H_
19 #define _E1000_OSDEP_H_
21 #include <linux/pci.h>
22 #include <linux/delay.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/sched.h>
28 #ifndef __INTEL_COMPILER
29 #pragma GCC diagnostic ignored "-Wunused-function"
32 #define usec_delay(x) udelay(x)
33 #define usec_delay_irq(x) udelay(x)
35 #define msec_delay(x) do { \
36 /* Don't mdelay in interrupt context! */ \
43 /* Some workarounds require millisecond delays and are run during interrupt
44 * context. Most notably, when establishing link, the phy may need tweaking
45 * but cannot process phy register reads/writes faster than millisecond
46 * intervals...and we establish link due to a "link status change" interrupt.
48 #define msec_delay_irq(x) mdelay(x)
51 #define PCI_COMMAND_REGISTER PCI_COMMAND
52 #define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
53 #define ETH_ADDR_LEN ETH_ALEN
56 #define E1000_BIG_ENDIAN __BIG_ENDIAN
61 #define DEBUGOUT(S) printk(KERN_DEBUG S)
62 #define DEBUGOUT1(S, A...) printk(KERN_DEBUG S, ## A)
65 #define DEBUGOUT1(S, A...)
69 #define DEBUGFUNC(F) DEBUGOUT(F "\n")
73 #define DEBUGOUT2 DEBUGOUT1
74 #define DEBUGOUT3 DEBUGOUT2
75 #define DEBUGOUT7 DEBUGOUT3
77 #define E1000_REGISTER(a, reg) reg
79 #define E1000_WRITE_REG(a, reg, value) ( \
80 writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg))))
82 #define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_REGISTER(a, reg)))
84 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
85 writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2))))
87 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
88 readl((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2)))
90 #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
91 #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
93 #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
94 writew((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1))))
96 #define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
97 readw((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1)))
99 #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
100 writeb((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + (offset))))
102 #define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
103 readb((a)->hw_addr + E1000_REGISTER(a, reg) + (offset)))
105 #define E1000_WRITE_REG_IO(a, reg, offset) do { \
106 outl(reg, ((a)->io_base)); \
107 outl(offset, ((a)->io_base + 4)); } while (0)
109 #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
111 #define E1000_WRITE_FLASH_REG(a, reg, value) ( \
112 writel((value), ((a)->flash_address + reg)))
114 #define E1000_WRITE_FLASH_REG16(a, reg, value) ( \
115 writew((value), ((a)->flash_address + reg)))
117 #define E1000_READ_FLASH_REG(a, reg) (readl((a)->flash_address + reg))
119 #define E1000_READ_FLASH_REG16(a, reg) (readw((a)->flash_address + reg))
121 #endif /* _E1000_OSDEP_H_ */