1 // SPDX-License-Identifier: GPL-2.0
2 /*******************************************************************************
4 Intel(R) Gigabit Ethernet Linux driver
5 Copyright(c) 2007-2013 Intel Corporation.
8 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
9 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
11 *******************************************************************************/
13 #include "e1000_api.h"
15 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
16 /* Cable length tables */
17 static const u16 e1000_m88_cable_length_table[] = {
18 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
19 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
20 (sizeof(e1000_m88_cable_length_table) / \
21 sizeof(e1000_m88_cable_length_table[0]))
23 static const u16 e1000_igp_2_cable_length_table[] = {
24 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
25 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
26 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
27 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
28 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
29 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
30 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
32 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
33 (sizeof(e1000_igp_2_cable_length_table) / \
34 sizeof(e1000_igp_2_cable_length_table[0]))
37 * e1000_init_phy_ops_generic - Initialize PHY function pointers
38 * @hw: pointer to the HW structure
40 * Setups up the function pointers to no-op functions
42 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
44 struct e1000_phy_info *phy = &hw->phy;
45 DEBUGFUNC("e1000_init_phy_ops_generic");
47 /* Initialize function pointers */
48 phy->ops.init_params = e1000_null_ops_generic;
49 phy->ops.acquire = e1000_null_ops_generic;
50 phy->ops.check_polarity = e1000_null_ops_generic;
51 phy->ops.check_reset_block = e1000_null_ops_generic;
52 phy->ops.commit = e1000_null_ops_generic;
53 phy->ops.force_speed_duplex = e1000_null_ops_generic;
54 phy->ops.get_cfg_done = e1000_null_ops_generic;
55 phy->ops.get_cable_length = e1000_null_ops_generic;
56 phy->ops.get_info = e1000_null_ops_generic;
57 phy->ops.set_page = e1000_null_set_page;
58 phy->ops.read_reg = e1000_null_read_reg;
59 phy->ops.read_reg_locked = e1000_null_read_reg;
60 phy->ops.read_reg_page = e1000_null_read_reg;
61 phy->ops.release = e1000_null_phy_generic;
62 phy->ops.reset = e1000_null_ops_generic;
63 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
64 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
65 phy->ops.write_reg = e1000_null_write_reg;
66 phy->ops.write_reg_locked = e1000_null_write_reg;
67 phy->ops.write_reg_page = e1000_null_write_reg;
68 phy->ops.power_up = e1000_null_phy_generic;
69 phy->ops.power_down = e1000_null_phy_generic;
70 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
71 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
75 * e1000_null_set_page - No-op function, return 0
76 * @hw: pointer to the HW structure
78 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw,
79 u16 E1000_UNUSEDARG data)
81 DEBUGFUNC("e1000_null_set_page");
86 * e1000_null_read_reg - No-op function, return 0
87 * @hw: pointer to the HW structure
89 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw,
90 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data)
92 DEBUGFUNC("e1000_null_read_reg");
97 * e1000_null_phy_generic - No-op function, return void
98 * @hw: pointer to the HW structure
100 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw)
102 DEBUGFUNC("e1000_null_phy_generic");
107 * e1000_null_lplu_state - No-op function, return 0
108 * @hw: pointer to the HW structure
110 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw,
111 bool E1000_UNUSEDARG active)
113 DEBUGFUNC("e1000_null_lplu_state");
114 return E1000_SUCCESS;
118 * e1000_null_write_reg - No-op function, return 0
119 * @hw: pointer to the HW structure
121 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,
122 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data)
124 DEBUGFUNC("e1000_null_write_reg");
125 return E1000_SUCCESS;
129 * e1000_read_i2c_byte_null - No-op function, return 0
130 * @hw: pointer to hardware structure
131 * @byte_offset: byte offset to write
132 * @dev_addr: device address
133 * @data: data value read
136 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
137 u8 E1000_UNUSEDARG byte_offset,
138 u8 E1000_UNUSEDARG dev_addr,
139 u8 E1000_UNUSEDARG *data)
141 DEBUGFUNC("e1000_read_i2c_byte_null");
142 return E1000_SUCCESS;
146 * e1000_write_i2c_byte_null - No-op function, return 0
147 * @hw: pointer to hardware structure
148 * @byte_offset: byte offset to write
149 * @dev_addr: device address
150 * @data: data value to write
153 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
154 u8 E1000_UNUSEDARG byte_offset,
155 u8 E1000_UNUSEDARG dev_addr,
156 u8 E1000_UNUSEDARG data)
158 DEBUGFUNC("e1000_write_i2c_byte_null");
159 return E1000_SUCCESS;
163 * e1000_check_reset_block_generic - Check if PHY reset is blocked
164 * @hw: pointer to the HW structure
166 * Read the PHY management control register and check whether a PHY reset
167 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
168 * return E1000_BLK_PHY_RESET (12).
170 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
174 DEBUGFUNC("e1000_check_reset_block");
176 manc = E1000_READ_REG(hw, E1000_MANC);
178 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
179 E1000_BLK_PHY_RESET : E1000_SUCCESS;
183 * e1000_get_phy_id - Retrieve the PHY ID and revision
184 * @hw: pointer to the HW structure
186 * Reads the PHY registers and stores the PHY ID and possibly the PHY
187 * revision in the hardware structure.
189 s32 e1000_get_phy_id(struct e1000_hw *hw)
191 struct e1000_phy_info *phy = &hw->phy;
192 s32 ret_val = E1000_SUCCESS;
195 DEBUGFUNC("e1000_get_phy_id");
197 if (!phy->ops.read_reg)
198 return E1000_SUCCESS;
200 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
204 phy->id = (u32)(phy_id << 16);
206 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
210 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
211 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
214 return E1000_SUCCESS;
218 * e1000_phy_reset_dsp_generic - Reset PHY DSP
219 * @hw: pointer to the HW structure
221 * Reset the digital signal processor.
223 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
227 DEBUGFUNC("e1000_phy_reset_dsp_generic");
229 if (!hw->phy.ops.write_reg)
230 return E1000_SUCCESS;
232 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
236 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
240 * e1000_read_phy_reg_mdic - Read MDI control register
241 * @hw: pointer to the HW structure
242 * @offset: register offset to be read
243 * @data: pointer to the read data
245 * Reads the MDI control register in the PHY at offset and stores the
246 * information read to data.
248 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
250 struct e1000_phy_info *phy = &hw->phy;
253 DEBUGFUNC("e1000_read_phy_reg_mdic");
255 if (offset > MAX_PHY_REG_ADDRESS) {
256 DEBUGOUT1("PHY Address %d is out of range\n", offset);
257 return -E1000_ERR_PARAM;
260 /* Set up Op-code, Phy Address, and register offset in the MDI
261 * Control register. The MAC will take care of interfacing with the
262 * PHY to retrieve the desired data.
264 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
265 (phy->addr << E1000_MDIC_PHY_SHIFT) |
266 (E1000_MDIC_OP_READ));
268 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
270 /* Poll the ready bit to see if the MDI read completed
271 * Increasing the time out as testing showed failures with
274 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
276 mdic = E1000_READ_REG(hw, E1000_MDIC);
277 if (mdic & E1000_MDIC_READY)
280 if (!(mdic & E1000_MDIC_READY)) {
281 DEBUGOUT("MDI Read did not complete\n");
282 return -E1000_ERR_PHY;
284 if (mdic & E1000_MDIC_ERROR) {
285 DEBUGOUT("MDI Error\n");
286 return -E1000_ERR_PHY;
288 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
289 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
291 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
292 return -E1000_ERR_PHY;
296 return E1000_SUCCESS;
300 * e1000_write_phy_reg_mdic - Write MDI control register
301 * @hw: pointer to the HW structure
302 * @offset: register offset to write to
303 * @data: data to write to register at offset
305 * Writes data to MDI control register in the PHY at offset.
307 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
309 struct e1000_phy_info *phy = &hw->phy;
312 DEBUGFUNC("e1000_write_phy_reg_mdic");
314 if (offset > MAX_PHY_REG_ADDRESS) {
315 DEBUGOUT1("PHY Address %d is out of range\n", offset);
316 return -E1000_ERR_PARAM;
319 /* Set up Op-code, Phy Address, and register offset in the MDI
320 * Control register. The MAC will take care of interfacing with the
321 * PHY to retrieve the desired data.
323 mdic = (((u32)data) |
324 (offset << E1000_MDIC_REG_SHIFT) |
325 (phy->addr << E1000_MDIC_PHY_SHIFT) |
326 (E1000_MDIC_OP_WRITE));
328 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
330 /* Poll the ready bit to see if the MDI read completed
331 * Increasing the time out as testing showed failures with
334 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
336 mdic = E1000_READ_REG(hw, E1000_MDIC);
337 if (mdic & E1000_MDIC_READY)
340 if (!(mdic & E1000_MDIC_READY)) {
341 DEBUGOUT("MDI Write did not complete\n");
342 return -E1000_ERR_PHY;
344 if (mdic & E1000_MDIC_ERROR) {
345 DEBUGOUT("MDI Error\n");
346 return -E1000_ERR_PHY;
348 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
349 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
351 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
352 return -E1000_ERR_PHY;
355 return E1000_SUCCESS;
359 * e1000_read_phy_reg_i2c - Read PHY register using i2c
360 * @hw: pointer to the HW structure
361 * @offset: register offset to be read
362 * @data: pointer to the read data
364 * Reads the PHY register at offset using the i2c interface and stores the
365 * retrieved information in data.
367 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
369 struct e1000_phy_info *phy = &hw->phy;
372 DEBUGFUNC("e1000_read_phy_reg_i2c");
374 /* Set up Op-code, Phy Address, and register address in the I2CCMD
375 * register. The MAC will take care of interfacing with the
376 * PHY to retrieve the desired data.
378 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
379 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
380 (E1000_I2CCMD_OPCODE_READ));
382 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
384 /* Poll the ready bit to see if the I2C read completed */
385 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
387 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
388 if (i2ccmd & E1000_I2CCMD_READY)
391 if (!(i2ccmd & E1000_I2CCMD_READY)) {
392 DEBUGOUT("I2CCMD Read did not complete\n");
393 return -E1000_ERR_PHY;
395 if (i2ccmd & E1000_I2CCMD_ERROR) {
396 DEBUGOUT("I2CCMD Error bit set\n");
397 return -E1000_ERR_PHY;
400 /* Need to byte-swap the 16-bit value. */
401 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
403 return E1000_SUCCESS;
407 * e1000_write_phy_reg_i2c - Write PHY register using i2c
408 * @hw: pointer to the HW structure
409 * @offset: register offset to write to
410 * @data: data to write at register offset
412 * Writes the data to PHY register at the offset using the i2c interface.
414 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
416 struct e1000_phy_info *phy = &hw->phy;
418 u16 phy_data_swapped;
420 DEBUGFUNC("e1000_write_phy_reg_i2c");
422 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
423 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
424 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
426 return -E1000_ERR_CONFIG;
429 /* Swap the data bytes for the I2C interface */
430 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
432 /* Set up Op-code, Phy Address, and register address in the I2CCMD
433 * register. The MAC will take care of interfacing with the
434 * PHY to retrieve the desired data.
436 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
437 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
438 E1000_I2CCMD_OPCODE_WRITE |
441 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
443 /* Poll the ready bit to see if the I2C read completed */
444 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
446 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
447 if (i2ccmd & E1000_I2CCMD_READY)
450 if (!(i2ccmd & E1000_I2CCMD_READY)) {
451 DEBUGOUT("I2CCMD Write did not complete\n");
452 return -E1000_ERR_PHY;
454 if (i2ccmd & E1000_I2CCMD_ERROR) {
455 DEBUGOUT("I2CCMD Error bit set\n");
456 return -E1000_ERR_PHY;
459 return E1000_SUCCESS;
463 * e1000_read_sfp_data_byte - Reads SFP module data.
464 * @hw: pointer to the HW structure
465 * @offset: byte location offset to be read
466 * @data: read data buffer pointer
468 * Reads one byte from SFP module data stored
469 * in SFP resided EEPROM memory or SFP diagnostic area.
470 * Function should be called with
471 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
472 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
475 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
481 DEBUGFUNC("e1000_read_sfp_data_byte");
483 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
484 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
485 return -E1000_ERR_PHY;
488 /* Set up Op-code, EEPROM Address,in the I2CCMD
489 * register. The MAC will take care of interfacing with the
490 * EEPROM to retrieve the desired data.
492 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
493 E1000_I2CCMD_OPCODE_READ);
495 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
497 /* Poll the ready bit to see if the I2C read completed */
498 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
500 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
501 if (data_local & E1000_I2CCMD_READY)
504 if (!(data_local & E1000_I2CCMD_READY)) {
505 DEBUGOUT("I2CCMD Read did not complete\n");
506 return -E1000_ERR_PHY;
508 if (data_local & E1000_I2CCMD_ERROR) {
509 DEBUGOUT("I2CCMD Error bit set\n");
510 return -E1000_ERR_PHY;
512 *data = (u8) data_local & 0xFF;
514 return E1000_SUCCESS;
518 * e1000_write_sfp_data_byte - Writes SFP module data.
519 * @hw: pointer to the HW structure
520 * @offset: byte location offset to write to
521 * @data: data to write
523 * Writes one byte to SFP module data stored
524 * in SFP resided EEPROM memory or SFP diagnostic area.
525 * Function should be called with
526 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
527 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
530 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
536 DEBUGFUNC("e1000_write_sfp_data_byte");
538 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
539 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
540 return -E1000_ERR_PHY;
542 /* The programming interface is 16 bits wide
543 * so we need to read the whole word first
544 * then update appropriate byte lane and write
545 * the updated word back.
547 /* Set up Op-code, EEPROM Address,in the I2CCMD
548 * register. The MAC will take care of interfacing
549 * with an EEPROM to write the data given.
551 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
552 E1000_I2CCMD_OPCODE_READ);
553 /* Set a command to read single word */
554 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
555 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
557 /* Poll the ready bit to see if lastly
558 * launched I2C operation completed
560 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
561 if (i2ccmd & E1000_I2CCMD_READY) {
562 /* Check if this is READ or WRITE phase */
563 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
564 E1000_I2CCMD_OPCODE_READ) {
565 /* Write the selected byte
566 * lane and update whole word
568 data_local = i2ccmd & 0xFF00;
571 E1000_I2CCMD_REG_ADDR_SHIFT) |
572 E1000_I2CCMD_OPCODE_WRITE | data_local);
573 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
579 if (!(i2ccmd & E1000_I2CCMD_READY)) {
580 DEBUGOUT("I2CCMD Write did not complete\n");
581 return -E1000_ERR_PHY;
583 if (i2ccmd & E1000_I2CCMD_ERROR) {
584 DEBUGOUT("I2CCMD Error bit set\n");
585 return -E1000_ERR_PHY;
587 return E1000_SUCCESS;
591 * e1000_read_phy_reg_m88 - Read m88 PHY register
592 * @hw: pointer to the HW structure
593 * @offset: register offset to be read
594 * @data: pointer to the read data
596 * Acquires semaphore, if necessary, then reads the PHY register at offset
597 * and storing the retrieved information in data. Release any acquired
598 * semaphores before exiting.
600 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
604 DEBUGFUNC("e1000_read_phy_reg_m88");
606 if (!hw->phy.ops.acquire)
607 return E1000_SUCCESS;
609 ret_val = hw->phy.ops.acquire(hw);
613 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
616 hw->phy.ops.release(hw);
622 * e1000_write_phy_reg_m88 - Write m88 PHY register
623 * @hw: pointer to the HW structure
624 * @offset: register offset to write to
625 * @data: data to write at register offset
627 * Acquires semaphore, if necessary, then writes the data to PHY register
628 * at the offset. Release any acquired semaphores before exiting.
630 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
634 DEBUGFUNC("e1000_write_phy_reg_m88");
636 if (!hw->phy.ops.acquire)
637 return E1000_SUCCESS;
639 ret_val = hw->phy.ops.acquire(hw);
643 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
646 hw->phy.ops.release(hw);
652 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
653 * @hw: pointer to the HW structure
654 * @page: page to set (shifted left when necessary)
656 * Sets PHY page required for PHY register access. Assumes semaphore is
657 * already acquired. Note, this function sets phy.addr to 1 so the caller
658 * must set it appropriately (if necessary) after this function returns.
660 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
662 DEBUGFUNC("e1000_set_page_igp");
664 DEBUGOUT1("Setting page 0x%x\n", page);
668 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
672 * __e1000_read_phy_reg_igp - Read igp PHY register
673 * @hw: pointer to the HW structure
674 * @offset: register offset to be read
675 * @data: pointer to the read data
676 * @locked: semaphore has already been acquired or not
678 * Acquires semaphore, if necessary, then reads the PHY register at offset
679 * and stores the retrieved information in data. Release any acquired
680 * semaphores before exiting.
682 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
685 s32 ret_val = E1000_SUCCESS;
687 DEBUGFUNC("__e1000_read_phy_reg_igp");
690 if (!hw->phy.ops.acquire)
691 return E1000_SUCCESS;
693 ret_val = hw->phy.ops.acquire(hw);
698 if (offset > MAX_PHY_MULTI_PAGE_REG)
699 ret_val = e1000_write_phy_reg_mdic(hw,
700 IGP01E1000_PHY_PAGE_SELECT,
703 ret_val = e1000_read_phy_reg_mdic(hw,
704 MAX_PHY_REG_ADDRESS & offset,
707 hw->phy.ops.release(hw);
713 * e1000_read_phy_reg_igp - Read igp PHY register
714 * @hw: pointer to the HW structure
715 * @offset: register offset to be read
716 * @data: pointer to the read data
718 * Acquires semaphore then reads the PHY register at offset and stores the
719 * retrieved information in data.
720 * Release the acquired semaphore before exiting.
722 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
724 return __e1000_read_phy_reg_igp(hw, offset, data, false);
728 * e1000_read_phy_reg_igp_locked - Read igp PHY register
729 * @hw: pointer to the HW structure
730 * @offset: register offset to be read
731 * @data: pointer to the read data
733 * Reads the PHY register at offset and stores the retrieved information
734 * in data. Assumes semaphore already acquired.
736 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
738 return __e1000_read_phy_reg_igp(hw, offset, data, true);
742 * e1000_write_phy_reg_igp - Write igp PHY register
743 * @hw: pointer to the HW structure
744 * @offset: register offset to write to
745 * @data: data to write at register offset
746 * @locked: semaphore has already been acquired or not
748 * Acquires semaphore, if necessary, then writes the data to PHY register
749 * at the offset. Release any acquired semaphores before exiting.
751 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
754 s32 ret_val = E1000_SUCCESS;
756 DEBUGFUNC("e1000_write_phy_reg_igp");
759 if (!hw->phy.ops.acquire)
760 return E1000_SUCCESS;
762 ret_val = hw->phy.ops.acquire(hw);
767 if (offset > MAX_PHY_MULTI_PAGE_REG)
768 ret_val = e1000_write_phy_reg_mdic(hw,
769 IGP01E1000_PHY_PAGE_SELECT,
772 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
776 hw->phy.ops.release(hw);
782 * e1000_write_phy_reg_igp - Write igp PHY register
783 * @hw: pointer to the HW structure
784 * @offset: register offset to write to
785 * @data: data to write at register offset
787 * Acquires semaphore then writes the data to PHY register
788 * at the offset. Release any acquired semaphores before exiting.
790 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
792 return __e1000_write_phy_reg_igp(hw, offset, data, false);
796 * e1000_write_phy_reg_igp_locked - Write igp PHY register
797 * @hw: pointer to the HW structure
798 * @offset: register offset to write to
799 * @data: data to write at register offset
801 * Writes the data to PHY register at the offset.
802 * Assumes semaphore already acquired.
804 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
806 return __e1000_write_phy_reg_igp(hw, offset, data, true);
810 * __e1000_read_kmrn_reg - Read kumeran register
811 * @hw: pointer to the HW structure
812 * @offset: register offset to be read
813 * @data: pointer to the read data
814 * @locked: semaphore has already been acquired or not
816 * Acquires semaphore, if necessary. Then reads the PHY register at offset
817 * using the kumeran interface. The information retrieved is stored in data.
818 * Release any acquired semaphores before exiting.
820 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
825 DEBUGFUNC("__e1000_read_kmrn_reg");
828 s32 ret_val = E1000_SUCCESS;
830 if (!hw->phy.ops.acquire)
831 return E1000_SUCCESS;
833 ret_val = hw->phy.ops.acquire(hw);
838 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
839 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
840 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
841 E1000_WRITE_FLUSH(hw);
845 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
846 *data = (u16)kmrnctrlsta;
849 hw->phy.ops.release(hw);
851 return E1000_SUCCESS;
855 * e1000_read_kmrn_reg_generic - Read kumeran register
856 * @hw: pointer to the HW structure
857 * @offset: register offset to be read
858 * @data: pointer to the read data
860 * Acquires semaphore then reads the PHY register at offset using the
861 * kumeran interface. The information retrieved is stored in data.
862 * Release the acquired semaphore before exiting.
864 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
866 return __e1000_read_kmrn_reg(hw, offset, data, false);
870 * e1000_read_kmrn_reg_locked - Read kumeran register
871 * @hw: pointer to the HW structure
872 * @offset: register offset to be read
873 * @data: pointer to the read data
875 * Reads the PHY register at offset using the kumeran interface. The
876 * information retrieved is stored in data.
877 * Assumes semaphore already acquired.
879 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
881 return __e1000_read_kmrn_reg(hw, offset, data, true);
885 * __e1000_write_kmrn_reg - Write kumeran register
886 * @hw: pointer to the HW structure
887 * @offset: register offset to write to
888 * @data: data to write at register offset
889 * @locked: semaphore has already been acquired or not
891 * Acquires semaphore, if necessary. Then write the data to PHY register
892 * at the offset using the kumeran interface. Release any acquired semaphores
895 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
900 DEBUGFUNC("e1000_write_kmrn_reg_generic");
903 s32 ret_val = E1000_SUCCESS;
905 if (!hw->phy.ops.acquire)
906 return E1000_SUCCESS;
908 ret_val = hw->phy.ops.acquire(hw);
913 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
914 E1000_KMRNCTRLSTA_OFFSET) | data;
915 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
916 E1000_WRITE_FLUSH(hw);
921 hw->phy.ops.release(hw);
923 return E1000_SUCCESS;
927 * e1000_write_kmrn_reg_generic - Write kumeran register
928 * @hw: pointer to the HW structure
929 * @offset: register offset to write to
930 * @data: data to write at register offset
932 * Acquires semaphore then writes the data to the PHY register at the offset
933 * using the kumeran interface. Release the acquired semaphore before exiting.
935 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
937 return __e1000_write_kmrn_reg(hw, offset, data, false);
941 * e1000_write_kmrn_reg_locked - Write kumeran register
942 * @hw: pointer to the HW structure
943 * @offset: register offset to write to
944 * @data: data to write at register offset
946 * Write the data to PHY register at the offset using the kumeran interface.
947 * Assumes semaphore already acquired.
949 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
951 return __e1000_write_kmrn_reg(hw, offset, data, true);
955 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
956 * @hw: pointer to the HW structure
958 * Sets up Master/slave mode
960 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
965 /* Resolve Master/Slave mode */
966 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
970 /* load defaults for future use */
971 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
972 ((phy_data & CR_1000T_MS_VALUE) ?
973 e1000_ms_force_master :
974 e1000_ms_force_slave) : e1000_ms_auto;
976 switch (hw->phy.ms_type) {
977 case e1000_ms_force_master:
978 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
980 case e1000_ms_force_slave:
981 phy_data |= CR_1000T_MS_ENABLE;
982 phy_data &= ~(CR_1000T_MS_VALUE);
985 phy_data &= ~CR_1000T_MS_ENABLE;
991 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
995 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
996 * @hw: pointer to the HW structure
998 * Sets up Carrier-sense on Transmit and downshift values.
1000 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1005 DEBUGFUNC("e1000_copper_link_setup_82577");
1007 if (hw->phy.reset_disable)
1008 return E1000_SUCCESS;
1010 if (hw->phy.type == e1000_phy_82580) {
1011 ret_val = hw->phy.ops.reset(hw);
1013 DEBUGOUT("Error resetting the PHY.\n");
1018 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1019 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1023 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1025 /* Enable downshift */
1026 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1028 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1032 /* Set MDI/MDIX mode */
1033 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1036 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
1038 * 0 - Auto (default)
1042 switch (hw->phy.mdix) {
1046 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
1050 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
1053 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1057 return e1000_set_master_slave_mode(hw);
1061 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1062 * @hw: pointer to the HW structure
1064 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1065 * and downshift values are set also.
1067 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1069 struct e1000_phy_info *phy = &hw->phy;
1073 DEBUGFUNC("e1000_copper_link_setup_m88");
1075 if (phy->reset_disable)
1076 return E1000_SUCCESS;
1078 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1079 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1083 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1086 * MDI/MDI-X = 0 (default)
1087 * 0 - Auto for all speeds
1090 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1092 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1094 switch (phy->mdix) {
1096 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1099 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1102 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1106 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1111 * disable_polarity_correction = 0 (default)
1112 * Automatic Correction for Reversed Cable Polarity
1116 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1117 if (phy->disable_polarity_correction)
1118 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1120 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1124 if (phy->revision < E1000_REVISION_4) {
1125 /* Force TX_CLK in the Extended PHY Specific Control Register
1128 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1133 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1135 if ((phy->revision == E1000_REVISION_2) &&
1136 (phy->id == M88E1111_I_PHY_ID)) {
1137 /* 82573L PHY - set the downshift counter to 5x. */
1138 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1139 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1141 /* Configure Master and Slave downshift values */
1142 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1143 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1144 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1145 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1147 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1153 /* Commit the changes. */
1154 ret_val = phy->ops.commit(hw);
1156 DEBUGOUT("Error committing the PHY changes\n");
1160 return E1000_SUCCESS;
1164 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1165 * @hw: pointer to the HW structure
1167 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1168 * Also enables and sets the downshift parameters.
1170 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1172 struct e1000_phy_info *phy = &hw->phy;
1176 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1178 if (phy->reset_disable)
1179 return E1000_SUCCESS;
1181 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1182 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1187 * MDI/MDI-X = 0 (default)
1188 * 0 - Auto for all speeds
1191 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1193 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1195 switch (phy->mdix) {
1197 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1200 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1203 /* M88E1112 does not support this mode) */
1204 if (phy->id != M88E1112_E_PHY_ID) {
1205 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1210 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1215 * disable_polarity_correction = 0 (default)
1216 * Automatic Correction for Reversed Cable Polarity
1220 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1221 if (phy->disable_polarity_correction)
1222 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1224 /* Enable downshift and setting it to X6 */
1225 if (phy->id == M88E1543_E_PHY_ID) {
1226 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
1228 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1232 ret_val = phy->ops.commit(hw);
1234 DEBUGOUT("Error committing the PHY changes\n");
1239 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1240 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1241 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1243 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1247 /* Commit the changes. */
1248 ret_val = phy->ops.commit(hw);
1250 DEBUGOUT("Error committing the PHY changes\n");
1254 ret_val = e1000_set_master_slave_mode(hw);
1258 return E1000_SUCCESS;
1262 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1263 * @hw: pointer to the HW structure
1265 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1268 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1270 struct e1000_phy_info *phy = &hw->phy;
1274 DEBUGFUNC("e1000_copper_link_setup_igp");
1276 if (phy->reset_disable)
1277 return E1000_SUCCESS;
1279 ret_val = hw->phy.ops.reset(hw);
1281 DEBUGOUT("Error resetting the PHY.\n");
1285 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1286 * timeout issues when LFS is enabled.
1290 /* disable lplu d0 during driver init */
1291 if (hw->phy.ops.set_d0_lplu_state) {
1292 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1294 DEBUGOUT("Error Disabling LPLU D0\n");
1298 /* Configure mdi-mdix settings */
1299 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1303 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1305 switch (phy->mdix) {
1307 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1310 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1314 data |= IGP01E1000_PSCR_AUTO_MDIX;
1317 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1321 /* set auto-master slave resolution settings */
1322 if (hw->mac.autoneg) {
1323 /* when autonegotiation advertisement is only 1000Mbps then we
1324 * should disable SmartSpeed and enable Auto MasterSlave
1325 * resolution as hardware default.
1327 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1328 /* Disable SmartSpeed */
1329 ret_val = phy->ops.read_reg(hw,
1330 IGP01E1000_PHY_PORT_CONFIG,
1335 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1336 ret_val = phy->ops.write_reg(hw,
1337 IGP01E1000_PHY_PORT_CONFIG,
1342 /* Set auto Master/Slave resolution process */
1343 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1347 data &= ~CR_1000T_MS_ENABLE;
1348 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1353 ret_val = e1000_set_master_slave_mode(hw);
1360 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1361 * @hw: pointer to the HW structure
1363 * Reads the MII auto-neg advertisement register and/or the 1000T control
1364 * register and if the PHY is already setup for auto-negotiation, then
1365 * return successful. Otherwise, setup advertisement and flow control to
1366 * the appropriate values for the wanted auto-negotiation.
1368 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1370 struct e1000_phy_info *phy = &hw->phy;
1372 u16 mii_autoneg_adv_reg;
1373 u16 mii_1000t_ctrl_reg = 0;
1375 DEBUGFUNC("e1000_phy_setup_autoneg");
1377 phy->autoneg_advertised &= phy->autoneg_mask;
1379 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1380 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1384 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1385 /* Read the MII 1000Base-T Control Register (Address 9). */
1386 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1387 &mii_1000t_ctrl_reg);
1392 /* Need to parse both autoneg_advertised and fc and set up
1393 * the appropriate PHY registers. First we will parse for
1394 * autoneg_advertised software override. Since we can advertise
1395 * a plethora of combinations, we need to check each bit
1399 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1400 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1401 * the 1000Base-T Control Register (Address 9).
1403 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1404 NWAY_AR_100TX_HD_CAPS |
1405 NWAY_AR_10T_FD_CAPS |
1406 NWAY_AR_10T_HD_CAPS);
1407 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1409 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1411 /* Do we want to advertise 10 Mb Half Duplex? */
1412 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1413 DEBUGOUT("Advertise 10mb Half duplex\n");
1414 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1417 /* Do we want to advertise 10 Mb Full Duplex? */
1418 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1419 DEBUGOUT("Advertise 10mb Full duplex\n");
1420 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1423 /* Do we want to advertise 100 Mb Half Duplex? */
1424 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1425 DEBUGOUT("Advertise 100mb Half duplex\n");
1426 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1429 /* Do we want to advertise 100 Mb Full Duplex? */
1430 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1431 DEBUGOUT("Advertise 100mb Full duplex\n");
1432 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1435 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1436 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1437 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1439 /* Do we want to advertise 1000 Mb Full Duplex? */
1440 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1441 DEBUGOUT("Advertise 1000mb Full duplex\n");
1442 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1445 /* Check for a software override of the flow control settings, and
1446 * setup the PHY advertisement registers accordingly. If
1447 * auto-negotiation is enabled, then software will have to set the
1448 * "PAUSE" bits to the correct value in the Auto-Negotiation
1449 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1452 * The possible values of the "fc" parameter are:
1453 * 0: Flow control is completely disabled
1454 * 1: Rx flow control is enabled (we can receive pause frames
1455 * but not send pause frames).
1456 * 2: Tx flow control is enabled (we can send pause frames
1457 * but we do not support receiving pause frames).
1458 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1459 * other: No software override. The flow control configuration
1460 * in the EEPROM is used.
1462 switch (hw->fc.current_mode) {
1464 /* Flow control (Rx & Tx) is completely disabled by a
1465 * software over-ride.
1467 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1469 case e1000_fc_rx_pause:
1470 /* Rx Flow control is enabled, and Tx Flow control is
1471 * disabled, by a software over-ride.
1473 * Since there really isn't a way to advertise that we are
1474 * capable of Rx Pause ONLY, we will advertise that we
1475 * support both symmetric and asymmetric Rx PAUSE. Later
1476 * (in e1000_config_fc_after_link_up) we will disable the
1477 * hw's ability to send PAUSE frames.
1479 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1481 case e1000_fc_tx_pause:
1482 /* Tx Flow control is enabled, and Rx Flow control is
1483 * disabled, by a software over-ride.
1485 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1486 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1489 /* Flow control (both Rx and Tx) is enabled by a software
1492 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1495 DEBUGOUT("Flow control param set incorrectly\n");
1496 return -E1000_ERR_CONFIG;
1499 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1503 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1505 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1506 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1507 mii_1000t_ctrl_reg);
1513 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1514 * @hw: pointer to the HW structure
1516 * Performs initial bounds checking on autoneg advertisement parameter, then
1517 * configure to advertise the full capability. Setup the PHY to autoneg
1518 * and restart the negotiation process between the link partner. If
1519 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1521 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1523 struct e1000_phy_info *phy = &hw->phy;
1527 DEBUGFUNC("e1000_copper_link_autoneg");
1529 /* Perform some bounds checking on the autoneg advertisement
1532 phy->autoneg_advertised &= phy->autoneg_mask;
1534 /* If autoneg_advertised is zero, we assume it was not defaulted
1535 * by the calling code so we set to advertise full capability.
1537 if (!phy->autoneg_advertised)
1538 phy->autoneg_advertised = phy->autoneg_mask;
1540 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1541 ret_val = e1000_phy_setup_autoneg(hw);
1543 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1546 DEBUGOUT("Restarting Auto-Neg\n");
1548 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1549 * the Auto Neg Restart bit in the PHY control register.
1551 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1555 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1556 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1560 /* Does the user want to wait for Auto-Neg to complete here, or
1561 * check at a later time (for example, callback routine).
1563 if (phy->autoneg_wait_to_complete) {
1564 ret_val = e1000_wait_autoneg(hw);
1566 DEBUGOUT("Error while waiting for autoneg to complete\n");
1571 hw->mac.get_link_status = true;
1577 * e1000_setup_copper_link_generic - Configure copper link settings
1578 * @hw: pointer to the HW structure
1580 * Calls the appropriate function to configure the link for auto-neg or forced
1581 * speed and duplex. Then we check for link, once link is established calls
1582 * to configure collision distance and flow control are called. If link is
1583 * not established, we return -E1000_ERR_PHY (-2).
1585 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1590 DEBUGFUNC("e1000_setup_copper_link_generic");
1592 if (hw->mac.autoneg) {
1593 /* Setup autoneg and flow control advertisement and perform
1596 ret_val = e1000_copper_link_autoneg(hw);
1600 /* PHY will be set to 10H, 10F, 100H or 100F
1601 * depending on user settings.
1603 DEBUGOUT("Forcing Speed and Duplex\n");
1604 ret_val = hw->phy.ops.force_speed_duplex(hw);
1606 DEBUGOUT("Error Forcing Speed and Duplex\n");
1611 /* Check link status. Wait up to 100 microseconds for link to become
1614 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1620 DEBUGOUT("Valid link established!!!\n");
1621 hw->mac.ops.config_collision_dist(hw);
1622 ret_val = e1000_config_fc_after_link_up_generic(hw);
1624 DEBUGOUT("Unable to establish link!!!\n");
1631 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1632 * @hw: pointer to the HW structure
1634 * Calls the PHY setup function to force speed and duplex. Clears the
1635 * auto-crossover to force MDI manually. Waits for link and returns
1636 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1638 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1640 struct e1000_phy_info *phy = &hw->phy;
1645 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1647 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1651 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1653 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1657 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1658 * forced whenever speed and duplex are forced.
1660 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1664 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1665 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1667 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1671 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1675 if (phy->autoneg_wait_to_complete) {
1676 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1678 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1684 DEBUGOUT("Link taking longer than expected.\n");
1687 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1695 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1696 * @hw: pointer to the HW structure
1698 * Calls the PHY setup function to force speed and duplex. Clears the
1699 * auto-crossover to force MDI manually. Resets the PHY to commit the
1700 * changes. If time expires while waiting for link up, we reset the DSP.
1701 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1702 * successful completion, else return corresponding error code.
1704 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1706 struct e1000_phy_info *phy = &hw->phy;
1711 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1713 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1714 if (phy->type != e1000_phy_i210) {
1715 /* Clear Auto-Crossover to force MDI manually. M88E1000
1716 * requires MDI forced whenever speed and duplex are forced.
1718 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1723 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1724 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1730 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1732 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1736 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1738 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1742 /* Reset the phy to commit changes. */
1743 ret_val = hw->phy.ops.commit(hw);
1747 if (phy->autoneg_wait_to_complete) {
1748 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1750 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1756 bool reset_dsp = true;
1758 switch (hw->phy.id) {
1759 case I347AT4_E_PHY_ID:
1760 case M88E1340M_E_PHY_ID:
1761 case M88E1112_E_PHY_ID:
1762 case M88E1543_E_PHY_ID:
1767 if (hw->phy.type != e1000_phy_m88)
1773 DEBUGOUT("Link taking longer than expected.\n");
1775 /* We didn't get link.
1776 * Reset the DSP and cross our fingers.
1778 ret_val = phy->ops.write_reg(hw,
1779 M88E1000_PHY_PAGE_SELECT,
1783 ret_val = e1000_phy_reset_dsp_generic(hw);
1790 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1796 if (hw->phy.type != e1000_phy_m88)
1797 return E1000_SUCCESS;
1799 if (hw->phy.id == I347AT4_E_PHY_ID ||
1800 hw->phy.id == M88E1340M_E_PHY_ID ||
1801 hw->phy.id == M88E1112_E_PHY_ID)
1802 return E1000_SUCCESS;
1803 if (hw->phy.id == I210_I_PHY_ID)
1804 return E1000_SUCCESS;
1805 if ((hw->phy.id == M88E1543_E_PHY_ID))
1806 return E1000_SUCCESS;
1807 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1811 /* Resetting the phy means we need to re-force TX_CLK in the
1812 * Extended PHY Specific Control Register to 25MHz clock from
1813 * the reset value of 2.5MHz.
1815 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1816 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1820 /* In addition, we must re-enable CRS on Tx for both half and full
1823 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1827 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1828 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1834 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1835 * @hw: pointer to the HW structure
1837 * Forces the speed and duplex settings of the PHY.
1838 * This is a function pointer entry point only called by
1839 * PHY setup routines.
1841 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1843 struct e1000_phy_info *phy = &hw->phy;
1848 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1850 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1854 e1000_phy_force_speed_duplex_setup(hw, &data);
1856 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1860 /* Disable MDI-X support for 10/100 */
1861 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1865 data &= ~IFE_PMC_AUTO_MDIX;
1866 data &= ~IFE_PMC_FORCE_MDIX;
1868 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1872 DEBUGOUT1("IFE PMC: %X\n", data);
1876 if (phy->autoneg_wait_to_complete) {
1877 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1879 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1885 DEBUGOUT("Link taking longer than expected.\n");
1888 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1894 return E1000_SUCCESS;
1898 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1899 * @hw: pointer to the HW structure
1900 * @phy_ctrl: pointer to current value of PHY_CONTROL
1902 * Forces speed and duplex on the PHY by doing the following: disable flow
1903 * control, force speed/duplex on the MAC, disable auto speed detection,
1904 * disable auto-negotiation, configure duplex, configure speed, configure
1905 * the collision distance, write configuration to CTRL register. The
1906 * caller must write to the PHY_CONTROL register for these settings to
1909 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1911 struct e1000_mac_info *mac = &hw->mac;
1914 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1916 /* Turn off flow control when forcing speed/duplex */
1917 hw->fc.current_mode = e1000_fc_none;
1919 /* Force speed/duplex on the mac */
1920 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1921 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1922 ctrl &= ~E1000_CTRL_SPD_SEL;
1924 /* Disable Auto Speed Detection */
1925 ctrl &= ~E1000_CTRL_ASDE;
1927 /* Disable autoneg on the phy */
1928 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1930 /* Forcing Full or Half Duplex? */
1931 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1932 ctrl &= ~E1000_CTRL_FD;
1933 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1934 DEBUGOUT("Half Duplex\n");
1936 ctrl |= E1000_CTRL_FD;
1937 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1938 DEBUGOUT("Full Duplex\n");
1941 /* Forcing 10mb or 100mb? */
1942 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1943 ctrl |= E1000_CTRL_SPD_100;
1944 *phy_ctrl |= MII_CR_SPEED_100;
1945 *phy_ctrl &= ~MII_CR_SPEED_1000;
1946 DEBUGOUT("Forcing 100mb\n");
1948 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1949 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1950 DEBUGOUT("Forcing 10mb\n");
1953 hw->mac.ops.config_collision_dist(hw);
1955 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1959 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
1960 * @hw: pointer to the HW structure
1961 * @active: boolean used to enable/disable lplu
1963 * Success returns 0, Failure returns 1
1965 * The low power link up (lplu) state is set to the power management level D3
1966 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1967 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1968 * is used during Dx states where the power conservation is most important.
1969 * During driver activity, SmartSpeed should be enabled so performance is
1972 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
1974 struct e1000_phy_info *phy = &hw->phy;
1978 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
1980 if (!hw->phy.ops.read_reg)
1981 return E1000_SUCCESS;
1983 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1988 data &= ~IGP02E1000_PM_D3_LPLU;
1989 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1993 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1994 * during Dx states where the power conservation is most
1995 * important. During driver activity we should enable
1996 * SmartSpeed, so performance is maintained.
1998 if (phy->smart_speed == e1000_smart_speed_on) {
1999 ret_val = phy->ops.read_reg(hw,
2000 IGP01E1000_PHY_PORT_CONFIG,
2005 data |= IGP01E1000_PSCFR_SMART_SPEED;
2006 ret_val = phy->ops.write_reg(hw,
2007 IGP01E1000_PHY_PORT_CONFIG,
2011 } else if (phy->smart_speed == e1000_smart_speed_off) {
2012 ret_val = phy->ops.read_reg(hw,
2013 IGP01E1000_PHY_PORT_CONFIG,
2018 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2019 ret_val = phy->ops.write_reg(hw,
2020 IGP01E1000_PHY_PORT_CONFIG,
2025 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2026 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2027 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2028 data |= IGP02E1000_PM_D3_LPLU;
2029 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2034 /* When LPLU is enabled, we should disable SmartSpeed */
2035 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2040 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2041 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2049 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2050 * @hw: pointer to the HW structure
2052 * Success returns 0, Failure returns 1
2054 * A downshift is detected by querying the PHY link health.
2056 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2058 struct e1000_phy_info *phy = &hw->phy;
2060 u16 phy_data, offset, mask;
2062 DEBUGFUNC("e1000_check_downshift_generic");
2064 switch (phy->type) {
2065 case e1000_phy_i210:
2067 case e1000_phy_gg82563:
2068 offset = M88E1000_PHY_SPEC_STATUS;
2069 mask = M88E1000_PSSR_DOWNSHIFT;
2071 case e1000_phy_igp_2:
2072 case e1000_phy_igp_3:
2073 offset = IGP01E1000_PHY_LINK_HEALTH;
2074 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2077 /* speed downshift not supported */
2078 phy->speed_downgraded = false;
2079 return E1000_SUCCESS;
2082 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2085 phy->speed_downgraded = !!(phy_data & mask);
2091 * e1000_check_polarity_m88 - Checks the polarity.
2092 * @hw: pointer to the HW structure
2094 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2096 * Polarity is determined based on the PHY specific status register.
2098 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2100 struct e1000_phy_info *phy = &hw->phy;
2104 DEBUGFUNC("e1000_check_polarity_m88");
2106 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2109 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
2110 ? e1000_rev_polarity_reversed
2111 : e1000_rev_polarity_normal);
2117 * e1000_check_polarity_igp - Checks the polarity.
2118 * @hw: pointer to the HW structure
2120 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2122 * Polarity is determined based on the PHY port status register, and the
2123 * current speed (since there is no polarity at 100Mbps).
2125 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2127 struct e1000_phy_info *phy = &hw->phy;
2129 u16 data, offset, mask;
2131 DEBUGFUNC("e1000_check_polarity_igp");
2133 /* Polarity is determined based on the speed of
2136 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2140 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2141 IGP01E1000_PSSR_SPEED_1000MBPS) {
2142 offset = IGP01E1000_PHY_PCS_INIT_REG;
2143 mask = IGP01E1000_PHY_POLARITY_MASK;
2145 /* This really only applies to 10Mbps since
2146 * there is no polarity for 100Mbps (always 0).
2148 offset = IGP01E1000_PHY_PORT_STATUS;
2149 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2152 ret_val = phy->ops.read_reg(hw, offset, &data);
2155 phy->cable_polarity = ((data & mask)
2156 ? e1000_rev_polarity_reversed
2157 : e1000_rev_polarity_normal);
2163 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2164 * @hw: pointer to the HW structure
2166 * Polarity is determined on the polarity reversal feature being enabled.
2168 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2170 struct e1000_phy_info *phy = &hw->phy;
2172 u16 phy_data, offset, mask;
2174 DEBUGFUNC("e1000_check_polarity_ife");
2176 /* Polarity is determined based on the reversal feature being enabled.
2178 if (phy->polarity_correction) {
2179 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2180 mask = IFE_PESC_POLARITY_REVERSED;
2182 offset = IFE_PHY_SPECIAL_CONTROL;
2183 mask = IFE_PSC_FORCE_POLARITY;
2186 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2189 phy->cable_polarity = ((phy_data & mask)
2190 ? e1000_rev_polarity_reversed
2191 : e1000_rev_polarity_normal);
2197 * e1000_wait_autoneg - Wait for auto-neg completion
2198 * @hw: pointer to the HW structure
2200 * Waits for auto-negotiation to complete or for the auto-negotiation time
2201 * limit to expire, which ever happens first.
2203 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2205 s32 ret_val = E1000_SUCCESS;
2208 DEBUGFUNC("e1000_wait_autoneg");
2210 if (!hw->phy.ops.read_reg)
2211 return E1000_SUCCESS;
2213 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2214 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2215 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2218 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2221 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2226 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2233 * e1000_phy_has_link_generic - Polls PHY for link
2234 * @hw: pointer to the HW structure
2235 * @iterations: number of times to poll for link
2236 * @usec_interval: delay between polling attempts
2237 * @success: pointer to whether polling was successful or not
2239 * Polls the PHY status register for link, 'iterations' number of times.
2241 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2242 u32 usec_interval, bool *success)
2244 s32 ret_val = E1000_SUCCESS;
2247 DEBUGFUNC("e1000_phy_has_link_generic");
2249 if (!hw->phy.ops.read_reg)
2250 return E1000_SUCCESS;
2252 for (i = 0; i < iterations; i++) {
2253 /* Some PHYs require the PHY_STATUS register to be read
2254 * twice due to the link bit being sticky. No harm doing
2255 * it across the board.
2257 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2259 /* If the first read fails, another entity may have
2260 * ownership of the resources, wait and try again to
2261 * see if they have relinquished the resources yet.
2263 usec_delay(usec_interval);
2264 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2267 if (phy_status & MII_SR_LINK_STATUS)
2269 if (usec_interval >= 1000)
2270 msec_delay_irq(usec_interval/1000);
2272 usec_delay(usec_interval);
2275 *success = (i < iterations);
2281 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2282 * @hw: pointer to the HW structure
2284 * Reads the PHY specific status register to retrieve the cable length
2285 * information. The cable length is determined by averaging the minimum and
2286 * maximum values to get the "average" cable length. The m88 PHY has four
2287 * possible cable length values, which are:
2288 * Register Value Cable Length
2292 * 3 110 - 140 meters
2295 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2297 struct e1000_phy_info *phy = &hw->phy;
2299 u16 phy_data, index;
2301 DEBUGFUNC("e1000_get_cable_length_m88");
2303 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2307 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2308 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2310 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2311 return -E1000_ERR_PHY;
2313 phy->min_cable_length = e1000_m88_cable_length_table[index];
2314 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2316 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2318 return E1000_SUCCESS;
2321 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2323 struct e1000_phy_info *phy = &hw->phy;
2325 u16 phy_data, phy_data2, is_cm;
2326 u16 index, default_page;
2328 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2330 switch (hw->phy.id) {
2332 /* Get cable length from PHY Cable Diagnostics Control Reg */
2333 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2334 (I347AT4_PCDL + phy->addr),
2339 /* Check if the unit of cable length is meters or cm */
2340 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2341 I347AT4_PCDC, &phy_data2);
2345 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2347 /* Populate the phy structure with cable length in meters */
2348 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2349 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2350 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2352 case M88E1543_E_PHY_ID:
2353 case M88E1340M_E_PHY_ID:
2354 case I347AT4_E_PHY_ID:
2355 /* Remember the original page select and set it to 7 */
2356 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2361 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2365 /* Get cable length from PHY Cable Diagnostics Control Reg */
2366 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2371 /* Check if the unit of cable length is meters or cm */
2372 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2376 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2378 /* Populate the phy structure with cable length in meters */
2379 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2380 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2381 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2383 /* Reset the page select to its original value */
2384 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2390 case M88E1112_E_PHY_ID:
2391 /* Remember the original page select and set it to 5 */
2392 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2397 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2401 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2406 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2407 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2409 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2410 return -E1000_ERR_PHY;
2412 phy->min_cable_length = e1000_m88_cable_length_table[index];
2413 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2415 phy->cable_length = (phy->min_cable_length +
2416 phy->max_cable_length) / 2;
2418 /* Reset the page select to its original value */
2419 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2426 return -E1000_ERR_PHY;
2433 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2434 * @hw: pointer to the HW structure
2436 * The automatic gain control (agc) normalizes the amplitude of the
2437 * received signal, adjusting for the attenuation produced by the
2438 * cable. By reading the AGC registers, which represent the
2439 * combination of coarse and fine gain value, the value can be put
2440 * into a lookup table to obtain the approximate cable length
2443 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2445 struct e1000_phy_info *phy = &hw->phy;
2447 u16 phy_data, i, agc_value = 0;
2448 u16 cur_agc_index, max_agc_index = 0;
2449 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2450 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2451 IGP02E1000_PHY_AGC_A,
2452 IGP02E1000_PHY_AGC_B,
2453 IGP02E1000_PHY_AGC_C,
2454 IGP02E1000_PHY_AGC_D
2457 DEBUGFUNC("e1000_get_cable_length_igp_2");
2459 /* Read the AGC registers for all channels */
2460 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2461 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2465 /* Getting bits 15:9, which represent the combination of
2466 * coarse and fine gain values. The result is a number
2467 * that can be put into the lookup table to obtain the
2468 * approximate cable length.
2470 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2471 IGP02E1000_AGC_LENGTH_MASK);
2473 /* Array index bound check. */
2474 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2475 (cur_agc_index == 0))
2476 return -E1000_ERR_PHY;
2478 /* Remove min & max AGC values from calculation. */
2479 if (e1000_igp_2_cable_length_table[min_agc_index] >
2480 e1000_igp_2_cable_length_table[cur_agc_index])
2481 min_agc_index = cur_agc_index;
2482 if (e1000_igp_2_cable_length_table[max_agc_index] <
2483 e1000_igp_2_cable_length_table[cur_agc_index])
2484 max_agc_index = cur_agc_index;
2486 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2489 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2490 e1000_igp_2_cable_length_table[max_agc_index]);
2491 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2493 /* Calculate cable length with the error range of +/- 10 meters. */
2494 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2495 (agc_value - IGP02E1000_AGC_RANGE) : 0);
2496 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2498 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2500 return E1000_SUCCESS;
2504 * e1000_get_phy_info_m88 - Retrieve PHY information
2505 * @hw: pointer to the HW structure
2507 * Valid for only copper links. Read the PHY status register (sticky read)
2508 * to verify that link is up. Read the PHY special control register to
2509 * determine the polarity and 10base-T extended distance. Read the PHY
2510 * special status register to determine MDI/MDIx and current speed. If
2511 * speed is 1000, then determine cable length, local and remote receiver.
2513 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2515 struct e1000_phy_info *phy = &hw->phy;
2520 DEBUGFUNC("e1000_get_phy_info_m88");
2522 if (phy->media_type != e1000_media_type_copper) {
2523 DEBUGOUT("Phy info is only valid for copper media\n");
2524 return -E1000_ERR_CONFIG;
2527 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2532 DEBUGOUT("Phy info is only valid if link is up\n");
2533 return -E1000_ERR_CONFIG;
2536 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2540 phy->polarity_correction = !!(phy_data &
2541 M88E1000_PSCR_POLARITY_REVERSAL);
2543 ret_val = e1000_check_polarity_m88(hw);
2547 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2551 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2553 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2554 ret_val = hw->phy.ops.get_cable_length(hw);
2558 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2562 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2563 ? e1000_1000t_rx_status_ok
2564 : e1000_1000t_rx_status_not_ok;
2566 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2567 ? e1000_1000t_rx_status_ok
2568 : e1000_1000t_rx_status_not_ok;
2570 /* Set values to "undefined" */
2571 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2572 phy->local_rx = e1000_1000t_rx_status_undefined;
2573 phy->remote_rx = e1000_1000t_rx_status_undefined;
2580 * e1000_get_phy_info_igp - Retrieve igp PHY information
2581 * @hw: pointer to the HW structure
2583 * Read PHY status to determine if link is up. If link is up, then
2584 * set/determine 10base-T extended distance and polarity correction. Read
2585 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2586 * determine on the cable length, local and remote receiver.
2588 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2590 struct e1000_phy_info *phy = &hw->phy;
2595 DEBUGFUNC("e1000_get_phy_info_igp");
2597 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2602 DEBUGOUT("Phy info is only valid if link is up\n");
2603 return -E1000_ERR_CONFIG;
2606 phy->polarity_correction = true;
2608 ret_val = e1000_check_polarity_igp(hw);
2612 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2616 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2618 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2619 IGP01E1000_PSSR_SPEED_1000MBPS) {
2620 ret_val = phy->ops.get_cable_length(hw);
2624 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2628 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2629 ? e1000_1000t_rx_status_ok
2630 : e1000_1000t_rx_status_not_ok;
2632 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2633 ? e1000_1000t_rx_status_ok
2634 : e1000_1000t_rx_status_not_ok;
2636 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2637 phy->local_rx = e1000_1000t_rx_status_undefined;
2638 phy->remote_rx = e1000_1000t_rx_status_undefined;
2645 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2646 * @hw: pointer to the HW structure
2648 * Populates "phy" structure with various feature states.
2650 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2652 struct e1000_phy_info *phy = &hw->phy;
2657 DEBUGFUNC("e1000_get_phy_info_ife");
2659 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2664 DEBUGOUT("Phy info is only valid if link is up\n");
2665 return -E1000_ERR_CONFIG;
2668 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2671 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2673 if (phy->polarity_correction) {
2674 ret_val = e1000_check_polarity_ife(hw);
2678 /* Polarity is forced */
2679 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2680 ? e1000_rev_polarity_reversed
2681 : e1000_rev_polarity_normal);
2684 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2688 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2690 /* The following parameters are undefined for 10/100 operation. */
2691 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2692 phy->local_rx = e1000_1000t_rx_status_undefined;
2693 phy->remote_rx = e1000_1000t_rx_status_undefined;
2695 return E1000_SUCCESS;
2699 * e1000_phy_sw_reset_generic - PHY software reset
2700 * @hw: pointer to the HW structure
2702 * Does a software reset of the PHY by reading the PHY control register and
2703 * setting/write the control register reset bit to the PHY.
2705 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2710 DEBUGFUNC("e1000_phy_sw_reset_generic");
2712 if (!hw->phy.ops.read_reg)
2713 return E1000_SUCCESS;
2715 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2719 phy_ctrl |= MII_CR_RESET;
2720 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2730 * e1000_phy_hw_reset_generic - PHY hardware reset
2731 * @hw: pointer to the HW structure
2733 * Verify the reset block is not blocking us from resetting. Acquire
2734 * semaphore (if necessary) and read/set/write the device control reset
2735 * bit in the PHY. Wait the appropriate delay time for the device to
2736 * reset and release the semaphore (if necessary).
2738 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2740 struct e1000_phy_info *phy = &hw->phy;
2744 DEBUGFUNC("e1000_phy_hw_reset_generic");
2746 if (phy->ops.check_reset_block) {
2747 ret_val = phy->ops.check_reset_block(hw);
2749 return E1000_SUCCESS;
2752 ret_val = phy->ops.acquire(hw);
2756 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2757 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2758 E1000_WRITE_FLUSH(hw);
2760 usec_delay(phy->reset_delay_us);
2762 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2763 E1000_WRITE_FLUSH(hw);
2767 phy->ops.release(hw);
2769 return phy->ops.get_cfg_done(hw);
2773 * e1000_get_cfg_done_generic - Generic configuration done
2774 * @hw: pointer to the HW structure
2776 * Generic function to wait 10 milli-seconds for configuration to complete
2777 * and return success.
2779 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2781 DEBUGFUNC("e1000_get_cfg_done_generic");
2785 return E1000_SUCCESS;
2789 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2790 * @hw: pointer to the HW structure
2792 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2794 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2796 DEBUGOUT("Running IGP 3 PHY init script\n");
2798 /* PHY init IGP 3 */
2799 /* Enable rise/fall, 10-mode work in class-A */
2800 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2801 /* Remove all caps from Replica path filter */
2802 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2803 /* Bias trimming for ADC, AFE and Driver (Default) */
2804 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2805 /* Increase Hybrid poly bias */
2806 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2807 /* Add 4% to Tx amplitude in Gig mode */
2808 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2809 /* Disable trimming (TTT) */
2810 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2811 /* Poly DC correction to 94.6% + 2% for all channels */
2812 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2813 /* ABS DC correction to 95.9% */
2814 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2815 /* BG temp curve trim */
2816 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2817 /* Increasing ADC OPAMP stage 1 currents to max */
2818 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2819 /* Force 1000 ( required for enabling PHY regs configuration) */
2820 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2821 /* Set upd_freq to 6 */
2822 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2824 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2825 /* Disable adaptive fixed FFE (Default) */
2826 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2827 /* Enable FFE hysteresis */
2828 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2829 /* Fixed FFE for short cable lengths */
2830 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2831 /* Fixed FFE for medium cable lengths */
2832 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2833 /* Fixed FFE for long cable lengths */
2834 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2835 /* Enable Adaptive Clip Threshold */
2836 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2837 /* AHT reset limit to 1 */
2838 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2839 /* Set AHT master delay to 127 msec */
2840 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2841 /* Set scan bits for AHT */
2842 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2843 /* Set AHT Preset bits */
2844 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2845 /* Change integ_factor of channel A to 3 */
2846 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2847 /* Change prop_factor of channels BCD to 8 */
2848 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2849 /* Change cg_icount + enable integbp for channels BCD */
2850 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2851 /* Change cg_icount + enable integbp + change prop_factor_master
2852 * to 8 for channel A
2854 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2855 /* Disable AHT in Slave mode on channel A */
2856 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2857 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2860 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2861 /* Enable restart AN on an1000_dis change */
2862 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2863 /* Enable wh_fifo read clock in 10/100 modes */
2864 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2865 /* Restart AN, Speed selection is 1000 */
2866 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2868 return E1000_SUCCESS;
2872 * e1000_get_phy_type_from_id - Get PHY type from id
2873 * @phy_id: phy_id read from the phy
2875 * Returns the phy type from the id.
2877 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2879 enum e1000_phy_type phy_type = e1000_phy_unknown;
2882 case M88E1000_I_PHY_ID:
2883 case M88E1000_E_PHY_ID:
2884 case M88E1111_I_PHY_ID:
2885 case M88E1011_I_PHY_ID:
2886 case M88E1543_E_PHY_ID:
2887 case I347AT4_E_PHY_ID:
2888 case M88E1112_E_PHY_ID:
2889 case M88E1340M_E_PHY_ID:
2890 phy_type = e1000_phy_m88;
2892 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2893 phy_type = e1000_phy_igp_2;
2895 case GG82563_E_PHY_ID:
2896 phy_type = e1000_phy_gg82563;
2898 case IGP03E1000_E_PHY_ID:
2899 phy_type = e1000_phy_igp_3;
2902 case IFE_PLUS_E_PHY_ID:
2903 case IFE_C_E_PHY_ID:
2904 phy_type = e1000_phy_ife;
2906 case I82580_I_PHY_ID:
2907 phy_type = e1000_phy_82580;
2910 phy_type = e1000_phy_i210;
2913 phy_type = e1000_phy_unknown;
2920 * e1000_determine_phy_address - Determines PHY address.
2921 * @hw: pointer to the HW structure
2923 * This uses a trial and error method to loop through possible PHY
2924 * addresses. It tests each by reading the PHY ID registers and
2925 * checking for a match.
2927 s32 e1000_determine_phy_address(struct e1000_hw *hw)
2931 enum e1000_phy_type phy_type = e1000_phy_unknown;
2933 hw->phy.id = phy_type;
2935 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2936 hw->phy.addr = phy_addr;
2940 e1000_get_phy_id(hw);
2941 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
2943 /* If phy_type is valid, break - we found our
2946 if (phy_type != e1000_phy_unknown)
2947 return E1000_SUCCESS;
2954 return -E1000_ERR_PHY_TYPE;
2958 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2959 * @hw: pointer to the HW structure
2961 * In the case of a PHY power down to save power, or to turn off link during a
2962 * driver unload, or wake on lan is not enabled, restore the link to previous
2965 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2970 /* The PHY will retain its settings across a power down/up cycle */
2971 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2972 mii_reg &= ~MII_CR_POWER_DOWN;
2973 if (hw->phy.type == e1000_phy_i210) {
2974 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
2975 power_reg &= ~GS40G_CS_POWER_DOWN;
2976 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
2978 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2982 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2983 * @hw: pointer to the HW structure
2985 * In the case of a PHY power down to save power, or to turn off link during a
2986 * driver unload, or wake on lan is not enabled, restore the link to previous
2989 void e1000_power_down_phy_copper(struct e1000_hw *hw)
2994 /* The PHY will retain its settings across a power down/up cycle */
2995 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2996 mii_reg |= MII_CR_POWER_DOWN;
2997 /* i210 Phy requires an additional bit for power up/down */
2998 if (hw->phy.type == e1000_phy_i210) {
2999 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
3000 power_reg |= GS40G_CS_POWER_DOWN;
3001 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
3003 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3008 * e1000_check_polarity_82577 - Checks the polarity.
3009 * @hw: pointer to the HW structure
3011 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3013 * Polarity is determined based on the PHY specific status register.
3015 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3017 struct e1000_phy_info *phy = &hw->phy;
3021 DEBUGFUNC("e1000_check_polarity_82577");
3023 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3026 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3027 ? e1000_rev_polarity_reversed
3028 : e1000_rev_polarity_normal);
3034 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3035 * @hw: pointer to the HW structure
3037 * Calls the PHY setup function to force speed and duplex.
3039 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3041 struct e1000_phy_info *phy = &hw->phy;
3046 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3048 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3052 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3054 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3060 if (phy->autoneg_wait_to_complete) {
3061 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3063 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3069 DEBUGOUT("Link taking longer than expected.\n");
3072 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3080 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3081 * @hw: pointer to the HW structure
3083 * Read PHY status to determine if link is up. If link is up, then
3084 * set/determine 10base-T extended distance and polarity correction. Read
3085 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3086 * determine on the cable length, local and remote receiver.
3088 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3090 struct e1000_phy_info *phy = &hw->phy;
3095 DEBUGFUNC("e1000_get_phy_info_82577");
3097 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3102 DEBUGOUT("Phy info is only valid if link is up\n");
3103 return -E1000_ERR_CONFIG;
3106 phy->polarity_correction = true;
3108 ret_val = e1000_check_polarity_82577(hw);
3112 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3116 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3118 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3119 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3120 ret_val = hw->phy.ops.get_cable_length(hw);
3124 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3128 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3129 ? e1000_1000t_rx_status_ok
3130 : e1000_1000t_rx_status_not_ok;
3132 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3133 ? e1000_1000t_rx_status_ok
3134 : e1000_1000t_rx_status_not_ok;
3136 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3137 phy->local_rx = e1000_1000t_rx_status_undefined;
3138 phy->remote_rx = e1000_1000t_rx_status_undefined;
3141 return E1000_SUCCESS;
3145 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3146 * @hw: pointer to the HW structure
3148 * Reads the diagnostic status register and verifies result is valid before
3149 * placing it in the phy_cable_length field.
3151 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3153 struct e1000_phy_info *phy = &hw->phy;
3155 u16 phy_data, length;
3157 DEBUGFUNC("e1000_get_cable_length_82577");
3159 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3163 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3164 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
3166 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3167 return -E1000_ERR_PHY;
3169 phy->cable_length = length;
3171 return E1000_SUCCESS;
3175 * e1000_write_phy_reg_gs40g - Write GS40G PHY register
3176 * @hw: pointer to the HW structure
3177 * @offset: register offset to write to
3178 * @data: data to write at register offset
3180 * Acquires semaphore, if necessary, then writes the data to PHY register
3181 * at the offset. Release any acquired semaphores before exiting.
3183 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
3186 u16 page = offset >> GS40G_PAGE_SHIFT;
3188 DEBUGFUNC("e1000_write_phy_reg_gs40g");
3190 offset = offset & GS40G_OFFSET_MASK;
3191 ret_val = hw->phy.ops.acquire(hw);
3195 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
3198 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
3201 hw->phy.ops.release(hw);
3206 * e1000_read_phy_reg_gs40g - Read GS40G PHY register
3207 * @hw: pointer to the HW structure
3208 * @offset: lower half is register offset to read to
3209 * upper half is page to use.
3210 * @data: data to read at register offset
3212 * Acquires semaphore, if necessary, then reads the data in the PHY register
3213 * at the offset. Release any acquired semaphores before exiting.
3215 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
3218 u16 page = offset >> GS40G_PAGE_SHIFT;
3220 DEBUGFUNC("e1000_read_phy_reg_gs40g");
3222 offset = offset & GS40G_OFFSET_MASK;
3223 ret_val = hw->phy.ops.acquire(hw);
3227 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
3230 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
3233 hw->phy.ops.release(hw);
3238 * e1000_read_phy_reg_mphy - Read mPHY control register
3239 * @hw: pointer to the HW structure
3240 * @address: address to be read
3241 * @data: pointer to the read data
3243 * Reads the mPHY control register in the PHY at offset and stores the
3244 * information read to data.
3246 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data)
3249 bool locked = false;
3252 DEBUGFUNC("e1000_read_phy_reg_mphy");
3254 /* Check if mPHY is ready to read/write operations */
3255 ready = e1000_is_mphy_ready(hw);
3257 return -E1000_ERR_PHY;
3259 /* Check if mPHY access is disabled and enable it if so */
3260 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
3261 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
3263 ready = e1000_is_mphy_ready(hw);
3265 return -E1000_ERR_PHY;
3266 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
3267 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
3270 /* Set the address that we want to read */
3271 ready = e1000_is_mphy_ready(hw);
3273 return -E1000_ERR_PHY;
3275 /* We mask address, because we want to use only current lane */
3276 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK &
3277 ~E1000_MPHY_ADDRESS_FNC_OVERRIDE) |
3278 (address & E1000_MPHY_ADDRESS_MASK);
3279 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
3281 /* Read data from the address */
3282 ready = e1000_is_mphy_ready(hw);
3284 return -E1000_ERR_PHY;
3285 *data = E1000_READ_REG(hw, E1000_MPHY_DATA);
3287 /* Disable access to mPHY if it was originally disabled */
3289 ready = e1000_is_mphy_ready(hw);
3291 return -E1000_ERR_PHY;
3292 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
3293 E1000_MPHY_DIS_ACCESS);
3296 return E1000_SUCCESS;
3300 * e1000_write_phy_reg_mphy - Write mPHY control register
3301 * @hw: pointer to the HW structure
3302 * @address: address to write to
3303 * @data: data to write to register at offset
3304 * @line_override: used when we want to use different line than default one
3306 * Writes data to mPHY control register.
3308 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,
3312 bool locked = false;
3315 DEBUGFUNC("e1000_write_phy_reg_mphy");
3317 /* Check if mPHY is ready to read/write operations */
3318 ready = e1000_is_mphy_ready(hw);
3320 return -E1000_ERR_PHY;
3322 /* Check if mPHY access is disabled and enable it if so */
3323 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
3324 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
3326 ready = e1000_is_mphy_ready(hw);
3328 return -E1000_ERR_PHY;
3329 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
3330 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
3333 /* Set the address that we want to read */
3334 ready = e1000_is_mphy_ready(hw);
3336 return -E1000_ERR_PHY;
3338 /* We mask address, because we want to use only current lane */
3340 mphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE;
3342 mphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE;
3343 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) |
3344 (address & E1000_MPHY_ADDRESS_MASK);
3345 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
3347 /* Read data from the address */
3348 ready = e1000_is_mphy_ready(hw);
3350 return -E1000_ERR_PHY;
3351 E1000_WRITE_REG(hw, E1000_MPHY_DATA, data);
3353 /* Disable access to mPHY if it was originally disabled */
3355 ready = e1000_is_mphy_ready(hw);
3357 return -E1000_ERR_PHY;
3358 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
3359 E1000_MPHY_DIS_ACCESS);
3362 return E1000_SUCCESS;
3366 * e1000_is_mphy_ready - Check if mPHY control register is not busy
3367 * @hw: pointer to the HW structure
3369 * Returns mPHY control register status.
3371 bool e1000_is_mphy_ready(struct e1000_hw *hw)
3373 u16 retry_count = 0;
3377 while (retry_count < 2) {
3378 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
3379 if (mphy_ctrl & E1000_MPHY_BUSY) {
3389 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n");