1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001 - 2015 Intel Corporation
8 void e1000_init_phy_ops_generic(struct e1000_hw *hw);
9 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data);
10 void e1000_null_phy_generic(struct e1000_hw *hw);
11 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active);
12 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);
13 s32 e1000_null_set_page(struct e1000_hw *hw, u16 data);
14 s32 e1000_read_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,
15 u8 dev_addr, u8 *data);
16 s32 e1000_write_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,
17 u8 dev_addr, u8 data);
18 s32 e1000_check_downshift_generic(struct e1000_hw *hw);
19 s32 e1000_check_polarity_m88(struct e1000_hw *hw);
20 s32 e1000_check_polarity_igp(struct e1000_hw *hw);
21 s32 e1000_check_polarity_ife(struct e1000_hw *hw);
22 s32 e1000_check_reset_block_generic(struct e1000_hw *hw);
23 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
24 s32 e1000_copper_link_autoneg(struct e1000_hw *hw);
25 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw);
26 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw);
27 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw);
28 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw);
29 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw);
30 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
31 s32 e1000_get_cable_length_m88(struct e1000_hw *hw);
32 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw);
33 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw);
34 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw);
35 s32 e1000_get_phy_id(struct e1000_hw *hw);
36 s32 e1000_get_phy_info_igp(struct e1000_hw *hw);
37 s32 e1000_get_phy_info_m88(struct e1000_hw *hw);
38 s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
39 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw);
40 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
41 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw);
42 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw);
43 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
44 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
45 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
46 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
47 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
48 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
49 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
50 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw);
51 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
52 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
53 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
54 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
55 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
56 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
57 u32 usec_interval, bool *success);
58 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw);
59 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);
60 s32 e1000_determine_phy_address(struct e1000_hw *hw);
61 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
62 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
63 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
64 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
65 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
66 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
67 void e1000_power_up_phy_copper(struct e1000_hw *hw);
68 void e1000_power_down_phy_copper(struct e1000_hw *hw);
69 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
70 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
71 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
72 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
73 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
74 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data);
75 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
76 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data);
77 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data);
78 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
79 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data);
80 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data);
81 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
82 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
83 s32 e1000_check_polarity_82577(struct e1000_hw *hw);
84 s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
85 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
86 s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
87 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);
88 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);
89 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data);
90 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,
92 bool e1000_is_mphy_ready(struct e1000_hw *hw);
94 #define E1000_MAX_PHY_ADDR 8
96 /* IGP01E1000 Specific Registers */
97 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
98 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
99 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
100 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
101 #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */
102 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
103 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
104 #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
105 #define IGP_PAGE_SHIFT 5
106 #define PHY_REG_MASK 0x1F
108 /* GS40G - I210 PHY defines */
109 #define GS40G_PAGE_SELECT 0x16
110 #define GS40G_PAGE_SHIFT 16
111 #define GS40G_OFFSET_MASK 0xFFFF
112 #define GS40G_PAGE_2 0x20000
113 #define GS40G_MAC_REG2 0x15
114 #define GS40G_MAC_LB 0x4140
115 #define GS40G_MAC_SPEED_1G 0X0006
116 #define GS40G_COPPER_SPEC 0x0010
118 /* BM/HV Specific Registers */
119 #define BM_PORT_CTRL_PAGE 769
120 #define BM_WUC_PAGE 800
121 #define BM_WUC_ADDRESS_OPCODE 0x11
122 #define BM_WUC_DATA_OPCODE 0x12
123 #define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE
124 #define BM_WUC_ENABLE_REG 17
125 #define BM_WUC_ENABLE_BIT (1 << 2)
126 #define BM_WUC_HOST_WU_BIT (1 << 4)
127 #define BM_WUC_ME_WU_BIT (1 << 5)
129 #define PHY_UPPER_SHIFT 21
130 #define BM_PHY_REG(page, reg) \
131 (((reg) & MAX_PHY_REG_ADDRESS) |\
132 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
133 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
134 #define BM_PHY_REG_PAGE(offset) \
135 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
136 #define BM_PHY_REG_NUM(offset) \
137 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
138 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
139 ~MAX_PHY_REG_ADDRESS)))
141 #define HV_INTC_FC_PAGE_START 768
142 #define I82578_ADDR_REG 29
143 #define I82577_ADDR_REG 16
144 #define I82577_CFG_REG 22
145 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
146 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift */
147 #define I82577_CTRL_REG 23
149 /* 82577 specific PHY registers */
150 #define I82577_PHY_CTRL_2 18
151 #define I82577_PHY_LBK_CTRL 19
152 #define I82577_PHY_STATUS_2 26
153 #define I82577_PHY_DIAG_STATUS 31
155 /* I82577 PHY Status 2 */
156 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400
157 #define I82577_PHY_STATUS2_MDIX 0x0800
158 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300
159 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
161 /* I82577 PHY Control 2 */
162 #define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200
163 #define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400
164 #define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600
166 /* I82577 PHY Diagnostics Status */
167 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC
168 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
170 /* 82580 PHY Power Management */
171 #define E1000_82580_PHY_POWER_MGMT 0xE14
172 #define E1000_82580_PM_SPD 0x0001 /* Smart Power Down */
173 #define E1000_82580_PM_D0_LPLU 0x0002 /* For D0a states */
174 #define E1000_82580_PM_D3_LPLU 0x0004 /* For all other states */
175 #define E1000_82580_PM_GO_LINKD 0x0020 /* Go Link Disconnect */
177 #define E1000_MPHY_DIS_ACCESS 0x80000000 /* disable_access bit */
178 #define E1000_MPHY_ENA_ACCESS 0x40000000 /* enable_access bit */
179 #define E1000_MPHY_BUSY 0x00010000 /* busy bit */
180 #define E1000_MPHY_ADDRESS_FNC_OVERRIDE 0x20000000 /* fnc_override bit */
181 #define E1000_MPHY_ADDRESS_MASK 0x0000FFFF /* address mask */
183 /* BM PHY Copper Specific Control 1 */
184 #define BM_CS_CTRL1 16
186 /* BM PHY Copper Specific Status */
187 #define BM_CS_STATUS 17
188 #define BM_CS_STATUS_LINK_UP 0x0400
189 #define BM_CS_STATUS_RESOLVED 0x0800
190 #define BM_CS_STATUS_SPEED_MASK 0xC000
191 #define BM_CS_STATUS_SPEED_1000 0x8000
193 /* 82577 Mobile Phy Status Register */
194 #define HV_M_STATUS 26
195 #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
196 #define HV_M_STATUS_SPEED_MASK 0x0300
197 #define HV_M_STATUS_SPEED_1000 0x0200
198 #define HV_M_STATUS_SPEED_100 0x0100
199 #define HV_M_STATUS_LINK_UP 0x0040
201 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
202 #define IGP01E1000_PHY_POLARITY_MASK 0x0078
204 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000
205 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
207 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080
209 /* Enable flexible speed on link-up */
210 #define IGP01E1000_GMII_FLEX_SPD 0x0010
211 #define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */
213 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
214 #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
215 #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
217 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
219 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
220 #define IGP01E1000_PSSR_MDIX 0x0800
221 #define IGP01E1000_PSSR_SPEED_MASK 0xC000
222 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
224 #define IGP02E1000_PHY_CHANNEL_NUM 4
225 #define IGP02E1000_PHY_AGC_A 0x11B1
226 #define IGP02E1000_PHY_AGC_B 0x12B1
227 #define IGP02E1000_PHY_AGC_C 0x14B1
228 #define IGP02E1000_PHY_AGC_D 0x18B1
230 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course=15:13, Fine=12:9 */
231 #define IGP02E1000_AGC_LENGTH_MASK 0x7F
232 #define IGP02E1000_AGC_RANGE 15
234 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF
236 #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
237 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
238 #define E1000_KMRNCTRLSTA_REN 0x00200000
239 #define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */
240 #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
241 #define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
242 #define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
243 #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */
244 #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
245 #define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
246 #define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */
247 #define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */
248 #define E1000_KMRNCTRLSTA_K0S_CTRL 0x1E /* Kumeran K0s Control */
249 #define E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT 0
250 #define E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT 4
251 #define E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_MASK \
252 (3 << E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT)
253 #define E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK \
254 (7 << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT)
255 #define E1000_KMRNCTRLSTA_OP_MODES 0x1F /* Kumeran Modes of Operation */
256 #define E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC 0x0002 /* change LSC to CSC */
258 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
259 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */
260 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */
261 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
263 /* IFE PHY Extended Status Control */
264 #define IFE_PESC_POLARITY_REVERSED 0x0100
266 /* IFE PHY Special Control */
267 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
268 #define IFE_PSC_FORCE_POLARITY 0x0020
270 /* IFE PHY Special Control and LED Control */
271 #define IFE_PSCL_PROBE_MODE 0x0020
272 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
273 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
275 /* IFE PHY MDIX Control */
276 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
277 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
278 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */
280 /* SFP modules ID memory locations */
281 #define E1000_SFF_IDENTIFIER_OFFSET 0x00
282 #define E1000_SFF_IDENTIFIER_SFF 0x02
283 #define E1000_SFF_IDENTIFIER_SFP 0x03
285 #define E1000_SFF_ETH_FLAGS_OFFSET 0x06
286 /* Flags for SFP modules compatible with ETH up to 1Gb */
287 struct sfp_e1000_flags {
298 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
299 #define E1000_SFF_VENDOR_OUI_TYCO 0x00407600
300 #define E1000_SFF_VENDOR_OUI_FTL 0x00906500
301 #define E1000_SFF_VENDOR_OUI_AVAGO 0x00176A00
302 #define E1000_SFF_VENDOR_OUI_INTEL 0x001B2100
304 /* EEPROM byte offsets */
305 #define IGB_SFF_8472_SWAP 0x5C
306 #define IGB_SFF_8472_COMP 0x5E
309 #define IGB_SFF_ADDRESSING_MODE 0x4
310 #define IGB_SFF_8472_UNSUP 0x00