1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2014-2018 Cavium Inc.
16 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
21 uint32_t max_iscsi_conn;
22 #define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
23 #define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0
24 #define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
25 #define LICENSE_MAX_ISCSI_INIT_CONN_SHIFT 16
29 uint32_t max_fcoe_conn;
30 #define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
31 #define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0
32 #define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
33 #define LICENSE_MAX_FCOE_INIT_CONN_SHIFT 16
35 uint32_t reserved_b[4];
38 typedef struct license_key license_key_t;
41 /****************************************************************************
42 * Shared HW configuration *
43 ****************************************************************************/
44 #define PIN_CFG_NA 0x00000000
45 #define PIN_CFG_GPIO0_P0 0x00000001
46 #define PIN_CFG_GPIO1_P0 0x00000002
47 #define PIN_CFG_GPIO2_P0 0x00000003
48 #define PIN_CFG_GPIO3_P0 0x00000004
49 #define PIN_CFG_GPIO0_P1 0x00000005
50 #define PIN_CFG_GPIO1_P1 0x00000006
51 #define PIN_CFG_GPIO2_P1 0x00000007
52 #define PIN_CFG_GPIO3_P1 0x00000008
53 #define PIN_CFG_EPIO0 0x00000009
54 #define PIN_CFG_EPIO1 0x0000000a
55 #define PIN_CFG_EPIO2 0x0000000b
56 #define PIN_CFG_EPIO3 0x0000000c
57 #define PIN_CFG_EPIO4 0x0000000d
58 #define PIN_CFG_EPIO5 0x0000000e
59 #define PIN_CFG_EPIO6 0x0000000f
60 #define PIN_CFG_EPIO7 0x00000010
61 #define PIN_CFG_EPIO8 0x00000011
62 #define PIN_CFG_EPIO9 0x00000012
63 #define PIN_CFG_EPIO10 0x00000013
64 #define PIN_CFG_EPIO11 0x00000014
65 #define PIN_CFG_EPIO12 0x00000015
66 #define PIN_CFG_EPIO13 0x00000016
67 #define PIN_CFG_EPIO14 0x00000017
68 #define PIN_CFG_EPIO15 0x00000018
69 #define PIN_CFG_EPIO16 0x00000019
70 #define PIN_CFG_EPIO17 0x0000001a
71 #define PIN_CFG_EPIO18 0x0000001b
72 #define PIN_CFG_EPIO19 0x0000001c
73 #define PIN_CFG_EPIO20 0x0000001d
74 #define PIN_CFG_EPIO21 0x0000001e
75 #define PIN_CFG_EPIO22 0x0000001f
76 #define PIN_CFG_EPIO23 0x00000020
77 #define PIN_CFG_EPIO24 0x00000021
78 #define PIN_CFG_EPIO25 0x00000022
79 #define PIN_CFG_EPIO26 0x00000023
80 #define PIN_CFG_EPIO27 0x00000024
81 #define PIN_CFG_EPIO28 0x00000025
82 #define PIN_CFG_EPIO29 0x00000026
83 #define PIN_CFG_EPIO30 0x00000027
84 #define PIN_CFG_EPIO31 0x00000028
87 #define EPIO_CFG_NA 0x00000000
88 #define EPIO_CFG_EPIO0 0x00000001
89 #define EPIO_CFG_EPIO1 0x00000002
90 #define EPIO_CFG_EPIO2 0x00000003
91 #define EPIO_CFG_EPIO3 0x00000004
92 #define EPIO_CFG_EPIO4 0x00000005
93 #define EPIO_CFG_EPIO5 0x00000006
94 #define EPIO_CFG_EPIO6 0x00000007
95 #define EPIO_CFG_EPIO7 0x00000008
96 #define EPIO_CFG_EPIO8 0x00000009
97 #define EPIO_CFG_EPIO9 0x0000000a
98 #define EPIO_CFG_EPIO10 0x0000000b
99 #define EPIO_CFG_EPIO11 0x0000000c
100 #define EPIO_CFG_EPIO12 0x0000000d
101 #define EPIO_CFG_EPIO13 0x0000000e
102 #define EPIO_CFG_EPIO14 0x0000000f
103 #define EPIO_CFG_EPIO15 0x00000010
104 #define EPIO_CFG_EPIO16 0x00000011
105 #define EPIO_CFG_EPIO17 0x00000012
106 #define EPIO_CFG_EPIO18 0x00000013
107 #define EPIO_CFG_EPIO19 0x00000014
108 #define EPIO_CFG_EPIO20 0x00000015
109 #define EPIO_CFG_EPIO21 0x00000016
110 #define EPIO_CFG_EPIO22 0x00000017
111 #define EPIO_CFG_EPIO23 0x00000018
112 #define EPIO_CFG_EPIO24 0x00000019
113 #define EPIO_CFG_EPIO25 0x0000001a
114 #define EPIO_CFG_EPIO26 0x0000001b
115 #define EPIO_CFG_EPIO27 0x0000001c
116 #define EPIO_CFG_EPIO28 0x0000001d
117 #define EPIO_CFG_EPIO29 0x0000001e
118 #define EPIO_CFG_EPIO30 0x0000001f
119 #define EPIO_CFG_EPIO31 0x00000020
127 struct shared_hw_cfg { /* NVRAM Offset */
128 /* Up to 16 bytes of NULL-terminated string */
129 uint8_t part_num[16]; /* 0x104 */
131 uint32_t config; /* 0x114 */
132 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
133 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
134 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
135 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
137 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
139 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
141 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000
142 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010
144 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
145 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
146 /* Whatever MFW found in NVM
147 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
148 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
149 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
150 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
151 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
152 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
153 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
154 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
155 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
156 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
157 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
158 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
159 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
160 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
162 /* Adjust the PCIe G2 Tx amplitude driver for all Tx lanes. For
163 backwards compatibility, value of 0 is disabling this feature.
164 That means that though 0 is a valid value, it cannot be
166 #define SHARED_HW_CFG_G2_TX_DRIVE_MASK 0x0000F000
167 #define SHARED_HW_CFG_G2_TX_DRIVE_SHIFT 12
169 #define SHARED_HW_CFG_LED_MODE_MASK 0x000F0000
170 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
171 #define SHARED_HW_CFG_LED_MAC1 0x00000000
172 #define SHARED_HW_CFG_LED_PHY1 0x00010000
173 #define SHARED_HW_CFG_LED_PHY2 0x00020000
174 #define SHARED_HW_CFG_LED_PHY3 0x00030000
175 #define SHARED_HW_CFG_LED_MAC2 0x00040000
176 #define SHARED_HW_CFG_LED_PHY4 0x00050000
177 #define SHARED_HW_CFG_LED_PHY5 0x00060000
178 #define SHARED_HW_CFG_LED_PHY6 0x00070000
179 #define SHARED_HW_CFG_LED_MAC3 0x00080000
180 #define SHARED_HW_CFG_LED_PHY7 0x00090000
181 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
182 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
183 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
184 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
185 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
186 #define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000
188 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000
189 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000
190 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000
192 #define SHARED_HW_CFG_ATC_MASK 0x80000000
193 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000
194 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000
196 uint32_t config2; /* 0x118 */
198 #define SHARED_HW_CFG_PCIE_GEN2_MASK 0x00000100
199 #define SHARED_HW_CFG_PCIE_GEN2_SHIFT 8
200 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000
201 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
203 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000
204 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
205 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
207 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
210 /* Output low when PERST is asserted */
211 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000
212 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000
213 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000
215 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000
216 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16
217 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000
218 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000
219 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000
220 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000
222 /* The fan failure mechanism is usually related to the PHY type
223 since the power consumption of the board is determined by the PHY.
224 Currently, fan is required for most designs with SFX7101, BNX2X8727
225 and BNX2X8481. If a fan is not required for a board which uses one
226 of those PHYs, this field should be set to "Disabled". If a fan is
227 required for a different PHY type, this option should be set to
228 "Enabled". The fan failure indication is expected on SPIO5 */
229 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
230 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
231 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
232 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
233 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
235 /* ASPM Power Management support */
236 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000
237 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21
238 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000
239 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000
240 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000
241 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000
243 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register
244 tl_control_0 (register 0x2800) */
245 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000
246 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000
247 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000
250 /* Set the MDC/MDIO access for the first external phy */
251 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
252 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26
253 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
254 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
255 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
256 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
257 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
259 /* Set the MDC/MDIO access for the second external phy */
260 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
261 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29
262 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
263 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
264 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
265 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
266 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
268 /* Max number of PF MSIX vectors */
269 uint32_t config_3; /* 0x11C */
270 #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK 0x0000007F
271 #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0
273 uint32_t ump_nc_si_config; /* 0x120 */
274 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
275 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
276 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
277 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
278 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
279 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
281 /* Reserved bits: 226-230 */
283 /* The output pin template BSC_SEL which selects the I2C for this
284 port in the I2C Mux */
285 uint32_t board; /* 0x124 */
286 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F
287 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0
289 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0
290 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6
291 /* Use the PIN_CFG_XXX defines on top */
292 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000
293 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
295 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000
296 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
298 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000
299 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
301 uint32_t wc_lane_config; /* 0x128 */
302 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
303 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0
304 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b
305 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4
306 #define SHARED_HW_CFG_LANE_SWAP_CFG_31200213 0x000027d8
307 #define SHARED_HW_CFG_LANE_SWAP_CFG_02133120 0x0000d827
308 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b
309 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4
310 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
311 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
312 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
313 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
315 /* TX lane Polarity swap */
316 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000
317 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000
318 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000
319 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000
320 /* TX lane Polarity swap */
321 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000
322 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000
323 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000
324 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000
326 /* Selects the port layout of the board */
327 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000
328 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24
329 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000
330 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000
331 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000
332 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000
333 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000
334 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000
338 /****************************************************************************
339 * Port HW configuration *
340 ****************************************************************************/
341 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
344 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000FFFF
345 #define PORT_HW_CFG_PCI_DEVICE_ID_SHIFT 0
347 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xFFFF0000
348 #define PORT_HW_CFG_PCI_VENDOR_ID_SHIFT 16
351 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000FFFF
352 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_SHIFT 0
354 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xFFFF0000
355 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_SHIFT 16
357 uint32_t power_dissipated;
358 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000FF
359 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
360 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000FF00
361 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
362 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00FF0000
363 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
364 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xFF000000
365 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
367 uint32_t power_consumed;
368 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000FF
369 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
370 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000FF00
371 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
372 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00FF0000
373 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
374 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xFF000000
375 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
378 uint32_t mac_lower; /* 0x140 */
379 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000FFFF
380 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
383 uint32_t iscsi_mac_upper; /* Upper 16 bits are always zeroes */
384 uint32_t iscsi_mac_lower;
386 uint32_t rdma_mac_upper; /* Upper 16 bits are always zeroes */
387 uint32_t rdma_mac_lower;
389 uint32_t serdes_config;
390 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF
391 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
393 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000
394 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
397 /* Default values: 2P-64, 4P-32 */
400 uint32_t vf_config; /* 0x15C */
401 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000
402 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16
404 uint32_t mf_pci_id; /* 0x160 */
405 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF
406 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0
408 /* Controls the TX laser of the SFP+ module */
409 uint32_t sfp_ctrl; /* 0x164 */
410 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF
411 #define PORT_HW_CFG_TX_LASER_SHIFT 0
412 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000
413 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001
414 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002
415 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003
416 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004
418 /* Controls the fault module LED of the SFP+ */
419 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00
420 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8
421 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000
422 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100
423 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200
424 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300
425 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400
427 /* The output pin TX_DIS that controls the TX laser of the SFP+
428 module. Use the PIN_CFG_XXX defines on top */
429 uint32_t e3_sfp_ctrl; /* 0x168 */
430 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF
431 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0
433 /* The output pin for SFPP_TYPE which turns on the Fault module LED */
434 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00
435 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8
437 /* The input pin MOD_ABS that indicates whether SFP+ module is
438 present or not. Use the PIN_CFG_XXX defines on top */
439 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000
440 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16
442 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+
443 module. Use the PIN_CFG_XXX defines on top */
444 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000
445 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24
448 * The input pin which signals module transmit fault. Use the
449 * PIN_CFG_XXX defines on top
451 uint32_t e3_cmn_pin_cfg; /* 0x16C */
452 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF
453 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0
455 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on
457 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00
458 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8
461 * The output pin which powers down the PHY. Use the PIN_CFG_XXX
464 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000
465 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16
467 /* The output pin values BSC_SEL which selects the I2C for this port
469 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000
470 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000
474 * The input pin I_FAULT which indicate over-current has occurred.
475 * Use the PIN_CFG_XXX defines on top
477 uint32_t e3_cmn_pin_cfg1; /* 0x170 */
478 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF
479 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0
481 /* pause on host ring */
482 uint32_t generic_features; /* 0x174 */
483 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001
484 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0
485 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000
486 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001
488 /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2
489 * LOM recommended and tested value is 0xBEB2. Using a different
490 * value means using a value not tested by BRCM
492 uint32_t sfi_tap_values; /* 0x178 */
493 #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF
494 #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0
496 /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested
497 * value is 0x2. LOM recommended and tested value is 0x2. Using a
498 * different value means using a value not tested by BRCM
500 #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000
501 #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16
503 /* Set non-default values for TXFIR in SFP mode. */
504 #define PORT_HW_CFG_TX_DRV_IFIR_MASK 0x00F00000
505 #define PORT_HW_CFG_TX_DRV_IFIR_SHIFT 20
507 /* Set non-default values for IPREDRIVER in SFP mode. */
508 #define PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK 0x0F000000
509 #define PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT 24
511 /* Set non-default values for POST2 in SFP mode. */
512 #define PORT_HW_CFG_TX_DRV_POST2_MASK 0xF0000000
513 #define PORT_HW_CFG_TX_DRV_POST2_SHIFT 28
515 uint32_t reserved0[5]; /* 0x17c */
517 uint32_t aeu_int_mask; /* 0x190 */
519 uint32_t media_type; /* 0x194 */
520 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF
521 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0
523 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00
524 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8
526 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000
527 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16
529 /* 4 times 16 bits for all 4 lanes. In case external PHY is present
530 (not direct mode), those values will not take effect on the 4 XGXS
531 lanes. For some external PHYs (such as 8706 and 8726) the values
532 will be used to configure the external PHY in those cases, not
533 all 4 values are needed. */
534 uint16_t xgxs_config_rx[4]; /* 0x198 */
535 uint16_t xgxs_config_tx[4]; /* 0x1A0 */
538 /* For storing FCOE mac on shared memory */
539 uint32_t fcoe_fip_mac_upper;
540 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff
541 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0
542 uint32_t fcoe_fip_mac_lower;
544 uint32_t fcoe_wwn_port_name_upper;
545 uint32_t fcoe_wwn_port_name_lower;
547 uint32_t fcoe_wwn_node_name_upper;
548 uint32_t fcoe_wwn_node_name_lower;
550 /* wwpn for npiv enabled */
551 uint32_t wwpn_for_npiv_config; /* 0x1C0 */
552 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_MASK 0x00000001
553 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_SHIFT 0
554 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_DISABLED 0x00000000
555 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_ENABLED 0x00000001
557 /* wwpn for npiv valid addresses */
558 uint32_t wwpn_for_npiv_valid_addresses; /* 0x1C4 */
559 #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_MASK 0x0000FFFF
560 #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_SHIFT 0
562 struct mac_addr wwpn_for_niv_macs[16];
564 /* Reserved bits: 2272-2336 For storing FCOE mac on shared memory */
565 uint32_t Reserved1[14];
567 uint32_t pf_allocation; /* 0x280 */
568 /* number of vfs per PF, if 0 - sriov disabled */
569 #define PORT_HW_CFG_NUMBER_OF_VFS_MASK 0x000000FF
570 #define PORT_HW_CFG_NUMBER_OF_VFS_SHIFT 0
572 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
574 uint32_t xgbt_phy_cfg; /* 0x284 */
575 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF
576 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0
578 uint32_t default_cfg; /* 0x288 */
579 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003
580 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0
581 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000
582 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001
583 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002
584 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003
586 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C
587 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2
588 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000
589 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004
590 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008
591 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c
593 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030
594 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4
595 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000
596 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010
597 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020
598 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030
600 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0
601 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6
602 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000
603 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040
604 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080
605 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0
607 /* When KR link is required to be set to force which is not
608 KR-compliant, this parameter determine what is the trigger for it.
609 When GPIO is selected, low input will force the speed. Currently
610 default speed is 1G. In the future, it may be widen to select the
611 forced speed in with another parameter. Note when force-1G is
612 enabled, it override option 56: Link Speed option. */
613 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00
614 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8
615 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000
616 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100
617 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200
618 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300
619 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400
620 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500
621 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600
622 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700
623 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800
624 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900
625 /* Enable to determine with which GPIO to reset the external phy */
626 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000
627 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16
628 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000
629 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000
630 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000
631 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000
632 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000
633 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000
634 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000
635 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000
636 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000
638 /* Enable BAM on KR */
639 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
640 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
641 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
642 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
644 /* Enable Common Mode Sense */
645 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000
646 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21
647 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000
648 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000
650 /* Determine the Serdes electrical interface */
651 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000
652 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24
653 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000
654 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000
655 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000
656 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000
657 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000
658 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000
660 /* SFP+ main TAP and post TAP volumes */
661 #define PORT_HW_CFG_TAP_LEVELS_MASK 0x70000000
662 #define PORT_HW_CFG_TAP_LEVELS_SHIFT 28
663 #define PORT_HW_CFG_TAP_LEVELS_POST_15_MAIN_43 0x00000000
664 #define PORT_HW_CFG_TAP_LEVELS_POST_14_MAIN_44 0x10000000
665 #define PORT_HW_CFG_TAP_LEVELS_POST_13_MAIN_45 0x20000000
666 #define PORT_HW_CFG_TAP_LEVELS_POST_12_MAIN_46 0x30000000
667 #define PORT_HW_CFG_TAP_LEVELS_POST_11_MAIN_47 0x40000000
668 #define PORT_HW_CFG_TAP_LEVELS_POST_10_MAIN_48 0x50000000
670 uint32_t speed_capability_mask2; /* 0x28C */
671 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
672 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
673 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
674 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF 0x00000002
675 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004
676 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
677 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
678 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G 0x00000020
679 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
680 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080
682 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
683 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
684 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
685 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_HALF 0x00020000
686 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_HALF 0x00040000
687 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
688 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
689 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_5G 0x00200000
690 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
691 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000
694 /* In the case where two media types (e.g. copper and fiber) are
695 present and electrically active at the same time, PHY Selection
696 will determine which of the two PHYs will be designated as the
697 Active PHY and used for a connection to the network. */
698 uint32_t multi_phy_config; /* 0x290 */
699 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
700 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
701 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
702 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
703 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
704 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
705 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
707 /* When enabled, all second phy nvram parameters will be swapped
708 with the first phy parameters */
709 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
710 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
711 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
712 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
715 /* Address of the second external phy */
716 uint32_t external_phy_config2; /* 0x294 */
717 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
718 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
720 /* The second XGXS external PHY type */
721 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
722 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
723 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
724 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8071 0x00000100
725 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8072 0x00000200
726 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8073 0x00000300
727 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8705 0x00000400
728 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8706 0x00000500
729 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8726 0x00000600
730 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8481 0x00000700
731 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
732 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8727 0x00000900
733 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8727_NOC 0x00000a00
734 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84823 0x00000b00
735 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54640 0x00000c00
736 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84833 0x00000d00
737 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE 0x00000e00
738 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8722 0x00000f00
739 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54616 0x00001000
740 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84834 0x00001100
741 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
742 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
745 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as
746 8706, 8726 and 8727) not all 4 values are needed. */
747 uint16_t xgxs_config2_rx[4]; /* 0x296 */
748 uint16_t xgxs_config2_tx[4]; /* 0x2A0 */
750 uint32_t lane_config;
751 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
752 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
754 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
756 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
758 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
760 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
761 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
762 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
763 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
764 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
765 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000C000
766 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
768 /* Indicate whether to swap the external phy polarity */
769 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
770 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
771 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
774 uint32_t external_phy_config;
775 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000FF
776 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
778 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000FF00
779 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
780 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
781 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8071 0x00000100
782 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8072 0x00000200
783 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073 0x00000300
784 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705 0x00000400
785 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706 0x00000500
786 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726 0x00000600
787 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481 0x00000700
788 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
789 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727 0x00000900
790 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC 0x00000a00
791 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823 0x00000b00
792 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54640 0x00000c00
793 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833 0x00000d00
794 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE 0x00000e00
795 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722 0x00000f00
796 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616 0x00001000
797 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834 0x00001100
798 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84858 0x00001200
799 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
800 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
801 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
803 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00FF0000
804 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
806 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xFF000000
807 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
808 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
809 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BNX2X5482 0x01000000
810 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000
811 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
813 uint32_t speed_capability_mask;
814 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000FFFF
815 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
816 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
817 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
818 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
819 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
820 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
821 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
822 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
823 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080
824 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
826 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xFFFF0000
827 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
828 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
829 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
830 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
831 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
832 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
833 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
834 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
835 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000
836 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
838 /* A place to hold the original MAC address as a backup */
839 uint32_t backup_mac_upper; /* 0x2B4 */
840 uint32_t backup_mac_lower; /* 0x2B8 */
845 /****************************************************************************
846 * Shared Feature configuration *
847 ****************************************************************************/
848 struct shared_feat_cfg { /* NVRAM Offset */
850 uint32_t config; /* 0x450 */
851 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
853 /* Use NVRAM values instead of HW default values */
854 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
856 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
858 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
861 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008
862 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000
863 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008
865 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030
866 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4
868 /* Override the OTP back to single function mode. When using GPIO,
869 high means only SF, 0 is according to CLP configuration */
870 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
871 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8
872 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
873 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
874 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
875 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
876 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400
878 /* Act as if the FCoE license is invalid */
879 #define SHARED_FEAT_CFG_PREVENT_FCOE 0x00001000
881 /* Force FLR capability to all ports */
882 #define SHARED_FEAT_CFG_FORCE_FLR_CAPABILITY 0x00002000
884 /* Act as if the iSCSI license is invalid */
885 #define SHARED_FEAT_CFG_PREVENT_ISCSI_MASK 0x00004000
886 #define SHARED_FEAT_CFG_PREVENT_ISCSI_SHIFT 14
887 #define SHARED_FEAT_CFG_PREVENT_ISCSI_DISABLED 0x00000000
888 #define SHARED_FEAT_CFG_PREVENT_ISCSI_ENABLED 0x00004000
890 /* The interval in seconds between sending LLDP packets. Set to zero
891 to disable the feature */
892 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00FF0000
893 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16
895 /* The assigned device type ID for LLDP usage */
896 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xFF000000
897 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24
902 /****************************************************************************
903 * Port Feature configuration *
904 ****************************************************************************/
905 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
908 #define PORT_FEAT_CFG_BAR1_SIZE_MASK 0x0000000F
909 #define PORT_FEAT_CFG_BAR1_SIZE_SHIFT 0
910 #define PORT_FEAT_CFG_BAR1_SIZE_DISABLED 0x00000000
911 #define PORT_FEAT_CFG_BAR1_SIZE_64K 0x00000001
912 #define PORT_FEAT_CFG_BAR1_SIZE_128K 0x00000002
913 #define PORT_FEAT_CFG_BAR1_SIZE_256K 0x00000003
914 #define PORT_FEAT_CFG_BAR1_SIZE_512K 0x00000004
915 #define PORT_FEAT_CFG_BAR1_SIZE_1M 0x00000005
916 #define PORT_FEAT_CFG_BAR1_SIZE_2M 0x00000006
917 #define PORT_FEAT_CFG_BAR1_SIZE_4M 0x00000007
918 #define PORT_FEAT_CFG_BAR1_SIZE_8M 0x00000008
919 #define PORT_FEAT_CFG_BAR1_SIZE_16M 0x00000009
920 #define PORT_FEAT_CFG_BAR1_SIZE_32M 0x0000000a
921 #define PORT_FEAT_CFG_BAR1_SIZE_64M 0x0000000b
922 #define PORT_FEAT_CFG_BAR1_SIZE_128M 0x0000000c
923 #define PORT_FEAT_CFG_BAR1_SIZE_256M 0x0000000d
924 #define PORT_FEAT_CFG_BAR1_SIZE_512M 0x0000000e
925 #define PORT_FEAT_CFG_BAR1_SIZE_1G 0x0000000f
926 #define PORT_FEAT_CFG_BAR2_SIZE_MASK 0x000000F0
927 #define PORT_FEAT_CFG_BAR2_SIZE_SHIFT 4
928 #define PORT_FEAT_CFG_BAR2_SIZE_DISABLED 0x00000000
929 #define PORT_FEAT_CFG_BAR2_SIZE_64K 0x00000010
930 #define PORT_FEAT_CFG_BAR2_SIZE_128K 0x00000020
931 #define PORT_FEAT_CFG_BAR2_SIZE_256K 0x00000030
932 #define PORT_FEAT_CFG_BAR2_SIZE_512K 0x00000040
933 #define PORT_FEAT_CFG_BAR2_SIZE_1M 0x00000050
934 #define PORT_FEAT_CFG_BAR2_SIZE_2M 0x00000060
935 #define PORT_FEAT_CFG_BAR2_SIZE_4M 0x00000070
936 #define PORT_FEAT_CFG_BAR2_SIZE_8M 0x00000080
937 #define PORT_FEAT_CFG_BAR2_SIZE_16M 0x00000090
938 #define PORT_FEAT_CFG_BAR2_SIZE_32M 0x000000a0
939 #define PORT_FEAT_CFG_BAR2_SIZE_64M 0x000000b0
940 #define PORT_FEAT_CFG_BAR2_SIZE_128M 0x000000c0
941 #define PORT_FEAT_CFG_BAR2_SIZE_256M 0x000000d0
942 #define PORT_FEAT_CFG_BAR2_SIZE_512M 0x000000e0
943 #define PORT_FEAT_CFG_BAR2_SIZE_1G 0x000000f0
945 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100
946 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000
947 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100
949 #define PORT_FEAT_CFG_AUTOGREEEN_MASK 0x00000200
950 #define PORT_FEAT_CFG_AUTOGREEEN_SHIFT 9
951 #define PORT_FEAT_CFG_AUTOGREEEN_DISABLED 0x00000000
952 #define PORT_FEAT_CFG_AUTOGREEEN_ENABLED 0x00000200
954 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00
955 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_SHIFT 10
956 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_DEFAULT 0x00000000
957 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400
958 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800
959 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH 0x00000c00
961 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000
962 #define PORT_FEATURE_EN_SIZE_SHIFT 24
963 #define PORT_FEATURE_WOL_ENABLED 0x01000000
964 #define PORT_FEATURE_MBA_ENABLED 0x02000000
965 #define PORT_FEATURE_MFW_ENABLED 0x04000000
967 /* Advertise expansion ROM even if MBA is disabled */
968 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000
969 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000
970 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000
972 /* Check the optic vendor via i2c against a list of approved modules
973 in a separate nvram image */
974 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000
975 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
976 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
978 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
980 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
981 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
984 /* Default is used when driver sets to "auto" mode */
985 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
988 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007
989 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
990 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
991 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
992 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
993 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
994 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004
995 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007
997 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038
998 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3
1000 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
1001 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800
1002 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
1003 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
1005 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000FF000
1006 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
1007 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
1008 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
1009 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
1010 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
1011 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
1012 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
1013 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
1014 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
1015 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
1016 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
1017 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
1018 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
1019 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
1020 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
1021 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
1022 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
1023 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00F00000
1024 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
1025 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
1026 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
1027 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
1028 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
1029 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
1030 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
1031 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3C000000
1032 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
1033 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
1034 #define PORT_FEATURE_MBA_LINK_SPEED_10M_HALF 0x04000000
1035 #define PORT_FEATURE_MBA_LINK_SPEED_10M_FULL 0x08000000
1036 #define PORT_FEATURE_MBA_LINK_SPEED_100M_HALF 0x0c000000
1037 #define PORT_FEATURE_MBA_LINK_SPEED_100M_FULL 0x10000000
1038 #define PORT_FEATURE_MBA_LINK_SPEED_1G 0x14000000
1039 #define PORT_FEATURE_MBA_LINK_SPEED_2_5G 0x18000000
1040 #define PORT_FEATURE_MBA_LINK_SPEED_10G 0x1c000000
1041 #define PORT_FEATURE_MBA_LINK_SPEED_20G 0x20000000
1043 uint32_t Reserved0; /* 0x460 */
1045 uint32_t mba_vlan_cfg;
1046 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000FFFF
1047 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
1048 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
1051 uint32_t smbus_config;
1052 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
1053 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
1056 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000F
1057 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0
1058 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000
1059 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001
1060 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002
1061 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003
1062 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004
1063 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005
1064 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006
1065 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007
1066 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008
1067 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009
1068 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a
1069 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b
1070 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c
1071 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d
1072 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e
1073 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f
1075 uint32_t link_config; /* Used as HW defaults for the driver */
1077 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
1078 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
1079 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
1080 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
1081 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
1082 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
1083 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
1084 #define PORT_FEATURE_FLOW_CONTROL_SAFC_RX 0x00000500
1085 #define PORT_FEATURE_FLOW_CONTROL_SAFC_TX 0x00000600
1086 #define PORT_FEATURE_FLOW_CONTROL_SAFC_BOTH 0x00000700
1088 #define PORT_FEATURE_LINK_SPEED_MASK 0x000F0000
1089 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
1090 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
1091 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
1092 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
1093 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
1094 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
1095 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
1096 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
1097 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
1098 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000
1100 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
1101 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
1102 /* (forced) low speed switch (< 10G) */
1103 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
1104 /* (forced) high speed switch (>= 10G) */
1105 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
1106 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
1107 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
1110 /* The default for MCP link configuration,
1111 uses the same defines as link_config */
1112 uint32_t mfw_wol_link_cfg;
1114 /* The default for the driver of the second external phy,
1115 uses the same defines as link_config */
1116 uint32_t link_config2; /* 0x47C */
1118 /* The default for MCP of the second external phy,
1119 uses the same defines as link_config */
1120 uint32_t mfw_wol_link_cfg2; /* 0x480 */
1123 /* EEE power saving mode */
1124 uint32_t eee_power_mode; /* 0x484 */
1125 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF
1126 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0
1127 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000
1128 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001
1129 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002
1130 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003
1133 uint32_t Reserved2[16]; /* 0x488 */
1136 /****************************************************************************
1137 * Device Information *
1138 ****************************************************************************/
1139 struct shm_dev_info { /* size */
1141 uint32_t bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
1143 struct shared_hw_cfg shared_hw_config; /* 40 */
1145 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
1147 struct shared_feat_cfg shared_feature_config; /* 4 */
1149 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */
1153 struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */
1155 /* Threshold in celcius to start using the fan */
1156 uint32_t temperature_monitor1; /* 0x4000 */
1157 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_MASK 0x0000007F
1158 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_SHIFT 0
1160 /* Threshold in celcius to shut down the board */
1161 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_MASK 0x00007F00
1162 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_SHIFT 8
1164 /* EPIO of fan temperature status */
1165 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_MASK 0x00FF0000
1166 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_SHIFT 16
1167 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_NA 0x00000000
1168 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO0 0x00010000
1169 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO1 0x00020000
1170 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO2 0x00030000
1171 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO3 0x00040000
1172 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO4 0x00050000
1173 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO5 0x00060000
1174 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO6 0x00070000
1175 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO7 0x00080000
1176 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO8 0x00090000
1177 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO9 0x000a0000
1178 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO10 0x000b0000
1179 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO11 0x000c0000
1180 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO12 0x000d0000
1181 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO13 0x000e0000
1182 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO14 0x000f0000
1183 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO15 0x00100000
1184 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO16 0x00110000
1185 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO17 0x00120000
1186 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO18 0x00130000
1187 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO19 0x00140000
1188 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO20 0x00150000
1189 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO21 0x00160000
1190 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO22 0x00170000
1191 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO23 0x00180000
1192 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO24 0x00190000
1193 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO25 0x001a0000
1194 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO26 0x001b0000
1195 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO27 0x001c0000
1196 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO28 0x001d0000
1197 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO29 0x001e0000
1198 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO30 0x001f0000
1199 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO31 0x00200000
1201 /* EPIO of shut down temperature status */
1202 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_MASK 0xFF000000
1203 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_SHIFT 24
1204 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_NA 0x00000000
1205 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO0 0x01000000
1206 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO1 0x02000000
1207 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO2 0x03000000
1208 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO3 0x04000000
1209 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO4 0x05000000
1210 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO5 0x06000000
1211 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO6 0x07000000
1212 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO7 0x08000000
1213 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO8 0x09000000
1214 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO9 0x0a000000
1215 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO10 0x0b000000
1216 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO11 0x0c000000
1217 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO12 0x0d000000
1218 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO13 0x0e000000
1219 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO14 0x0f000000
1220 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO15 0x10000000
1221 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO16 0x11000000
1222 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO17 0x12000000
1223 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO18 0x13000000
1224 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO19 0x14000000
1225 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO20 0x15000000
1226 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO21 0x16000000
1227 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO22 0x17000000
1228 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO23 0x18000000
1229 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO24 0x19000000
1230 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO25 0x1a000000
1231 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO26 0x1b000000
1232 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO27 0x1c000000
1233 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO28 0x1d000000
1234 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO29 0x1e000000
1235 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO30 0x1f000000
1236 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO31 0x20000000
1239 /* EPIO of shut down temperature status */
1240 uint32_t temperature_monitor2; /* 0x4004 */
1241 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK 0x0000FFFF
1242 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT 0
1245 /* MFW flavor to be used */
1246 uint32_t mfw_cfg; /* 0x4008 */
1247 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_MASK 0x000000FF
1248 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_SHIFT 0
1249 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_NA 0x00000000
1250 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_A 0x00000001
1252 /* Should NIC data query remain enabled upon last drv unload */
1253 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_MASK 0x00000100
1254 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_SHIFT 8
1255 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000
1256 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED 0x00000100
1258 /* Hide DCBX feature in CCM/BACS menus */
1259 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK 0x00010000
1260 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT 16
1261 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_DISABLED 0x00000000
1262 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_ENABLED 0x00010000
1264 uint32_t smbus_config; /* 0x400C */
1265 #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_MASK 0x000000FF
1266 #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_SHIFT 0
1268 /* Switching regulator loop gain */
1269 uint32_t board_cfg; /* 0x4010 */
1270 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_MASK 0x0000000F
1271 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_SHIFT 0
1272 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_HW_DEFAULT 0x00000000
1273 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X2 0x00000008
1274 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X4 0x00000009
1275 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X8 0x0000000a
1276 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X16 0x0000000b
1277 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV8 0x0000000c
1278 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV4 0x0000000d
1279 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV2 0x0000000e
1280 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X1 0x0000000f
1282 /* whether shadow swim feature is supported */
1283 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_MASK 0x00000100
1284 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_SHIFT 8
1285 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_DISABLED 0x00000000
1286 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_ENABLED 0x00000100
1288 /* whether to show/hide SRIOV menu in CCM */
1289 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_MASK 0x00000200
1290 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_SHIFT 9
1291 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU 0x00000000
1292 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU 0x00000200
1294 /* Threshold in celcius for max continuous operation */
1295 uint32_t temperature_report; /* 0x4014 */
1296 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK 0x0000007F
1297 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_SHIFT 0
1299 /* Threshold in celcius for sensor caution */
1300 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_MASK 0x00007F00
1301 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_SHIFT 8
1303 /* wwn node prefix to be used (unless value is 0) */
1304 uint32_t wwn_prefix; /* 0x4018 */
1305 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_MASK 0x000000FF
1306 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_SHIFT 0
1308 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_MASK 0x0000FF00
1309 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_SHIFT 8
1311 /* wwn port prefix to be used (unless value is 0) */
1312 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_MASK 0x00FF0000
1313 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_SHIFT 16
1315 /* wwn port prefix to be used (unless value is 0) */
1316 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_MASK 0xFF000000
1317 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_SHIFT 24
1319 /* General debug nvm cfg */
1320 uint32_t dbg_cfg_flags; /* 0x401C */
1321 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_MASK 0x000FFFFF
1322 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SHIFT 0
1323 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ENABLE 0x00000001
1324 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_EN_SIGDET_FILTER 0x00000002
1325 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_LP_TX_PRESET7 0x00000004
1326 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_TX_ANA_DEFAULT 0x00000008
1327 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_PLL_ANA_DEFAULT 0x00000010
1328 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_G1PLL_RETUNE 0x00000020
1329 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_RX_ANA_DEFAULT 0x00000040
1330 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_SERDES_RX_CLK 0x00000080
1331 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_RX_LP_EIEOS 0x00000100
1332 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FINALIZE_UCODE 0x00000200
1333 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_HOLDOFF_REQ 0x00000400
1334 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_OVERRIDE 0x00000800
1335 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GP_PORG_UC_RESET 0x00001000
1336 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SUPPRESS_COMPEN_EVT 0x00002000
1337 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ADJ_TXEQ_P0_P1 0x00004000
1338 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_G3_PLL_RETUNE 0x00008000
1339 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_MAC_PHY_CTL8 0x00010000
1340 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_MAC_G3_FRM_ERR 0x00020000
1341 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI 0x00040000
1342 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA 0x00080000
1344 /* Debug signet rx threshold */
1345 uint32_t dbg_rx_sigdet_threshold; /* 0x4020 */
1346 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK 0x00000007
1347 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_SHIFT 0
1349 /* Enable IFFE feature */
1350 uint32_t iffe_features; /* 0x4024 */
1351 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_MASK 0x00000001
1352 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_SHIFT 0
1353 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_DISABLED 0x00000000
1354 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_ENABLED 0x00000001
1356 /* Allowable port enablement (bitmask for ports 3-1) */
1357 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_MASK 0x0000000E
1358 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_SHIFT 1
1360 /* Allow iSCSI offload override */
1361 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_MASK 0x00000010
1362 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_SHIFT 4
1363 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_DISABLED 0x00000000
1364 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_ENABLED 0x00000010
1366 /* Allow FCoE offload override */
1367 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_MASK 0x00000020
1368 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_SHIFT 5
1369 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_DISABLED 0x00000000
1370 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_ENABLED 0x00000020
1372 /* Tie to adaptor */
1373 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_MASK 0x00008000
1374 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_SHIFT 15
1375 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_DISABLED 0x00000000
1376 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_ENABLED 0x00008000
1378 /* Currently enabled port(s) (bitmask for ports 3-1) */
1379 uint32_t current_iffe_mask; /* 0x4028 */
1380 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_MASK 0x0000000E
1381 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_SHIFT 1
1383 /* Current iSCSI offload */
1384 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_MASK 0x00000010
1385 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_SHIFT 4
1386 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_DISABLED 0x00000000
1387 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_ENABLED 0x00000010
1389 /* Current FCoE offload */
1390 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_MASK 0x00000020
1391 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_SHIFT 5
1392 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_DISABLED 0x00000000
1393 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_ENABLED 0x00000020
1395 /* FW set this pin to "0" (assert) these signal if either of its MAC
1396 * or PHY specific threshold values is exceeded.
1397 * Values are standard GPIO/EPIO pins.
1399 uint32_t threshold_pin; /* 0x402C */
1400 #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_MASK 0x000000FF
1401 #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_SHIFT 0
1402 #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_MASK 0x0000FF00
1403 #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_SHIFT 8
1404 #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_MASK 0x00FF0000
1405 #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_SHIFT 16
1407 /* MAC die temperature threshold in Celsius. */
1408 uint32_t mac_threshold_val; /* 0x4030 */
1409 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_MASK 0x000000FF
1410 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_SHIFT 0
1411 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_MASK 0x0000FF00
1412 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_SHIFT 8
1413 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_MASK 0x00FF0000
1414 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_SHIFT 16
1416 /* PHY die temperature threshold in Celsius. */
1417 uint32_t phy_threshold_val; /* 0x4034 */
1418 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_MASK 0x000000FF
1419 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_SHIFT 0
1420 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_MASK 0x0000FF00
1421 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_SHIFT 8
1422 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_MASK 0x00FF0000
1423 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_SHIFT 16
1425 /* External pins to communicate with host.
1426 * Values are standard GPIO/EPIO pins.
1428 uint32_t host_pin; /* 0x4038 */
1429 #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_MASK 0x000000FF
1430 #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_SHIFT 0
1431 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_MASK 0x0000FF00
1432 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_SHIFT 8
1433 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_MASK 0x00FF0000
1434 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT 16
1435 #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK 0xFF000000
1436 #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT 24
1440 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1441 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1452 #define E1H_FUNC_MAX 8
1453 #define E2_FUNC_MAX 4 /* per path */
1462 #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */
1463 /* This value (in milliseconds) determines the frequency of the driver
1464 * issuing the PULSE message code. The firmware monitors this periodic
1465 * pulse to determine when to switch to an OS-absent mode. */
1466 #define DRV_PULSE_PERIOD_MS 250
1468 /* This value (in milliseconds) determines how long the driver should
1469 * wait for an acknowledgement from the firmware before timing out. Once
1470 * the firmware has timed out, the driver will assume there is no firmware
1471 * running and there won't be any firmware-driver synchronization during a
1473 #define FW_ACK_TIME_OUT_MS 5000
1475 #define FW_ACK_POLL_TIME_MS 1
1477 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1479 #define MFW_TRACE_SIGNATURE 0x54524342
1481 /****************************************************************************
1482 * Driver <-> FW Mailbox *
1483 ****************************************************************************/
1484 struct drv_port_mb {
1486 uint32_t link_status;
1487 /* Driver should update this field on any link change event */
1489 #define LINK_STATUS_NONE (0<<0)
1490 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
1491 #define LINK_STATUS_LINK_UP 0x00000001
1492 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
1493 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
1494 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
1495 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
1496 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
1497 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
1498 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
1499 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
1500 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
1501 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
1502 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
1503 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
1504 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
1505 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
1506 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
1507 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1)
1508 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1)
1510 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
1511 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
1513 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
1514 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
1515 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
1517 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
1518 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
1519 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
1520 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
1521 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
1522 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
1523 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
1525 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
1526 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
1528 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
1529 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
1531 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
1532 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
1533 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
1534 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
1535 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
1537 #define LINK_STATUS_SERDES_LINK 0x00100000
1539 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
1540 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
1541 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
1542 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000
1544 #define LINK_STATUS_PFC_ENABLED 0x20000000
1546 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000
1547 #define LINK_STATUS_SFP_TX_FAULT 0x80000000
1551 uint32_t stat_nig_timer;
1553 /* MCP firmware does not use this field */
1554 uint32_t ext_phy_fw_version;
1559 struct drv_func_mb {
1561 uint32_t drv_mb_header;
1562 #define DRV_MSG_CODE_MASK 0xffff0000
1563 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
1564 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
1565 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
1566 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
1567 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
1568 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
1569 #define DRV_MSG_CODE_DCC_OK 0x30000000
1570 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
1571 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
1572 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
1573 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
1574 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
1575 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
1576 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
1577 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
1580 * The optic module verification command requires bootcode
1581 * v5.0.6 or later, te specific optic module verification command
1582 * requires bootcode v5.2.12 or later
1584 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
1585 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
1586 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
1587 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
1588 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000
1589 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002
1590 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014
1591 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201
1592 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201
1593 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209
1595 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
1596 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
1597 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401
1599 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
1601 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000
1602 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000
1603 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000
1604 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000
1605 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000
1607 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000
1608 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000
1610 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000
1612 #define DRV_MSG_CODE_RMMOD 0xdb000000
1613 #define REQ_BC_VER_4_RMMOD_CMD 0x0007080f
1615 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000
1616 #define REQ_BC_VER_4_SET_MF_BW 0x00060202
1617 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
1619 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000
1621 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000
1622 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213
1624 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
1625 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
1626 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1627 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1629 #define DRV_MSG_CODE_IMG_OFFSET_REQ 0xe2000000
1630 #define DRV_MSG_CODE_IMG_SIZE_REQ 0xe3000000
1632 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1634 uint32_t drv_mb_param;
1635 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000
1636 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000
1638 #define DRV_MSG_CODE_UNLOAD_NON_D3_POWER 0x00000001
1639 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002
1641 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a
1642 #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000
1644 #define DRV_MSG_CODE_USR_BLK_IMAGE_REQ 0x00000001
1646 uint32_t fw_mb_header;
1647 #define FW_MSG_CODE_MASK 0xffff0000
1648 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
1649 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1650 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1651 /* Load common chip is supported from bc 6.0.0 */
1652 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
1653 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
1655 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
1656 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1657 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
1658 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
1659 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
1660 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1661 #define FW_MSG_CODE_DCC_DONE 0x30100000
1662 #define FW_MSG_CODE_LLDP_DONE 0x40100000
1663 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
1664 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
1665 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
1666 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
1667 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
1668 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
1669 #define FW_MSG_CODE_NO_KEY 0x80f00000
1670 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
1671 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
1672 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
1673 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
1674 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
1675 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
1676 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
1677 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
1678 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
1679 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1680 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000
1682 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000
1683 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000
1684 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000
1685 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000
1686 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000
1688 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000
1689 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000
1691 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000
1693 #define FW_MSG_CODE_RMMOD_ACK 0xdb100000
1695 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000
1696 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000
1698 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000
1700 #define FW_MSG_CODE_FLR_ACK 0x02000000
1701 #define FW_MSG_CODE_FLR_NACK 0x02100000
1703 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
1704 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
1705 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1706 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1708 #define FW_MSG_CODE_IMG_OFFSET_RESPONSE 0xe2100000
1709 #define FW_MSG_CODE_IMG_SIZE_RESPONSE 0xe3100000
1711 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1713 uint32_t fw_mb_param;
1715 #define FW_PARAM_INVALID_IMG 0xffffffff
1717 uint32_t drv_pulse_mb;
1718 #define DRV_PULSE_SEQ_MASK 0x00007fff
1719 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1721 * The system time is in the format of
1722 * (year-2001)*12*32 + month*32 + day.
1724 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1726 * Indicate to the firmware not to go into the
1727 * OS-absent when it is not getting driver pulse.
1728 * This is used for debugging as well for PXE(MBA).
1731 uint32_t mcp_pulse_mb;
1732 #define MCP_PULSE_SEQ_MASK 0x00007fff
1733 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1734 /* Indicates to the driver not to assert due to lack
1735 * of MCP response */
1736 #define MCP_EVENT_MASK 0xffff0000
1737 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1739 uint32_t iscsi_boot_signature;
1740 uint32_t iscsi_boot_block_offset;
1742 uint32_t drv_status;
1743 #define DRV_STATUS_PMF 0x00000001
1744 #define DRV_STATUS_VF_DISABLED 0x00000002
1745 #define DRV_STATUS_SET_MF_BW 0x00000004
1746 #define DRV_STATUS_LINK_EVENT 0x00000008
1748 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
1749 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
1750 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
1751 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
1752 #define DRV_STATUS_DCC_RESERVED1 0x00000800
1753 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
1754 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
1756 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
1757 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
1758 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000
1759 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000
1760 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000
1761 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000
1762 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000
1764 #define DRV_STATUS_DRV_INFO_REQ 0x04000000
1766 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000
1768 uint32_t virt_mac_upper;
1769 #define VIRT_MAC_SIGN_MASK 0xffff0000
1770 #define VIRT_MAC_SIGNATURE 0x564d0000
1771 uint32_t virt_mac_lower;
1776 /****************************************************************************
1777 * Management firmware state *
1778 ****************************************************************************/
1779 /* Allocate 440 bytes for management firmware */
1780 #define MGMTFW_STATE_WORD_SIZE 110
1782 struct mgmtfw_state {
1783 uint32_t opaque[MGMTFW_STATE_WORD_SIZE];
1787 /****************************************************************************
1788 * Multi-Function configuration *
1789 ****************************************************************************/
1790 struct shared_mf_cfg {
1793 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
1795 #define SHARED_MF_CLP_EXIT 0x00000001
1797 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
1801 struct port_mf_cfg {
1803 uint32_t dynamic_cfg; /* device control channel */
1804 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1805 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
1806 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
1808 uint32_t reserved[1];
1812 struct func_mf_cfg {
1816 /* function 0 of each port cannot be hidden */
1817 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
1819 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006
1820 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000
1821 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
1822 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1823 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
1824 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1825 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1827 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
1828 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010
1830 #define FUNC_MF_CFG_FUNC_BOOT_MASK 0x00000060
1831 #define FUNC_MF_CFG_FUNC_BOOT_BIOS_CTRL 0x00000000
1832 #define FUNC_MF_CFG_FUNC_BOOT_VCM_DISABLED 0x00000020
1833 #define FUNC_MF_CFG_FUNC_BOOT_VCM_ENABLED 0x00000040
1836 /* 0 - low priority, 3 - high priority */
1837 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
1838 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
1839 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
1842 /* value range - 0..100, increments in 100Mbps */
1843 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
1844 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
1845 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
1846 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
1847 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
1848 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
1850 uint32_t mac_upper; /* MAC */
1851 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
1852 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
1853 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
1855 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
1857 uint32_t e1hov_tag; /* VNI */
1858 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1859 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
1860 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
1862 /* afex default VLAN ID - 12 bits */
1863 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000
1864 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16
1866 uint32_t afex_config;
1867 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff
1868 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0
1869 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00
1870 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8
1871 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100
1872 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000
1873 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16
1875 uint32_t pf_allocation;
1876 /* number of vfs in function, if 0 - sriov disabled */
1877 #define FUNC_MF_CFG_NUMBER_OF_VFS_MASK 0x000000FF
1878 #define FUNC_MF_CFG_NUMBER_OF_VFS_SHIFT 0
1881 enum mf_cfg_afex_vlan_mode {
1882 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,
1883 FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE,
1884 FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE
1887 /* This structure is not applicable and should not be accessed on 57711 */
1888 struct func_ext_cfg {
1890 #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F
1891 #define MACP_FUNC_CFG_FLAGS_SHIFT 0
1892 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001
1893 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002
1894 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004
1895 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008
1896 #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080
1898 uint32_t iscsi_mac_addr_upper;
1899 uint32_t iscsi_mac_addr_lower;
1901 uint32_t fcoe_mac_addr_upper;
1902 uint32_t fcoe_mac_addr_lower;
1904 uint32_t fcoe_wwn_port_name_upper;
1905 uint32_t fcoe_wwn_port_name_lower;
1907 uint32_t fcoe_wwn_node_name_upper;
1908 uint32_t fcoe_wwn_node_name_lower;
1910 uint32_t preserve_data;
1911 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)
1912 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1)
1913 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2)
1914 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3)
1915 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4)
1916 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5)
1921 struct shared_mf_cfg shared_mf_config; /* 0x4 */
1922 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX];
1924 /* for all chips, there are 8 mf functions */
1925 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
1927 * Extended configuration per function - this array does not exist and
1928 * should not be accessed on 57711
1930 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
1933 /****************************************************************************
1934 * Shared Memory Region *
1935 ****************************************************************************/
1936 struct shmem_region { /* SharedMem Offset (size) */
1938 uint32_t validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
1939 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
1940 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
1942 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
1943 #define SHR_MEM_VALIDITY_MB 0x00200000
1944 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
1945 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
1946 /* One licensing bit should be set */
1947 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
1948 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
1949 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
1950 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
1952 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
1953 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
1954 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
1955 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
1956 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
1957 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
1959 struct shm_dev_info dev_info; /* 0x8 (0x438) */
1961 license_key_t drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
1963 /* FW information (for internal FW use) */
1964 uint32_t fw_info_fio_offset; /* 0x4a8 (0x4) */
1965 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
1967 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
1971 /* This is a variable length array */
1972 /* the number of function depends on the chip type */
1973 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1975 /* the number of function depends on the chip type */
1976 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1979 }; /* 57711 = 0x7E4 | 57712 = 0x734 */
1981 /****************************************************************************
1982 * Shared Memory 2 Region *
1983 ****************************************************************************/
1984 /* The fw_flr_ack is actually built in the following way: */
1986 /* 64 bit: VF ack */
1987 /* 8 bit: ios_dis_ack */
1988 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
1989 /* uint32_t. The fw must have the VF right after the PF since this is how it */
1990 /* access arrays(it expects always the VF to reside after the PF, and that */
1991 /* makes the calculation much easier for it. ) */
1992 /* In order to answer both limitations, and keep the struct small, the code */
1993 /* will abuse the structure defined here to achieve the actual partition */
1995 /****************************************************************************/
1999 uint32_t iov_dis_ack;
2004 uint32_t opgen_addr;
2005 struct fw_flr_ack ack;
2008 struct eee_remote_vals {
2013 /**** SUPPORT FOR SHMEM ARRRAYS ***
2014 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
2015 * define arrays with storage types smaller then unsigned dwords.
2016 * The macros below add generic support for SHMEM arrays with numeric elements
2017 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
2018 * array with individual bit-filed elements accessed using shifts and masks.
2022 /* eb is the bitwidth of a single element */
2023 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)
2024 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))
2026 /* the bit-position macro allows the used to flip the order of the arrays
2027 * elements on a per byte or word boundary.
2029 * example: an array with 8 entries each 4 bit wide. This array will fit into
2030 * a single dword. The diagrmas below show the array order of the nibbles.
2032 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
2035 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
2038 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
2041 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 |
2044 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
2047 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 |
2050 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \
2051 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
2052 (((i)%((fb)/(eb))) * (eb)))
2054 #define SHMEM_ARRAY_GET(a, i, eb, fb) \
2055 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \
2056 SHMEM_ARRAY_MASK(eb))
2058 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \
2060 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \
2061 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
2062 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \
2063 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
2067 /****START OF DCBX STRUCTURES DECLARATIONS****/
2068 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8
2069 #define DCBX_PRI_PG_BITWIDTH 4
2070 #define DCBX_PRI_PG_FBITS 8
2071 #define DCBX_PRI_PG_GET(a, i) \
2072 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
2073 #define DCBX_PRI_PG_SET(a, i, val) \
2074 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
2075 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8
2076 #define DCBX_BW_PG_BITWIDTH 8
2077 #define DCBX_PG_BW_GET(a, i) \
2078 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
2079 #define DCBX_PG_BW_SET(a, i, val) \
2080 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
2081 #define DCBX_STRICT_PRI_PG 15
2082 #define DCBX_MAX_APP_PROTOCOL 16
2083 #define DCBX_MAX_APP_LOCAL 32
2084 #define FCOE_APP_IDX 0
2085 #define ISCSI_APP_IDX 1
2086 #define PREDEFINED_APP_IDX_MAX 2
2089 /* Big/Little endian have the same representation. */
2090 struct dcbx_ets_feature {
2092 * For Admin MIB - is this feature supported by the
2093 * driver | For Local MIB - should this feature be enabled.
2096 uint32_t pg_bw_tbl[2];
2097 uint32_t pri_pg_tbl[1];
2100 /* Driver structure in LE */
2101 struct dcbx_pfc_feature {
2103 uint8_t pri_en_bitmap;
2104 #define DCBX_PFC_PRI_0 0x01
2105 #define DCBX_PFC_PRI_1 0x02
2106 #define DCBX_PFC_PRI_2 0x04
2107 #define DCBX_PFC_PRI_3 0x08
2108 #define DCBX_PFC_PRI_4 0x10
2109 #define DCBX_PFC_PRI_5 0x20
2110 #define DCBX_PFC_PRI_6 0x40
2111 #define DCBX_PFC_PRI_7 0x80
2115 #elif defined(__LITTLE_ENDIAN)
2119 uint8_t pri_en_bitmap;
2120 #define DCBX_PFC_PRI_0 0x01
2121 #define DCBX_PFC_PRI_1 0x02
2122 #define DCBX_PFC_PRI_2 0x04
2123 #define DCBX_PFC_PRI_3 0x08
2124 #define DCBX_PFC_PRI_4 0x10
2125 #define DCBX_PFC_PRI_5 0x20
2126 #define DCBX_PFC_PRI_6 0x40
2127 #define DCBX_PFC_PRI_7 0x80
2131 struct dcbx_app_priority_entry {
2135 uint8_t appBitfield;
2136 #define DCBX_APP_ENTRY_VALID 0x01
2137 #define DCBX_APP_ENTRY_SF_MASK 0x30
2138 #define DCBX_APP_ENTRY_SF_SHIFT 4
2139 #define DCBX_APP_SF_ETH_TYPE 0x10
2140 #define DCBX_APP_SF_PORT 0x20
2141 #elif defined(__LITTLE_ENDIAN)
2142 uint8_t appBitfield;
2143 #define DCBX_APP_ENTRY_VALID 0x01
2144 #define DCBX_APP_ENTRY_SF_MASK 0x30
2145 #define DCBX_APP_ENTRY_SF_SHIFT 4
2146 #define DCBX_APP_SF_ETH_TYPE 0x10
2147 #define DCBX_APP_SF_PORT 0x20
2154 /* FW structure in BE */
2155 struct dcbx_app_priority_feature {
2158 uint8_t default_pri;
2159 uint8_t tc_supported;
2161 #elif defined(__LITTLE_ENDIAN)
2163 uint8_t tc_supported;
2164 uint8_t default_pri;
2167 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
2170 /* FW structure in BE */
2171 struct dcbx_features {
2173 struct dcbx_ets_feature ets;
2175 struct dcbx_pfc_feature pfc;
2177 struct dcbx_app_priority_feature app;
2180 /* LLDP protocol parameters */
2181 /* FW structure in BE */
2182 struct lldp_params {
2184 uint8_t msg_fast_tx_interval;
2185 uint8_t msg_tx_hold;
2186 uint8_t msg_tx_interval;
2187 uint8_t admin_status;
2188 #define LLDP_TX_ONLY 0x01
2189 #define LLDP_RX_ONLY 0x02
2190 #define LLDP_TX_RX 0x03
2191 #define LLDP_DISABLED 0x04
2196 #elif defined(__LITTLE_ENDIAN)
2197 uint8_t admin_status;
2198 #define LLDP_TX_ONLY 0x01
2199 #define LLDP_RX_ONLY 0x02
2200 #define LLDP_TX_RX 0x03
2201 #define LLDP_DISABLED 0x04
2202 uint8_t msg_tx_interval;
2203 uint8_t msg_tx_hold;
2204 uint8_t msg_fast_tx_interval;
2210 #define REM_CHASSIS_ID_STAT_LEN 4
2211 #define REM_PORT_ID_STAT_LEN 4
2212 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
2213 uint32_t peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
2214 /* Holds remote Port ID TLV header, subtype and 9B of payload. */
2215 uint32_t peer_port_id[REM_PORT_ID_STAT_LEN];
2218 struct lldp_dcbx_stat {
2219 #define LOCAL_CHASSIS_ID_STAT_LEN 2
2220 #define LOCAL_PORT_ID_STAT_LEN 2
2221 /* Holds local Chassis ID 8B payload of constant subtype 4. */
2222 uint32_t local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
2223 /* Holds local Port ID 8B payload of constant subtype 3. */
2224 uint32_t local_port_id[LOCAL_PORT_ID_STAT_LEN];
2225 /* Number of DCBX frames transmitted. */
2226 uint32_t num_tx_dcbx_pkts;
2227 /* Number of DCBX frames received. */
2228 uint32_t num_rx_dcbx_pkts;
2231 /* ADMIN MIB - DCBX local machine default configuration. */
2232 struct lldp_admin_mib {
2233 uint32_t ver_cfg_flags;
2234 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
2235 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
2236 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
2237 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008
2238 #define DCBX_ETS_RECO_VALID 0x00000010
2239 #define DCBX_ETS_WILLING 0x00000020
2240 #define DCBX_PFC_WILLING 0x00000040
2241 #define DCBX_APP_WILLING 0x00000080
2242 #define DCBX_VERSION_CEE 0x00000100
2243 #define DCBX_VERSION_IEEE 0x00000200
2244 #define DCBX_DCBX_ENABLED 0x00000400
2245 #define DCBX_CEE_VERSION_MASK 0x0000f000
2246 #define DCBX_CEE_VERSION_SHIFT 12
2247 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
2248 #define DCBX_CEE_MAX_VERSION_SHIFT 16
2249 struct dcbx_features features;
2252 /* REMOTE MIB - remote machine DCBX configuration. */
2253 struct lldp_remote_mib {
2254 uint32_t prefix_seq_num;
2256 #define DCBX_ETS_TLV_RX 0x00000001
2257 #define DCBX_PFC_TLV_RX 0x00000002
2258 #define DCBX_APP_TLV_RX 0x00000004
2259 #define DCBX_ETS_RX_ERROR 0x00000010
2260 #define DCBX_PFC_RX_ERROR 0x00000020
2261 #define DCBX_APP_RX_ERROR 0x00000040
2262 #define DCBX_ETS_REM_WILLING 0x00000100
2263 #define DCBX_PFC_REM_WILLING 0x00000200
2264 #define DCBX_APP_REM_WILLING 0x00000400
2265 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
2266 #define DCBX_REMOTE_MIB_VALID 0x00002000
2267 struct dcbx_features features;
2268 uint32_t suffix_seq_num;
2271 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
2272 struct lldp_local_mib {
2273 uint32_t prefix_seq_num;
2274 /* Indicates if there is mismatch with negotiation results. */
2276 #define DCBX_LOCAL_ETS_ERROR 0x00000001
2277 #define DCBX_LOCAL_PFC_ERROR 0x00000002
2278 #define DCBX_LOCAL_APP_ERROR 0x00000004
2279 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010
2280 #define DCBX_LOCAL_APP_MISMATCH 0x00000020
2281 #define DCBX_REMOTE_MIB_ERROR 0x00000040
2282 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080
2283 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100
2284 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200
2285 struct dcbx_features features;
2286 uint32_t suffix_seq_num;
2289 struct lldp_local_mib_ext {
2290 uint32_t prefix_seq_num;
2291 /* APP TLV extension - 16 more entries for negotiation results*/
2292 struct dcbx_app_priority_entry app_pri_tbl_ext[DCBX_MAX_APP_PROTOCOL];
2293 uint32_t suffix_seq_num;
2295 /***END OF DCBX STRUCTURES DECLARATIONS***/
2297 /***********************************************************/
2299 /***********************************************************/
2300 #define SHMEM_LINK_CONFIG_SIZE 2
2302 uint32_t req_duplex;
2303 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff
2304 #define REQ_DUPLEX_PHY0_SHIFT 0
2305 #define REQ_DUPLEX_PHY1_MASK 0xffff0000
2306 #define REQ_DUPLEX_PHY1_SHIFT 16
2307 uint32_t req_flow_ctrl;
2308 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff
2309 #define REQ_FLOW_CTRL_PHY0_SHIFT 0
2310 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000
2311 #define REQ_FLOW_CTRL_PHY1_SHIFT 16
2312 uint32_t req_line_speed; /* Also determine AutoNeg */
2313 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff
2314 #define REQ_LINE_SPD_PHY0_SHIFT 0
2315 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000
2316 #define REQ_LINE_SPD_PHY1_SHIFT 16
2317 uint32_t speed_cap_mask[SHMEM_LINK_CONFIG_SIZE];
2318 uint32_t additional_config;
2319 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff
2320 #define REQ_FC_AUTO_ADV0_SHIFT 0
2321 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000
2323 #define LFA_LINK_FLAP_REASON_OFFSET 0
2324 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff
2325 #define LFA_LINK_DOWN 0x1
2326 #define LFA_LOOPBACK_ENABLED 0x2
2327 #define LFA_DUPLEX_MISMATCH 0x3
2328 #define LFA_MFW_IS_TOO_OLD 0x4
2329 #define LFA_LINK_SPEED_MISMATCH 0x5
2330 #define LFA_FLOW_CTRL_MISMATCH 0x6
2331 #define LFA_SPEED_CAP_MISMATCH 0x7
2332 #define LFA_DCC_LFA_DISABLED 0x8
2333 #define LFA_EEE_MISMATCH 0x9
2335 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8
2336 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
2338 #define LINK_FLAP_COUNT_OFFSET 16
2339 #define LINK_FLAP_COUNT_MASK 0x00ff0000
2341 #define LFA_FLAGS_MASK 0xff000000
2342 #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24)
2346 struct shmem2_region {
2348 uint32_t size; /* 0x0000 */
2350 uint32_t dcc_support; /* 0x0004 */
2351 #define SHMEM_DCC_SUPPORT_NONE 0x00000000
2352 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
2353 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
2354 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
2355 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
2356 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
2358 uint32_t ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */
2360 * For backwards compatibility, if the mf_cfg_addr does not exist
2361 * (the size filed is smaller than 0xc) the mf_cfg resides at the
2362 * end of struct shmem_region
2364 uint32_t mf_cfg_addr; /* 0x0010 */
2365 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000
2367 struct fw_flr_mb flr_mb; /* 0x0014 */
2368 uint32_t dcbx_lldp_params_offset; /* 0x0028 */
2369 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
2370 uint32_t dcbx_neg_res_offset; /* 0x002c */
2371 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000
2372 uint32_t dcbx_remote_mib_offset; /* 0x0030 */
2373 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
2375 * The other shmemX_base_addr holds the other path's shmem address
2376 * required for example in case of common phy init, or for path1 to know
2377 * the address of mcp debug trace which is located in offset from shmem
2380 uint32_t other_shmem_base_addr; /* 0x0034 */
2381 uint32_t other_shmem2_base_addr; /* 0x0038 */
2383 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
2384 * which were disabled/flred
2386 uint32_t mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */
2389 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
2392 uint32_t drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
2394 uint32_t dcbx_lldp_dcbx_stat_offset; /* 0x0064 */
2395 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
2398 * edebug_driver_if field is used to transfer messages between edebug
2399 * app to the driver through shmem2.
2402 * bits 0-2 - function number / instance of driver to perform request
2403 * bits 3-5 - op code / is_ack?
2406 uint32_t edebug_driver_if[2]; /* 0x0068 */
2407 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1
2408 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2
2409 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3
2411 uint32_t nvm_retain_bitmap_addr; /* 0x0070 */
2413 /* afex support of that driver */
2414 uint32_t afex_driver_support; /* 0x0074 */
2415 #define SHMEM_AFEX_VERSION_MASK 0x100f
2416 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001
2417 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000
2419 /* driver receives addr in scratchpad to which it should respond */
2420 uint32_t afex_scratchpad_addr_to_write[E2_FUNC_MAX];
2423 * generic params from MCP to driver (value depends on the msg sent
2426 uint32_t afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */
2427 uint32_t afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */
2429 uint32_t swim_base_addr; /* 0x0108 */
2430 uint32_t swim_funcs;
2431 uint32_t swim_main_cb;
2434 * bitmap notifying which VIF profiles stored in nvram are enabled by
2437 uint32_t afex_profiles_enabled[2];
2439 /* generic flags controlled by the driver */
2441 #define DRV_FLAGS_DCB_CONFIGURED 0x0
2442 #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1
2443 #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2
2445 #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \
2446 (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \
2447 (1 << DRV_FLAGS_DCB_MFW_CONFIGURED))
2449 #define DRV_FLAGS_P0_OFFSET 0
2450 #define DRV_FLAGS_P1_OFFSET 16
2451 #define DRV_FLAGS_GET_PORT_OFFSET(_port) ((0 == _port) ? \
2452 DRV_FLAGS_P0_OFFSET : \
2453 DRV_FLAGS_P1_OFFSET)
2455 #define DRV_FLAGS_GET_PORT_MASK(_port) (DRV_FLAGS_PORT_MASK << \
2456 DRV_FLAGS_GET_PORT_OFFSET(_port))
2458 #define DRV_FLAGS_FILED_BY_PORT(_field_bit, _port) (1 << ( \
2459 (_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port)))
2461 /* pointer to extended dev_info shared data copied from nvm image */
2462 uint32_t extended_dev_info_shared_addr;
2463 uint32_t ncsi_oem_data_addr;
2465 uint32_t sensor_data_addr;
2466 uint32_t buffer_block_addr;
2467 uint32_t sensor_data_req_update_interval;
2468 uint32_t temperature_in_half_celsius;
2469 uint32_t glob_struct_in_host;
2471 uint32_t dcbx_neg_res_ext_offset;
2472 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000
2474 uint32_t drv_capabilities_flag[E2_FUNC_MAX];
2475 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
2476 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002
2477 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004
2478 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008
2480 uint32_t extended_dev_info_shared_cfg_size;
2482 uint32_t dcbx_en[PORT_MAX];
2484 /* The offset points to the multi threaded meta structure */
2485 uint32_t multi_thread_data_offset;
2487 /* address of DMAable host address holding values from the drivers */
2488 uint32_t drv_info_host_addr_lo;
2489 uint32_t drv_info_host_addr_hi;
2491 /* general values written by the MFW (such as current version) */
2492 uint32_t drv_info_control;
2493 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff
2494 #define DRV_INFO_CONTROL_VER_SHIFT 0
2495 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00
2496 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8
2497 uint32_t ibft_host_addr; /* initialized by option ROM */
2499 struct eee_remote_vals eee_remote_vals[PORT_MAX];
2500 uint32_t pf_allocation[E2_FUNC_MAX];
2501 #define PF_ALLOACTION_MSIX_VECTORS_MASK 0x000000ff /* real value, as PCI config space can show only maximum of 64 vectors */
2502 #define PF_ALLOACTION_MSIX_VECTORS_SHIFT 0
2504 /* the status of EEE auto-negotiation
2505 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31.
2506 * bits 19:16 the supported modes for EEE.
2507 * bits 23:20 the speeds advertised for EEE.
2508 * bits 27:24 the speeds the Link partner advertised for EEE.
2509 * The supported/adv. modes in bits 27:19 originate from the
2510 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed).
2511 * bit 28 when 1'b1 EEE was requested.
2512 * bit 29 when 1'b1 tx lpi was requested.
2513 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted if
2515 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
2516 * value. When 1'b1 those bits contains a value times 16 microseconds.
2518 uint32_t eee_status[PORT_MAX];
2519 #define SHMEM_EEE_TIMER_MASK 0x0000ffff
2520 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000
2521 #define SHMEM_EEE_SUPPORTED_SHIFT 16
2522 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000
2523 #define SHMEM_EEE_100M_ADV (1<<0)
2524 #define SHMEM_EEE_1G_ADV (1U<<1)
2525 #define SHMEM_EEE_10G_ADV (1<<2)
2526 #define SHMEM_EEE_ADV_STATUS_SHIFT 20
2527 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000
2528 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24
2529 #define SHMEM_EEE_REQUESTED_BIT 0x10000000
2530 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000
2531 #define SHMEM_EEE_ACTIVE_BIT 0x40000000
2532 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000
2534 uint32_t sizeof_port_stats;
2536 /* Link Flap Avoidance */
2537 uint32_t lfa_host_addr[PORT_MAX];
2539 /* External PHY temperature in deg C. */
2540 uint32_t extphy_temps_in_celsius;
2541 #define EXTPHY1_TEMP_MASK 0x0000ffff
2542 #define EXTPHY1_TEMP_SHIFT 0
2544 uint32_t ocdata_info_addr; /* Offset 0x148 */
2545 uint32_t drv_func_info_addr; /* Offset 0x14C */
2546 uint32_t drv_func_info_size; /* Offset 0x150 */
2547 uint32_t link_attr_sync[PORT_MAX]; /* Offset 0x154 */
2548 #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001
2549 #define LINK_ATTR_84858 0x00000002
2550 #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00
2551 #define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8
2553 uint32_t link_change_count[PORT_MAX]; /* Offset 0x160-0x164 */
2558 uint32_t rx_stat_ifhcinoctets;
2559 uint32_t rx_stat_ifhcinbadoctets;
2560 uint32_t rx_stat_etherstatsfragments;
2561 uint32_t rx_stat_ifhcinucastpkts;
2562 uint32_t rx_stat_ifhcinmulticastpkts;
2563 uint32_t rx_stat_ifhcinbroadcastpkts;
2564 uint32_t rx_stat_dot3statsfcserrors;
2565 uint32_t rx_stat_dot3statsalignmenterrors;
2566 uint32_t rx_stat_dot3statscarriersenseerrors;
2567 uint32_t rx_stat_xonpauseframesreceived;
2568 uint32_t rx_stat_xoffpauseframesreceived;
2569 uint32_t rx_stat_maccontrolframesreceived;
2570 uint32_t rx_stat_xoffstateentered;
2571 uint32_t rx_stat_dot3statsframestoolong;
2572 uint32_t rx_stat_etherstatsjabbers;
2573 uint32_t rx_stat_etherstatsundersizepkts;
2574 uint32_t rx_stat_etherstatspkts64octets;
2575 uint32_t rx_stat_etherstatspkts65octetsto127octets;
2576 uint32_t rx_stat_etherstatspkts128octetsto255octets;
2577 uint32_t rx_stat_etherstatspkts256octetsto511octets;
2578 uint32_t rx_stat_etherstatspkts512octetsto1023octets;
2579 uint32_t rx_stat_etherstatspkts1024octetsto1522octets;
2580 uint32_t rx_stat_etherstatspktsover1522octets;
2582 uint32_t rx_stat_falsecarriererrors;
2584 uint32_t tx_stat_ifhcoutoctets;
2585 uint32_t tx_stat_ifhcoutbadoctets;
2586 uint32_t tx_stat_etherstatscollisions;
2587 uint32_t tx_stat_outxonsent;
2588 uint32_t tx_stat_outxoffsent;
2589 uint32_t tx_stat_flowcontroldone;
2590 uint32_t tx_stat_dot3statssinglecollisionframes;
2591 uint32_t tx_stat_dot3statsmultiplecollisionframes;
2592 uint32_t tx_stat_dot3statsdeferredtransmissions;
2593 uint32_t tx_stat_dot3statsexcessivecollisions;
2594 uint32_t tx_stat_dot3statslatecollisions;
2595 uint32_t tx_stat_ifhcoutucastpkts;
2596 uint32_t tx_stat_ifhcoutmulticastpkts;
2597 uint32_t tx_stat_ifhcoutbroadcastpkts;
2598 uint32_t tx_stat_etherstatspkts64octets;
2599 uint32_t tx_stat_etherstatspkts65octetsto127octets;
2600 uint32_t tx_stat_etherstatspkts128octetsto255octets;
2601 uint32_t tx_stat_etherstatspkts256octetsto511octets;
2602 uint32_t tx_stat_etherstatspkts512octetsto1023octets;
2603 uint32_t tx_stat_etherstatspkts1024octetsto1522octets;
2604 uint32_t tx_stat_etherstatspktsover1522octets;
2605 uint32_t tx_stat_dot3statsinternalmactransmiterrors;
2609 struct bmac1_stats {
2610 uint32_t tx_stat_gtpkt_lo;
2611 uint32_t tx_stat_gtpkt_hi;
2612 uint32_t tx_stat_gtxpf_lo;
2613 uint32_t tx_stat_gtxpf_hi;
2614 uint32_t tx_stat_gtfcs_lo;
2615 uint32_t tx_stat_gtfcs_hi;
2616 uint32_t tx_stat_gtmca_lo;
2617 uint32_t tx_stat_gtmca_hi;
2618 uint32_t tx_stat_gtbca_lo;
2619 uint32_t tx_stat_gtbca_hi;
2620 uint32_t tx_stat_gtfrg_lo;
2621 uint32_t tx_stat_gtfrg_hi;
2622 uint32_t tx_stat_gtovr_lo;
2623 uint32_t tx_stat_gtovr_hi;
2624 uint32_t tx_stat_gt64_lo;
2625 uint32_t tx_stat_gt64_hi;
2626 uint32_t tx_stat_gt127_lo;
2627 uint32_t tx_stat_gt127_hi;
2628 uint32_t tx_stat_gt255_lo;
2629 uint32_t tx_stat_gt255_hi;
2630 uint32_t tx_stat_gt511_lo;
2631 uint32_t tx_stat_gt511_hi;
2632 uint32_t tx_stat_gt1023_lo;
2633 uint32_t tx_stat_gt1023_hi;
2634 uint32_t tx_stat_gt1518_lo;
2635 uint32_t tx_stat_gt1518_hi;
2636 uint32_t tx_stat_gt2047_lo;
2637 uint32_t tx_stat_gt2047_hi;
2638 uint32_t tx_stat_gt4095_lo;
2639 uint32_t tx_stat_gt4095_hi;
2640 uint32_t tx_stat_gt9216_lo;
2641 uint32_t tx_stat_gt9216_hi;
2642 uint32_t tx_stat_gt16383_lo;
2643 uint32_t tx_stat_gt16383_hi;
2644 uint32_t tx_stat_gtmax_lo;
2645 uint32_t tx_stat_gtmax_hi;
2646 uint32_t tx_stat_gtufl_lo;
2647 uint32_t tx_stat_gtufl_hi;
2648 uint32_t tx_stat_gterr_lo;
2649 uint32_t tx_stat_gterr_hi;
2650 uint32_t tx_stat_gtbyt_lo;
2651 uint32_t tx_stat_gtbyt_hi;
2653 uint32_t rx_stat_gr64_lo;
2654 uint32_t rx_stat_gr64_hi;
2655 uint32_t rx_stat_gr127_lo;
2656 uint32_t rx_stat_gr127_hi;
2657 uint32_t rx_stat_gr255_lo;
2658 uint32_t rx_stat_gr255_hi;
2659 uint32_t rx_stat_gr511_lo;
2660 uint32_t rx_stat_gr511_hi;
2661 uint32_t rx_stat_gr1023_lo;
2662 uint32_t rx_stat_gr1023_hi;
2663 uint32_t rx_stat_gr1518_lo;
2664 uint32_t rx_stat_gr1518_hi;
2665 uint32_t rx_stat_gr2047_lo;
2666 uint32_t rx_stat_gr2047_hi;
2667 uint32_t rx_stat_gr4095_lo;
2668 uint32_t rx_stat_gr4095_hi;
2669 uint32_t rx_stat_gr9216_lo;
2670 uint32_t rx_stat_gr9216_hi;
2671 uint32_t rx_stat_gr16383_lo;
2672 uint32_t rx_stat_gr16383_hi;
2673 uint32_t rx_stat_grmax_lo;
2674 uint32_t rx_stat_grmax_hi;
2675 uint32_t rx_stat_grpkt_lo;
2676 uint32_t rx_stat_grpkt_hi;
2677 uint32_t rx_stat_grfcs_lo;
2678 uint32_t rx_stat_grfcs_hi;
2679 uint32_t rx_stat_grmca_lo;
2680 uint32_t rx_stat_grmca_hi;
2681 uint32_t rx_stat_grbca_lo;
2682 uint32_t rx_stat_grbca_hi;
2683 uint32_t rx_stat_grxcf_lo;
2684 uint32_t rx_stat_grxcf_hi;
2685 uint32_t rx_stat_grxpf_lo;
2686 uint32_t rx_stat_grxpf_hi;
2687 uint32_t rx_stat_grxuo_lo;
2688 uint32_t rx_stat_grxuo_hi;
2689 uint32_t rx_stat_grjbr_lo;
2690 uint32_t rx_stat_grjbr_hi;
2691 uint32_t rx_stat_grovr_lo;
2692 uint32_t rx_stat_grovr_hi;
2693 uint32_t rx_stat_grflr_lo;
2694 uint32_t rx_stat_grflr_hi;
2695 uint32_t rx_stat_grmeg_lo;
2696 uint32_t rx_stat_grmeg_hi;
2697 uint32_t rx_stat_grmeb_lo;
2698 uint32_t rx_stat_grmeb_hi;
2699 uint32_t rx_stat_grbyt_lo;
2700 uint32_t rx_stat_grbyt_hi;
2701 uint32_t rx_stat_grund_lo;
2702 uint32_t rx_stat_grund_hi;
2703 uint32_t rx_stat_grfrg_lo;
2704 uint32_t rx_stat_grfrg_hi;
2705 uint32_t rx_stat_grerb_lo;
2706 uint32_t rx_stat_grerb_hi;
2707 uint32_t rx_stat_grfre_lo;
2708 uint32_t rx_stat_grfre_hi;
2709 uint32_t rx_stat_gripj_lo;
2710 uint32_t rx_stat_gripj_hi;
2713 struct bmac2_stats {
2714 uint32_t tx_stat_gtpk_lo; /* gtpok */
2715 uint32_t tx_stat_gtpk_hi; /* gtpok */
2716 uint32_t tx_stat_gtxpf_lo; /* gtpf */
2717 uint32_t tx_stat_gtxpf_hi; /* gtpf */
2718 uint32_t tx_stat_gtpp_lo; /* NEW BMAC2 */
2719 uint32_t tx_stat_gtpp_hi; /* NEW BMAC2 */
2720 uint32_t tx_stat_gtfcs_lo;
2721 uint32_t tx_stat_gtfcs_hi;
2722 uint32_t tx_stat_gtuca_lo; /* NEW BMAC2 */
2723 uint32_t tx_stat_gtuca_hi; /* NEW BMAC2 */
2724 uint32_t tx_stat_gtmca_lo;
2725 uint32_t tx_stat_gtmca_hi;
2726 uint32_t tx_stat_gtbca_lo;
2727 uint32_t tx_stat_gtbca_hi;
2728 uint32_t tx_stat_gtovr_lo;
2729 uint32_t tx_stat_gtovr_hi;
2730 uint32_t tx_stat_gtfrg_lo;
2731 uint32_t tx_stat_gtfrg_hi;
2732 uint32_t tx_stat_gtpkt1_lo; /* gtpkt */
2733 uint32_t tx_stat_gtpkt1_hi; /* gtpkt */
2734 uint32_t tx_stat_gt64_lo;
2735 uint32_t tx_stat_gt64_hi;
2736 uint32_t tx_stat_gt127_lo;
2737 uint32_t tx_stat_gt127_hi;
2738 uint32_t tx_stat_gt255_lo;
2739 uint32_t tx_stat_gt255_hi;
2740 uint32_t tx_stat_gt511_lo;
2741 uint32_t tx_stat_gt511_hi;
2742 uint32_t tx_stat_gt1023_lo;
2743 uint32_t tx_stat_gt1023_hi;
2744 uint32_t tx_stat_gt1518_lo;
2745 uint32_t tx_stat_gt1518_hi;
2746 uint32_t tx_stat_gt2047_lo;
2747 uint32_t tx_stat_gt2047_hi;
2748 uint32_t tx_stat_gt4095_lo;
2749 uint32_t tx_stat_gt4095_hi;
2750 uint32_t tx_stat_gt9216_lo;
2751 uint32_t tx_stat_gt9216_hi;
2752 uint32_t tx_stat_gt16383_lo;
2753 uint32_t tx_stat_gt16383_hi;
2754 uint32_t tx_stat_gtmax_lo;
2755 uint32_t tx_stat_gtmax_hi;
2756 uint32_t tx_stat_gtufl_lo;
2757 uint32_t tx_stat_gtufl_hi;
2758 uint32_t tx_stat_gterr_lo;
2759 uint32_t tx_stat_gterr_hi;
2760 uint32_t tx_stat_gtbyt_lo;
2761 uint32_t tx_stat_gtbyt_hi;
2763 uint32_t rx_stat_gr64_lo;
2764 uint32_t rx_stat_gr64_hi;
2765 uint32_t rx_stat_gr127_lo;
2766 uint32_t rx_stat_gr127_hi;
2767 uint32_t rx_stat_gr255_lo;
2768 uint32_t rx_stat_gr255_hi;
2769 uint32_t rx_stat_gr511_lo;
2770 uint32_t rx_stat_gr511_hi;
2771 uint32_t rx_stat_gr1023_lo;
2772 uint32_t rx_stat_gr1023_hi;
2773 uint32_t rx_stat_gr1518_lo;
2774 uint32_t rx_stat_gr1518_hi;
2775 uint32_t rx_stat_gr2047_lo;
2776 uint32_t rx_stat_gr2047_hi;
2777 uint32_t rx_stat_gr4095_lo;
2778 uint32_t rx_stat_gr4095_hi;
2779 uint32_t rx_stat_gr9216_lo;
2780 uint32_t rx_stat_gr9216_hi;
2781 uint32_t rx_stat_gr16383_lo;
2782 uint32_t rx_stat_gr16383_hi;
2783 uint32_t rx_stat_grmax_lo;
2784 uint32_t rx_stat_grmax_hi;
2785 uint32_t rx_stat_grpkt_lo;
2786 uint32_t rx_stat_grpkt_hi;
2787 uint32_t rx_stat_grfcs_lo;
2788 uint32_t rx_stat_grfcs_hi;
2789 uint32_t rx_stat_gruca_lo;
2790 uint32_t rx_stat_gruca_hi;
2791 uint32_t rx_stat_grmca_lo;
2792 uint32_t rx_stat_grmca_hi;
2793 uint32_t rx_stat_grbca_lo;
2794 uint32_t rx_stat_grbca_hi;
2795 uint32_t rx_stat_grxpf_lo; /* grpf */
2796 uint32_t rx_stat_grxpf_hi; /* grpf */
2797 uint32_t rx_stat_grpp_lo;
2798 uint32_t rx_stat_grpp_hi;
2799 uint32_t rx_stat_grxuo_lo; /* gruo */
2800 uint32_t rx_stat_grxuo_hi; /* gruo */
2801 uint32_t rx_stat_grjbr_lo;
2802 uint32_t rx_stat_grjbr_hi;
2803 uint32_t rx_stat_grovr_lo;
2804 uint32_t rx_stat_grovr_hi;
2805 uint32_t rx_stat_grxcf_lo; /* grcf */
2806 uint32_t rx_stat_grxcf_hi; /* grcf */
2807 uint32_t rx_stat_grflr_lo;
2808 uint32_t rx_stat_grflr_hi;
2809 uint32_t rx_stat_grpok_lo;
2810 uint32_t rx_stat_grpok_hi;
2811 uint32_t rx_stat_grmeg_lo;
2812 uint32_t rx_stat_grmeg_hi;
2813 uint32_t rx_stat_grmeb_lo;
2814 uint32_t rx_stat_grmeb_hi;
2815 uint32_t rx_stat_grbyt_lo;
2816 uint32_t rx_stat_grbyt_hi;
2817 uint32_t rx_stat_grund_lo;
2818 uint32_t rx_stat_grund_hi;
2819 uint32_t rx_stat_grfrg_lo;
2820 uint32_t rx_stat_grfrg_hi;
2821 uint32_t rx_stat_grerb_lo; /* grerrbyt */
2822 uint32_t rx_stat_grerb_hi; /* grerrbyt */
2823 uint32_t rx_stat_grfre_lo; /* grfrerr */
2824 uint32_t rx_stat_grfre_hi; /* grfrerr */
2825 uint32_t rx_stat_gripj_lo;
2826 uint32_t rx_stat_gripj_hi;
2829 struct mstat_stats {
2831 /* OTE MSTAT on E3 has a bug where this register's contents are
2832 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp
2834 uint32_t tx_gtxpok_lo;
2835 uint32_t tx_gtxpok_hi;
2836 uint32_t tx_gtxpf_lo;
2837 uint32_t tx_gtxpf_hi;
2838 uint32_t tx_gtxpp_lo;
2839 uint32_t tx_gtxpp_hi;
2840 uint32_t tx_gtfcs_lo;
2841 uint32_t tx_gtfcs_hi;
2842 uint32_t tx_gtuca_lo;
2843 uint32_t tx_gtuca_hi;
2844 uint32_t tx_gtmca_lo;
2845 uint32_t tx_gtmca_hi;
2846 uint32_t tx_gtgca_lo;
2847 uint32_t tx_gtgca_hi;
2848 uint32_t tx_gtpkt_lo;
2849 uint32_t tx_gtpkt_hi;
2850 uint32_t tx_gt64_lo;
2851 uint32_t tx_gt64_hi;
2852 uint32_t tx_gt127_lo;
2853 uint32_t tx_gt127_hi;
2854 uint32_t tx_gt255_lo;
2855 uint32_t tx_gt255_hi;
2856 uint32_t tx_gt511_lo;
2857 uint32_t tx_gt511_hi;
2858 uint32_t tx_gt1023_lo;
2859 uint32_t tx_gt1023_hi;
2860 uint32_t tx_gt1518_lo;
2861 uint32_t tx_gt1518_hi;
2862 uint32_t tx_gt2047_lo;
2863 uint32_t tx_gt2047_hi;
2864 uint32_t tx_gt4095_lo;
2865 uint32_t tx_gt4095_hi;
2866 uint32_t tx_gt9216_lo;
2867 uint32_t tx_gt9216_hi;
2868 uint32_t tx_gt16383_lo;
2869 uint32_t tx_gt16383_hi;
2870 uint32_t tx_gtufl_lo;
2871 uint32_t tx_gtufl_hi;
2872 uint32_t tx_gterr_lo;
2873 uint32_t tx_gterr_hi;
2874 uint32_t tx_gtbyt_lo;
2875 uint32_t tx_gtbyt_hi;
2876 uint32_t tx_collisions_lo;
2877 uint32_t tx_collisions_hi;
2878 uint32_t tx_singlecollision_lo;
2879 uint32_t tx_singlecollision_hi;
2880 uint32_t tx_multiplecollisions_lo;
2881 uint32_t tx_multiplecollisions_hi;
2882 uint32_t tx_deferred_lo;
2883 uint32_t tx_deferred_hi;
2884 uint32_t tx_excessivecollisions_lo;
2885 uint32_t tx_excessivecollisions_hi;
2886 uint32_t tx_latecollisions_lo;
2887 uint32_t tx_latecollisions_hi;
2891 uint32_t rx_gr64_lo;
2892 uint32_t rx_gr64_hi;
2893 uint32_t rx_gr127_lo;
2894 uint32_t rx_gr127_hi;
2895 uint32_t rx_gr255_lo;
2896 uint32_t rx_gr255_hi;
2897 uint32_t rx_gr511_lo;
2898 uint32_t rx_gr511_hi;
2899 uint32_t rx_gr1023_lo;
2900 uint32_t rx_gr1023_hi;
2901 uint32_t rx_gr1518_lo;
2902 uint32_t rx_gr1518_hi;
2903 uint32_t rx_gr2047_lo;
2904 uint32_t rx_gr2047_hi;
2905 uint32_t rx_gr4095_lo;
2906 uint32_t rx_gr4095_hi;
2907 uint32_t rx_gr9216_lo;
2908 uint32_t rx_gr9216_hi;
2909 uint32_t rx_gr16383_lo;
2910 uint32_t rx_gr16383_hi;
2911 uint32_t rx_grpkt_lo;
2912 uint32_t rx_grpkt_hi;
2913 uint32_t rx_grfcs_lo;
2914 uint32_t rx_grfcs_hi;
2915 uint32_t rx_gruca_lo;
2916 uint32_t rx_gruca_hi;
2917 uint32_t rx_grmca_lo;
2918 uint32_t rx_grmca_hi;
2919 uint32_t rx_grbca_lo;
2920 uint32_t rx_grbca_hi;
2921 uint32_t rx_grxpf_lo;
2922 uint32_t rx_grxpf_hi;
2923 uint32_t rx_grxpp_lo;
2924 uint32_t rx_grxpp_hi;
2925 uint32_t rx_grxuo_lo;
2926 uint32_t rx_grxuo_hi;
2927 uint32_t rx_grovr_lo;
2928 uint32_t rx_grovr_hi;
2929 uint32_t rx_grxcf_lo;
2930 uint32_t rx_grxcf_hi;
2931 uint32_t rx_grflr_lo;
2932 uint32_t rx_grflr_hi;
2933 uint32_t rx_grpok_lo;
2934 uint32_t rx_grpok_hi;
2935 uint32_t rx_grbyt_lo;
2936 uint32_t rx_grbyt_hi;
2937 uint32_t rx_grund_lo;
2938 uint32_t rx_grund_hi;
2939 uint32_t rx_grfrg_lo;
2940 uint32_t rx_grfrg_hi;
2941 uint32_t rx_grerb_lo;
2942 uint32_t rx_grerb_hi;
2943 uint32_t rx_grfre_lo;
2944 uint32_t rx_grfre_hi;
2946 uint32_t rx_alignmenterrors_lo;
2947 uint32_t rx_alignmenterrors_hi;
2948 uint32_t rx_falsecarrier_lo;
2949 uint32_t rx_falsecarrier_hi;
2950 uint32_t rx_llfcmsgcnt_lo;
2951 uint32_t rx_llfcmsgcnt_hi;
2956 struct emac_stats emac_stats;
2957 struct bmac1_stats bmac1_stats;
2958 struct bmac2_stats bmac2_stats;
2959 struct mstat_stats mstat_stats;
2965 uint32_t rx_stat_ifhcinbadoctets_hi;
2966 uint32_t rx_stat_ifhcinbadoctets_lo;
2968 /* out_bad_octets */
2969 uint32_t tx_stat_ifhcoutbadoctets_hi;
2970 uint32_t tx_stat_ifhcoutbadoctets_lo;
2972 /* crc_receive_errors */
2973 uint32_t rx_stat_dot3statsfcserrors_hi;
2974 uint32_t rx_stat_dot3statsfcserrors_lo;
2975 /* alignment_errors */
2976 uint32_t rx_stat_dot3statsalignmenterrors_hi;
2977 uint32_t rx_stat_dot3statsalignmenterrors_lo;
2978 /* carrier_sense_errors */
2979 uint32_t rx_stat_dot3statscarriersenseerrors_hi;
2980 uint32_t rx_stat_dot3statscarriersenseerrors_lo;
2981 /* false_carrier_detections */
2982 uint32_t rx_stat_falsecarriererrors_hi;
2983 uint32_t rx_stat_falsecarriererrors_lo;
2985 /* runt_packets_received */
2986 uint32_t rx_stat_etherstatsundersizepkts_hi;
2987 uint32_t rx_stat_etherstatsundersizepkts_lo;
2988 /* jabber_packets_received */
2989 uint32_t rx_stat_dot3statsframestoolong_hi;
2990 uint32_t rx_stat_dot3statsframestoolong_lo;
2992 /* error_runt_packets_received */
2993 uint32_t rx_stat_etherstatsfragments_hi;
2994 uint32_t rx_stat_etherstatsfragments_lo;
2995 /* error_jabber_packets_received */
2996 uint32_t rx_stat_etherstatsjabbers_hi;
2997 uint32_t rx_stat_etherstatsjabbers_lo;
2999 /* control_frames_received */
3000 uint32_t rx_stat_maccontrolframesreceived_hi;
3001 uint32_t rx_stat_maccontrolframesreceived_lo;
3002 uint32_t rx_stat_mac_xpf_hi;
3003 uint32_t rx_stat_mac_xpf_lo;
3004 uint32_t rx_stat_mac_xcf_hi;
3005 uint32_t rx_stat_mac_xcf_lo;
3007 /* xoff_state_entered */
3008 uint32_t rx_stat_xoffstateentered_hi;
3009 uint32_t rx_stat_xoffstateentered_lo;
3010 /* pause_xon_frames_received */
3011 uint32_t rx_stat_xonpauseframesreceived_hi;
3012 uint32_t rx_stat_xonpauseframesreceived_lo;
3013 /* pause_xoff_frames_received */
3014 uint32_t rx_stat_xoffpauseframesreceived_hi;
3015 uint32_t rx_stat_xoffpauseframesreceived_lo;
3016 /* pause_xon_frames_transmitted */
3017 uint32_t tx_stat_outxonsent_hi;
3018 uint32_t tx_stat_outxonsent_lo;
3019 /* pause_xoff_frames_transmitted */
3020 uint32_t tx_stat_outxoffsent_hi;
3021 uint32_t tx_stat_outxoffsent_lo;
3022 /* flow_control_done */
3023 uint32_t tx_stat_flowcontroldone_hi;
3024 uint32_t tx_stat_flowcontroldone_lo;
3026 /* ether_stats_collisions */
3027 uint32_t tx_stat_etherstatscollisions_hi;
3028 uint32_t tx_stat_etherstatscollisions_lo;
3029 /* single_collision_transmit_frames */
3030 uint32_t tx_stat_dot3statssinglecollisionframes_hi;
3031 uint32_t tx_stat_dot3statssinglecollisionframes_lo;
3032 /* multiple_collision_transmit_frames */
3033 uint32_t tx_stat_dot3statsmultiplecollisionframes_hi;
3034 uint32_t tx_stat_dot3statsmultiplecollisionframes_lo;
3035 /* deferred_transmissions */
3036 uint32_t tx_stat_dot3statsdeferredtransmissions_hi;
3037 uint32_t tx_stat_dot3statsdeferredtransmissions_lo;
3038 /* excessive_collision_frames */
3039 uint32_t tx_stat_dot3statsexcessivecollisions_hi;
3040 uint32_t tx_stat_dot3statsexcessivecollisions_lo;
3041 /* late_collision_frames */
3042 uint32_t tx_stat_dot3statslatecollisions_hi;
3043 uint32_t tx_stat_dot3statslatecollisions_lo;
3045 /* frames_transmitted_64_bytes */
3046 uint32_t tx_stat_etherstatspkts64octets_hi;
3047 uint32_t tx_stat_etherstatspkts64octets_lo;
3048 /* frames_transmitted_65_127_bytes */
3049 uint32_t tx_stat_etherstatspkts65octetsto127octets_hi;
3050 uint32_t tx_stat_etherstatspkts65octetsto127octets_lo;
3051 /* frames_transmitted_128_255_bytes */
3052 uint32_t tx_stat_etherstatspkts128octetsto255octets_hi;
3053 uint32_t tx_stat_etherstatspkts128octetsto255octets_lo;
3054 /* frames_transmitted_256_511_bytes */
3055 uint32_t tx_stat_etherstatspkts256octetsto511octets_hi;
3056 uint32_t tx_stat_etherstatspkts256octetsto511octets_lo;
3057 /* frames_transmitted_512_1023_bytes */
3058 uint32_t tx_stat_etherstatspkts512octetsto1023octets_hi;
3059 uint32_t tx_stat_etherstatspkts512octetsto1023octets_lo;
3060 /* frames_transmitted_1024_1522_bytes */
3061 uint32_t tx_stat_etherstatspkts1024octetsto1522octets_hi;
3062 uint32_t tx_stat_etherstatspkts1024octetsto1522octets_lo;
3063 /* frames_transmitted_1523_9022_bytes */
3064 uint32_t tx_stat_etherstatspktsover1522octets_hi;
3065 uint32_t tx_stat_etherstatspktsover1522octets_lo;
3066 uint32_t tx_stat_mac_2047_hi;
3067 uint32_t tx_stat_mac_2047_lo;
3068 uint32_t tx_stat_mac_4095_hi;
3069 uint32_t tx_stat_mac_4095_lo;
3070 uint32_t tx_stat_mac_9216_hi;
3071 uint32_t tx_stat_mac_9216_lo;
3072 uint32_t tx_stat_mac_16383_hi;
3073 uint32_t tx_stat_mac_16383_lo;
3075 /* internal_mac_transmit_errors */
3076 uint32_t tx_stat_dot3statsinternalmactransmiterrors_hi;
3077 uint32_t tx_stat_dot3statsinternalmactransmiterrors_lo;
3079 /* if_out_discards */
3080 uint32_t tx_stat_mac_ufl_hi;
3081 uint32_t tx_stat_mac_ufl_lo;
3085 #define MAC_STX_IDX_MAX 2
3087 struct host_port_stats {
3088 uint32_t host_port_stats_counter;
3090 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
3092 uint32_t brb_drop_hi;
3093 uint32_t brb_drop_lo;
3095 uint32_t not_used; /* obsolete as of MFW 7.2.1 */
3097 uint32_t pfc_frames_tx_hi;
3098 uint32_t pfc_frames_tx_lo;
3099 uint32_t pfc_frames_rx_hi;
3100 uint32_t pfc_frames_rx_lo;
3102 uint32_t eee_lpi_count_hi;
3103 uint32_t eee_lpi_count_lo;
3107 struct host_func_stats {
3108 uint32_t host_func_stats_start;
3110 uint32_t total_bytes_received_hi;
3111 uint32_t total_bytes_received_lo;
3113 uint32_t total_bytes_transmitted_hi;
3114 uint32_t total_bytes_transmitted_lo;
3116 uint32_t total_unicast_packets_received_hi;
3117 uint32_t total_unicast_packets_received_lo;
3119 uint32_t total_multicast_packets_received_hi;
3120 uint32_t total_multicast_packets_received_lo;
3122 uint32_t total_broadcast_packets_received_hi;
3123 uint32_t total_broadcast_packets_received_lo;
3125 uint32_t total_unicast_packets_transmitted_hi;
3126 uint32_t total_unicast_packets_transmitted_lo;
3128 uint32_t total_multicast_packets_transmitted_hi;
3129 uint32_t total_multicast_packets_transmitted_lo;
3131 uint32_t total_broadcast_packets_transmitted_hi;
3132 uint32_t total_broadcast_packets_transmitted_lo;
3134 uint32_t valid_bytes_received_hi;
3135 uint32_t valid_bytes_received_lo;
3137 uint32_t host_func_stats_end;
3140 /* VIC definitions */
3141 #define VICSTATST_UIF_INDEX 2
3144 * stats collected for afex.
3145 * NOTE: structure is exactly as expected to be received by the switch.
3146 * order must remain exactly as is unless protocol changes !
3149 uint32_t tx_unicast_frames_hi;
3150 uint32_t tx_unicast_frames_lo;
3151 uint32_t tx_unicast_bytes_hi;
3152 uint32_t tx_unicast_bytes_lo;
3153 uint32_t tx_multicast_frames_hi;
3154 uint32_t tx_multicast_frames_lo;
3155 uint32_t tx_multicast_bytes_hi;
3156 uint32_t tx_multicast_bytes_lo;
3157 uint32_t tx_broadcast_frames_hi;
3158 uint32_t tx_broadcast_frames_lo;
3159 uint32_t tx_broadcast_bytes_hi;
3160 uint32_t tx_broadcast_bytes_lo;
3161 uint32_t tx_frames_discarded_hi;
3162 uint32_t tx_frames_discarded_lo;
3163 uint32_t tx_frames_dropped_hi;
3164 uint32_t tx_frames_dropped_lo;
3166 uint32_t rx_unicast_frames_hi;
3167 uint32_t rx_unicast_frames_lo;
3168 uint32_t rx_unicast_bytes_hi;
3169 uint32_t rx_unicast_bytes_lo;
3170 uint32_t rx_multicast_frames_hi;
3171 uint32_t rx_multicast_frames_lo;
3172 uint32_t rx_multicast_bytes_hi;
3173 uint32_t rx_multicast_bytes_lo;
3174 uint32_t rx_broadcast_frames_hi;
3175 uint32_t rx_broadcast_frames_lo;
3176 uint32_t rx_broadcast_bytes_hi;
3177 uint32_t rx_broadcast_bytes_lo;
3178 uint32_t rx_frames_discarded_hi;
3179 uint32_t rx_frames_discarded_lo;
3180 uint32_t rx_frames_dropped_hi;
3181 uint32_t rx_frames_dropped_lo;
3184 /* To maintain backward compatibility between FW and drivers, new elements */
3185 /* should be added to the end of the structure. */
3187 /* Per Port Statistics */
3189 uint32_t size; /* size of this structure (i.e. sizeof(port_info)) */
3190 uint32_t enabled; /* 0 =Disabled, 1= Enabled */
3191 uint32_t link_speed; /* multiplier of 100Mb */
3192 uint32_t wol_support; /* WoL Support (i.e. Non-Zero if WOL supported ) */
3193 uint32_t flow_control; /* 802.3X Flow Ctrl. 0=off 1=RX 2=TX 3=RX&TX.*/
3194 uint32_t flex10; /* Flex10 mode enabled. non zero = yes */
3195 uint32_t rx_drops; /* RX Discards. Counters roll over, never reset */
3196 uint32_t rx_errors; /* RX Errors. Physical Port Stats L95, All PFs and NC-SI.
3197 This is flagged by Consumer as an error. */
3198 uint32_t rx_uncast_lo; /* RX Unicast Packets. Free running counters: */
3199 uint32_t rx_uncast_hi; /* RX Unicast Packets. Free running counters: */
3200 uint32_t rx_mcast_lo; /* RX Multicast Packets */
3201 uint32_t rx_mcast_hi; /* RX Multicast Packets */
3202 uint32_t rx_bcast_lo; /* RX Broadcast Packets */
3203 uint32_t rx_bcast_hi; /* RX Broadcast Packets */
3204 uint32_t tx_uncast_lo; /* TX Unicast Packets */
3205 uint32_t tx_uncast_hi; /* TX Unicast Packets */
3206 uint32_t tx_mcast_lo; /* TX Multicast Packets */
3207 uint32_t tx_mcast_hi; /* TX Multicast Packets */
3208 uint32_t tx_bcast_lo; /* TX Broadcast Packets */
3209 uint32_t tx_bcast_hi; /* TX Broadcast Packets */
3210 uint32_t tx_errors; /* TX Errors */
3211 uint32_t tx_discards; /* TX Discards */
3212 uint32_t rx_frames_lo; /* RX Frames received */
3213 uint32_t rx_frames_hi; /* RX Frames received */
3214 uint32_t rx_bytes_lo; /* RX Bytes received */
3215 uint32_t rx_bytes_hi; /* RX Bytes received */
3216 uint32_t tx_frames_lo; /* TX Frames sent */
3217 uint32_t tx_frames_hi; /* TX Frames sent */
3218 uint32_t tx_bytes_lo; /* TX Bytes sent */
3219 uint32_t tx_bytes_hi; /* TX Bytes sent */
3220 uint32_t link_status; /* Port P Link Status. 1:0 bit for port enabled.
3221 1:1 bit for link good,
3222 2:1 Set if link changed between last poll. */
3223 uint32_t tx_pfc_frames_lo; /* PFC Frames sent. */
3224 uint32_t tx_pfc_frames_hi; /* PFC Frames sent. */
3225 uint32_t rx_pfc_frames_lo; /* PFC Frames Received. */
3226 uint32_t rx_pfc_frames_hi; /* PFC Frames Received. */
3230 #define BNX2X_5710_FW_MAJOR_VERSION 7
3231 #define BNX2X_5710_FW_MINOR_VERSION 2
3232 #define BNX2X_5710_FW_REVISION_VERSION 51
3233 #define BNX2X_5710_FW_ENGINEERING_VERSION 0
3234 #define BNX2X_5710_FW_COMPILE_FLAGS 1
3238 * attention bits $$KEEP_ENDIANNESS$$
3240 struct atten_sp_status_block
3242 uint32_t attn_bits /* 16 bit of attention signal lines */;
3243 uint32_t attn_bits_ack /* 16 bit of attention signal ack */;
3244 uint8_t status_block_id /* status block id */;
3245 uint8_t reserved0 /* resreved for padding */;
3246 uint16_t attn_bits_index /* attention bits running index */;
3247 uint32_t reserved1 /* resreved for padding */;
3252 * The eth aggregative context of Cstorm
3254 struct cstorm_eth_ag_context
3256 uint32_t __reserved0[10];
3261 * dmae command structure
3266 #define DMAE_COMMAND_SRC (0x1<<0) /* BitField opcode Whether the source is the PCIe or the GRC. 0- The source is the PCIe 1- The source is the GRC. */
3267 #define DMAE_COMMAND_SRC_SHIFT 0
3268 #define DMAE_COMMAND_DST (0x3<<1) /* BitField opcode The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */
3269 #define DMAE_COMMAND_DST_SHIFT 1
3270 #define DMAE_COMMAND_C_DST (0x1<<3) /* BitField opcode The destination of the completion: 0-PCIe 1-GRC */
3271 #define DMAE_COMMAND_C_DST_SHIFT 3
3272 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) /* BitField opcode Whether to write a completion word to the completion destination: 0-Do not write a completion word 1-Write the completion word */
3273 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
3274 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) /* BitField opcode Whether to write a CRC word to the completion destination 0-Do not write a CRC word 1-Write a CRC word */
3275 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
3276 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) /* BitField opcode The CRC word should be taken from the DMAE GRC space from address 9+X, where X is the value in these bits. */
3277 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
3278 #define DMAE_COMMAND_ENDIANITY (0x3<<9) /* BitField opcode swapping mode. */
3279 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
3280 #define DMAE_COMMAND_PORT (0x1<<11) /* BitField opcode Which network port ID to present to the PCI request interface */
3281 #define DMAE_COMMAND_PORT_SHIFT 11
3282 #define DMAE_COMMAND_CRC_RESET (0x1<<12) /* BitField opcode reset crc result */
3283 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
3284 #define DMAE_COMMAND_SRC_RESET (0x1<<13) /* BitField opcode reset source address in next go */
3285 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
3286 #define DMAE_COMMAND_DST_RESET (0x1<<14) /* BitField opcode reset dest address in next go */
3287 #define DMAE_COMMAND_DST_RESET_SHIFT 14
3288 #define DMAE_COMMAND_E1HVN (0x3<<15) /* BitField opcode vnic number E2 and onwards source vnic */
3289 #define DMAE_COMMAND_E1HVN_SHIFT 15
3290 #define DMAE_COMMAND_DST_VN (0x3<<17) /* BitField opcode E2 and onwards dest vnic */
3291 #define DMAE_COMMAND_DST_VN_SHIFT 17
3292 #define DMAE_COMMAND_C_FUNC (0x1<<19) /* BitField opcode E2 and onwards which function gets the completion src_vn(e1hvn)-0 dst_vn-1 */
3293 #define DMAE_COMMAND_C_FUNC_SHIFT 19
3294 #define DMAE_COMMAND_ERR_POLICY (0x3<<20) /* BitField opcode E2 and onwards what to do when theres a completion and a PCI error regular-0 error indication-1 no completion-2 */
3295 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20
3296 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22) /* BitField opcode */
3297 #define DMAE_COMMAND_RESERVED0_SHIFT 22
3298 uint32_t src_addr_lo /* source address low/grc address */;
3299 uint32_t src_addr_hi /* source address hi */;
3300 uint32_t dst_addr_lo /* dest address low/grc address */;
3301 uint32_t dst_addr_hi /* dest address hi */;
3302 #if defined(__BIG_ENDIAN)
3303 uint16_t opcode_iov;
3304 #define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */
3305 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
3306 #define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */
3307 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
3308 #define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */
3309 #define DMAE_COMMAND_RESERVED1_SHIFT 7
3310 #define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */
3311 #define DMAE_COMMAND_DST_VFID_SHIFT 8
3312 #define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */
3313 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
3314 #define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */
3315 #define DMAE_COMMAND_RESERVED2_SHIFT 15
3316 uint16_t len /* copy length */;
3317 #elif defined(__LITTLE_ENDIAN)
3318 uint16_t len /* copy length */;
3319 uint16_t opcode_iov;
3320 #define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */
3321 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
3322 #define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */
3323 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
3324 #define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */
3325 #define DMAE_COMMAND_RESERVED1_SHIFT 7
3326 #define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */
3327 #define DMAE_COMMAND_DST_VFID_SHIFT 8
3328 #define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */
3329 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
3330 #define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */
3331 #define DMAE_COMMAND_RESERVED2_SHIFT 15
3333 uint32_t comp_addr_lo /* completion address low/grc address */;
3334 uint32_t comp_addr_hi /* completion address hi */;
3335 uint32_t comp_val /* value to write to completion address */;
3336 uint32_t crc32 /* crc32 result */;
3337 uint32_t crc32_c /* crc32_c result */;
3338 #if defined(__BIG_ENDIAN)
3339 uint16_t crc16_c /* crc16_c result */;
3340 uint16_t crc16 /* crc16 result */;
3341 #elif defined(__LITTLE_ENDIAN)
3342 uint16_t crc16 /* crc16 result */;
3343 uint16_t crc16_c /* crc16_c result */;
3345 #if defined(__BIG_ENDIAN)
3347 uint16_t crc_t10 /* crc_t10 result */;
3348 #elif defined(__LITTLE_ENDIAN)
3349 uint16_t crc_t10 /* crc_t10 result */;
3352 #if defined(__BIG_ENDIAN)
3353 uint16_t xsum8 /* checksum8 result */;
3354 uint16_t xsum16 /* checksum16 result */;
3355 #elif defined(__LITTLE_ENDIAN)
3356 uint16_t xsum16 /* checksum16 result */;
3357 uint16_t xsum8 /* checksum8 result */;
3363 * common data for all protocols
3368 #define DOORBELL_HDR_RX (0x1<<0) /* BitField header 1 for rx doorbell, 0 for tx doorbell */
3369 #define DOORBELL_HDR_RX_SHIFT 0
3370 #define DOORBELL_HDR_DB_TYPE (0x1<<1) /* BitField header 0 for normal doorbell, 1 for advertise wnd doorbell */
3371 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
3372 #define DOORBELL_HDR_DPM_SIZE (0x3<<2) /* BitField header rdma tx only: DPM transaction size specifier (64/128/256/512 bytes) */
3373 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
3374 #define DOORBELL_HDR_CONN_TYPE (0xF<<4) /* BitField header connection type */
3375 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
3381 struct eth_tx_doorbell
3383 #if defined(__BIG_ENDIAN)
3384 uint16_t npackets /* number of data bytes that were added in the doorbell */;
3386 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */
3387 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3388 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */
3389 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
3390 #define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */
3391 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
3392 struct doorbell_hdr hdr;
3393 #elif defined(__LITTLE_ENDIAN)
3394 struct doorbell_hdr hdr;
3396 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */
3397 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3398 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */
3399 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
3400 #define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */
3401 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
3402 uint16_t npackets /* number of data bytes that were added in the doorbell */;
3408 * 3 lines. status block $$KEEP_ENDIANNESS$$
3410 struct hc_status_block_e1x
3412 uint16_t index_values[HC_SB_MAX_INDICES_E1X] /* indices reported by cstorm */;
3413 uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */;
3420 struct host_hc_status_block_e1x
3422 struct hc_status_block_e1x sb /* fast path indices */;
3427 * 3 lines. status block $$KEEP_ENDIANNESS$$
3429 struct hc_status_block_e2
3431 uint16_t index_values[HC_SB_MAX_INDICES_E2] /* indices reported by cstorm */;
3432 uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */;
3433 uint32_t reserved[11];
3439 struct host_hc_status_block_e2
3441 struct hc_status_block_e2 sb /* fast path indices */;
3446 * 5 lines. slow-path status block $$KEEP_ENDIANNESS$$
3448 struct hc_sp_status_block
3450 uint16_t index_values[HC_SP_SB_MAX_INDICES] /* indices reported by cstorm */;
3451 uint16_t running_index /* Status Block running index */;
3459 struct host_sp_status_block
3461 struct atten_sp_status_block atten_status_block /* attention bits section */;
3462 struct hc_sp_status_block sp_sb /* slow path indices */;
3467 * IGU driver acknowledgment register
3469 union igu_ack_register
3472 #if defined(__BIG_ENDIAN)
3473 uint16_t sb_id_and_flags;
3474 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */
3475 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3476 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */
3477 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3478 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */
3479 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3480 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */
3481 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3482 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */
3483 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3484 uint16_t status_block_index /* status block index acknowledgement */;
3485 #elif defined(__LITTLE_ENDIAN)
3486 uint16_t status_block_index /* status block index acknowledgement */;
3487 uint16_t sb_id_and_flags;
3488 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */
3489 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3490 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */
3491 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3492 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */
3493 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3494 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */
3495 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3496 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */
3497 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3505 * IGU driver acknowledgement register
3507 struct igu_backward_compatible
3509 uint32_t sb_id_and_flags;
3510 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) /* BitField sb_id_and_flags */
3511 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
3512 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) /* BitField sb_id_and_flags */
3513 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
3514 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */
3515 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
3516 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) /* BitField sb_id_and_flags if set, acknowledges status block index */
3517 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
3518 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */
3519 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
3520 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) /* BitField sb_id_and_flags */
3521 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
3522 uint32_t reserved_2;
3527 * IGU driver acknowledgement register
3531 uint32_t sb_id_and_flags;
3532 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) /* BitField sb_id_and_flags */
3533 #define IGU_REGULAR_SB_INDEX_SHIFT 0
3534 #define IGU_REGULAR_RESERVED0 (0x1<<20) /* BitField sb_id_and_flags */
3535 #define IGU_REGULAR_RESERVED0_SHIFT 20
3536 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 21-23 (use enum igu_seg_access) */
3537 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
3538 #define IGU_REGULAR_BUPDATE (0x1<<24) /* BitField sb_id_and_flags */
3539 #define IGU_REGULAR_BUPDATE_SHIFT 24
3540 #define IGU_REGULAR_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop (use enum igu_int_cmd) */
3541 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
3542 #define IGU_REGULAR_RESERVED_1 (0x1<<27) /* BitField sb_id_and_flags */
3543 #define IGU_REGULAR_RESERVED_1_SHIFT 27
3544 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) /* BitField sb_id_and_flags */
3545 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
3546 #define IGU_REGULAR_CLEANUP_SET (0x1<<30) /* BitField sb_id_and_flags */
3547 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
3548 #define IGU_REGULAR_BCLEANUP (0x1<<31) /* BitField sb_id_and_flags */
3549 #define IGU_REGULAR_BCLEANUP_SHIFT 31
3550 uint32_t reserved_2;
3554 * IGU driver acknowledgement register
3556 union igu_consprod_reg
3558 struct igu_regular regular;
3559 struct igu_backward_compatible backward_compatible;
3564 * Igu control commands
3568 IGU_CTRL_CMD_TYPE_RD,
3569 IGU_CTRL_CMD_TYPE_WR,
3574 * Control register for the IGU command register
3579 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0) /* BitField ctrl_data */
3580 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
3581 #define IGU_CTRL_REG_FID (0x7F<<12) /* BitField ctrl_data */
3582 #define IGU_CTRL_REG_FID_SHIFT 12
3583 #define IGU_CTRL_REG_RESERVED (0x1<<19) /* BitField ctrl_data */
3584 #define IGU_CTRL_REG_RESERVED_SHIFT 19
3585 #define IGU_CTRL_REG_TYPE (0x1<<20) /* BitField ctrl_data (use enum igu_ctrl_cmd) */
3586 #define IGU_CTRL_REG_TYPE_SHIFT 20
3587 #define IGU_CTRL_REG_UNUSED (0x7FF<<21) /* BitField ctrl_data */
3588 #define IGU_CTRL_REG_UNUSED_SHIFT 21
3593 * Igu interrupt command
3609 IGU_SEG_ACCESS_NORM,
3611 IGU_SEG_ACCESS_ATTN,
3612 MAX_IGU_SEG_ACCESS};
3616 * Parser parsing flags field
3618 struct parsing_flags
3621 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) /* BitField flagscontext flags 0=non-unicast, 1=unicast (use enum prs_flags_eth_addr_type) */
3622 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
3623 #define PARSING_FLAGS_VLAN (0x1<<1) /* BitField flagscontext flags 0 or 1 */
3624 #define PARSING_FLAGS_VLAN_SHIFT 1
3625 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) /* BitField flagscontext flags 0 or 1 */
3626 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
3627 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) /* BitField flagscontext flags 0=un-known, 1=Ipv4, 2=Ipv6,3=LLC SNAP un-known. LLC SNAP here refers only to LLC/SNAP packets that do not have Ipv4 or Ipv6 above them. Ipv4 and Ipv6 indications are even if they are over LLC/SNAP and not directly over Ethernet (use enum prs_flags_over_eth) */
3628 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
3629 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5) /* BitField flagscontext flags 0=no IP options / extension headers. 1=IP options / extension header exist */
3630 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
3631 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) /* BitField flagscontext flags 0=non-fragmented, 1=fragmented */
3632 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
3633 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) /* BitField flagscontext flags 0=un-known, 1=TCP, 2=UDP (use enum prs_flags_over_ip) */
3634 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
3635 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) /* BitField flagscontext flags 0=packet with data, 1=pure-ACK (use enum prs_flags_ack_type) */
3636 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
3637 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) /* BitField flagscontext flags 0=no TCP options. 1=TCP options */
3638 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
3639 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) /* BitField flagscontext flags According to the TCP header options parsing */
3640 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
3641 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) /* BitField flagscontext flags connection match in searcher indication */
3642 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
3643 #define PARSING_FLAGS_LLC_SNAP (0x1<<13) /* BitField flagscontext flags LLC SNAP indication */
3644 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
3645 #define PARSING_FLAGS_RESERVED0 (0x3<<14) /* BitField flagscontext flags */
3646 #define PARSING_FLAGS_RESERVED0_SHIFT 14
3651 * Parsing flags for TCP ACK type
3653 enum prs_flags_ack_type
3655 PRS_FLAG_PUREACK_PIGGY,
3656 PRS_FLAG_PUREACK_PURE,
3657 MAX_PRS_FLAGS_ACK_TYPE};
3661 * Parsing flags for Ethernet address type
3663 enum prs_flags_eth_addr_type
3665 PRS_FLAG_ETHTYPE_NON_UNICAST,
3666 PRS_FLAG_ETHTYPE_UNICAST,
3667 MAX_PRS_FLAGS_ETH_ADDR_TYPE};
3671 * Parsing flags for over-ethernet protocol
3673 enum prs_flags_over_eth
3675 PRS_FLAG_OVERETH_UNKNOWN,
3676 PRS_FLAG_OVERETH_IPV4,
3677 PRS_FLAG_OVERETH_IPV6,
3678 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN,
3679 MAX_PRS_FLAGS_OVER_ETH};
3683 * Parsing flags for over-IP protocol
3685 enum prs_flags_over_ip
3687 PRS_FLAG_OVERIP_UNKNOWN,
3688 PRS_FLAG_OVERIP_TCP,
3689 PRS_FLAG_OVERIP_UDP,
3690 MAX_PRS_FLAGS_OVER_IP};
3694 * SDM operation gen command (generate aggregative interrupt)
3699 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0) /* BitField commandcomp_param and comp_type thread ID/aggr interrupt number/counter depending on the completion type */
3700 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
3701 #define SDM_OP_GEN_COMP_TYPE (0x7<<5) /* BitField commandcomp_param and comp_type Direct messages to CM / PCI switch are not supported in operation_gen completion */
3702 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5
3703 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) /* BitField commandcomp_param and comp_type bit index in aggregated interrupt vector */
3704 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
3705 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) /* BitField commandcomp_param and comp_type */
3706 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
3707 #define SDM_OP_GEN_RESERVED (0x7FFF<<17) /* BitField commandcomp_param and comp_type */
3708 #define SDM_OP_GEN_RESERVED_SHIFT 17
3713 * Timers connection context
3715 struct timers_block_context
3717 uint32_t __reserved_0 /* data of client 0 of the timers block*/;
3718 uint32_t __reserved_1 /* data of client 1 of the timers block*/;
3719 uint32_t __reserved_2 /* data of client 2 of the timers block*/;
3721 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) /* BitField flagscontext flags number of active timers running */
3722 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
3723 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) /* BitField flagscontext flags flag: is connection valid (should be set by driver to 1 in toe/iscsi connections) */
3724 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
3725 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) /* BitField flagscontext flags */
3726 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
3731 * The eth aggregative context of Tstorm
3733 struct tstorm_eth_ag_context
3735 uint32_t __reserved0[14];
3740 * The eth aggregative context of Ustorm
3742 struct ustorm_eth_ag_context
3744 uint32_t __reserved0;
3745 #if defined(__BIG_ENDIAN)
3746 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;
3747 uint8_t __reserved2;
3748 uint16_t __reserved1;
3749 #elif defined(__LITTLE_ENDIAN)
3750 uint16_t __reserved1;
3751 uint8_t __reserved2;
3752 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;
3754 uint32_t __reserved3[6];
3759 * The eth aggregative context of Xstorm
3761 struct xstorm_eth_ag_context
3764 #if defined(__BIG_ENDIAN)
3765 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */;
3768 #elif defined(__LITTLE_ENDIAN)
3771 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */;
3773 uint32_t reserved3[30];
3778 * doorbell message sent to the chip
3782 #if defined(__BIG_ENDIAN)
3783 uint16_t zero_fill2 /* driver must zero this field! */;
3784 uint8_t zero_fill1 /* driver must zero this field! */;
3785 struct doorbell_hdr header;
3786 #elif defined(__LITTLE_ENDIAN)
3787 struct doorbell_hdr header;
3788 uint8_t zero_fill1 /* driver must zero this field! */;
3789 uint16_t zero_fill2 /* driver must zero this field! */;
3795 * doorbell message sent to the chip
3797 struct doorbell_set_prod
3799 #if defined(__BIG_ENDIAN)
3800 uint16_t prod /* Producer index to be set */;
3801 uint8_t zero_fill1 /* driver must zero this field! */;
3802 struct doorbell_hdr header;
3803 #elif defined(__LITTLE_ENDIAN)
3804 struct doorbell_hdr header;
3805 uint8_t zero_fill1 /* driver must zero this field! */;
3806 uint16_t prod /* Producer index to be set */;
3813 uint32_t lo /* low word for reg-pair */;
3814 uint32_t hi /* high word for reg-pair */;
3818 struct regpair_native
3820 uint32_t lo /* low word for reg-pair */;
3821 uint32_t hi /* high word for reg-pair */;
3826 * Classify rule opcodes in E2/E3
3830 CLASSIFY_RULE_OPCODE_MAC /* Add/remove a MAC address */,
3831 CLASSIFY_RULE_OPCODE_VLAN /* Add/remove a VLAN */,
3832 CLASSIFY_RULE_OPCODE_PAIR /* Add/remove a MAC-VLAN pair */,
3837 * Classify rule types in E2/E3
3839 enum classify_rule_action_type
3841 CLASSIFY_RULE_REMOVE,
3843 MAX_CLASSIFY_RULE_ACTION_TYPE};
3847 * client init ramrod data $$KEEP_ENDIANNESS$$
3849 struct client_init_general_data
3851 uint8_t client_id /* client_id */;
3852 uint8_t statistics_counter_id /* statistics counter id */;
3853 uint8_t statistics_en_flg /* statistics en flg */;
3854 uint8_t is_fcoe_flg /* is this an fcoe connection. (1 bit is used) */;
3855 uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */;
3856 uint8_t sp_client_id /* the slow path rings client Id. */;
3857 uint16_t mtu /* Host MTU from client config */;
3858 uint8_t statistics_zero_flg /* if set FW will reset the statistic counter of this client */;
3859 uint8_t func_id /* PCI function ID (0-71) */;
3860 uint8_t cos /* The connection cos, if applicable */;
3861 uint8_t traffic_type;
3867 * client init rx data $$KEEP_ENDIANNESS$$
3869 struct client_init_rx_data
3872 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) /* BitField tpa_entpa_enable tpa enable flg ipv4 */
3873 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
3874 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) /* BitField tpa_entpa_enable tpa enable flg ipv6 */
3875 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
3876 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) /* BitField tpa_entpa_enable tpa mode (LRO or GRO) (use enum tpa_mode) */
3877 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
3878 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) /* BitField tpa_entpa_enable */
3879 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3
3880 uint8_t vmqueue_mode_en_flg /* If set, working in VMQueue mode (always consume one sge) */;
3881 uint8_t extra_data_over_sgl_en_flg /* if set, put over sgl data from end of input message */;
3882 uint8_t cache_line_alignment_log_size /* The log size of cache line alignment in bytes. Must be a power of 2. */;
3883 uint8_t enable_dynamic_hc /* If set, dynamic HC is enabled */;
3884 uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */;
3885 uint8_t client_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this client rx producers */;
3886 uint8_t drop_ip_cs_err_flg /* If set, this client drops packets with IP checksum error */;
3887 uint8_t drop_tcp_cs_err_flg /* If set, this client drops packets with TCP checksum error */;
3888 uint8_t drop_ttl0_flg /* If set, this client drops packets with TTL=0 */;
3889 uint8_t drop_udp_cs_err_flg /* If set, this client drops packets with UDP checksum error */;
3890 uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client */;
3891 uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client */;
3892 uint8_t status_block_id /* rx status block id */;
3893 uint8_t rx_sb_index_number /* status block indices */;
3894 uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */;
3895 uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */;
3896 uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */;
3897 uint16_t max_bytes_on_bd /* Maximum bytes that can be placed on a BD. The BD allocated size should include 2 more bytes (ip alignment) and alignment size (in case the address is not aligned) */;
3898 uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */;
3899 uint8_t approx_mcast_engine_id /* In Everest2, if is_approx_mcast is set, this field specified which approximate multicast engine is associate with this client */;
3900 uint8_t rss_engine_id /* In Everest2, if rss_mode is set, this field specified which RSS engine is associate with this client */;
3901 struct regpair bd_page_base /* BD page base address at the host */;
3902 struct regpair sge_page_base /* SGE page base address at the host */;
3903 struct regpair cqe_page_base /* Completion queue base address */;
3904 uint8_t is_leading_rss;
3905 uint8_t is_approx_mcast;
3906 uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */;
3908 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) /* BitField staterx filters state drop all unicast packets */
3909 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
3910 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) /* BitField staterx filters state accept all unicast packets (subject to vlan) */
3911 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
3912 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField staterx filters state accept all unmatched unicast packets (subject to vlan) */
3913 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3914 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) /* BitField staterx filters state drop all multicast packets */
3915 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
3916 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) /* BitField staterx filters state accept all multicast packets (subject to vlan) */
3917 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
3918 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) /* BitField staterx filters state accept all broadcast packets (subject to vlan) */
3919 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
3920 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) /* BitField staterx filters state accept packets matched only by MAC (without checking vlan) */
3921 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
3922 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) /* BitField staterx filters state */
3923 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
3924 uint16_t cqe_pause_thr_low /* number of remaining cqes under which, we send pause message */;
3925 uint16_t cqe_pause_thr_high /* number of remaining cqes above which, we send un-pause message */;
3926 uint16_t bd_pause_thr_low /* number of remaining bds under which, we send pause message */;
3927 uint16_t bd_pause_thr_high /* number of remaining bds above which, we send un-pause message */;
3928 uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */;
3929 uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */;
3930 uint16_t rx_cos_mask /* the bits that will be set on pfc/ safc paket with will be genratet when this ring is full. for regular flow control set this to 1 */;
3931 uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */;
3932 uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */;
3933 uint32_t reserved6[2];
3937 * client init tx data $$KEEP_ENDIANNESS$$
3939 struct client_init_tx_data
3941 uint8_t enforce_security_flg /* if set, security checks will be made for this connection */;
3942 uint8_t tx_status_block_id /* the number of status block to update */;
3943 uint8_t tx_sb_index_number /* the index to use inside the status block */;
3944 uint8_t tss_leading_client_id /* client ID of the leading TSS client, for TX classification source knock out */;
3945 uint8_t tx_switching_flg /* if set, tx switching will be done to packets on this connection */;
3946 uint8_t anti_spoofing_flg /* if set, anti spoofing check will be done to packets on this connection */;
3947 uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */;
3948 struct regpair tx_bd_page_base /* BD page base address at the host for TxBdCons */;
3950 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) /* BitField statetx filters state accept all unicast packets (subject to vlan) */
3951 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
3952 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) /* BitField statetx filters state accept all multicast packets (subject to vlan) */
3953 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
3954 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) /* BitField statetx filters state accept all broadcast packets (subject to vlan) */
3955 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
3956 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) /* BitField statetx filters state accept packets matched only by MAC (without checking vlan) */
3957 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
3958 #define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) /* BitField statetx filters state */
3959 #define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4
3960 uint8_t default_vlan_flg /* is default vlan valid for this client. */;
3961 uint8_t force_default_pri_flg /* if set, force default priority */;
3962 uint8_t tunnel_lso_inc_ip_id /* In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header */;
3963 uint8_t refuse_outband_vlan_flg /* if set, the FW will not add outband vlan on packet (even if will exist on BD). */;
3964 uint8_t tunnel_non_lso_pcsum_location /* In case of non-Lso encapsulated packets with L4 checksum offload, the pseudo checksum location - on packet or on BD. */;
3965 uint8_t tunnel_non_lso_outer_ip_csum_location /* In case of non-Lso encapsulated packets with outer L3 ip checksum offload, the pseudo checksum location - on packet or on BD. */;
3969 * client init ramrod data $$KEEP_ENDIANNESS$$
3971 struct client_init_ramrod_data
3973 struct client_init_general_data general /* client init general data */;
3974 struct client_init_rx_data rx /* client init rx data */;
3975 struct client_init_tx_data tx /* client init tx data */;
3980 * client update ramrod data $$KEEP_ENDIANNESS$$
3982 struct client_update_ramrod_data
3984 uint8_t client_id /* the client to update */;
3985 uint8_t func_id /* PCI function ID this client belongs to (0-71) */;
3986 uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client, will be change according to change flag */;
3987 uint8_t inner_vlan_removal_change_flg /* If set, inner VLAN removal flag will be set according to the enable flag */;
3988 uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client, will be change according to change flag */;
3989 uint8_t outer_vlan_removal_change_flg /* If set, outer VLAN removal flag will be set according to the enable flag */;
3990 uint8_t anti_spoofing_enable_flg /* If set, anti spoofing is enabled for this client, will be change according to change flag */;
3991 uint8_t anti_spoofing_change_flg /* If set, anti spoofing flag will be set according to anti spoofing flag */;
3992 uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */;
3993 uint8_t activate_change_flg /* If set, activate_flg will be checked */;
3994 uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */;
3995 uint8_t default_vlan_enable_flg;
3996 uint8_t default_vlan_change_flg;
3997 uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */;
3998 uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */;
3999 uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */;
4000 uint8_t silent_vlan_change_flg;
4001 uint8_t refuse_outband_vlan_flg /* If set, the FW will not add outband vlan on packet (even if will exist on BD). */;
4002 uint8_t refuse_outband_vlan_change_flg /* If set, refuse_outband_vlan_flg will be updated. */;
4003 uint8_t tx_switching_flg /* If set, tx switching will be done to packets on this connection. */;
4004 uint8_t tx_switching_change_flg /* If set, tx_switching_flg will be updated. */;
4006 uint32_t echo /* echo value to be sent to driver on event ring */;
4011 * The eth storm context of Cstorm
4013 struct cstorm_eth_st_context
4015 uint32_t __reserved0[4];
4019 struct double_regpair
4021 uint32_t regpair0_lo /* low word for reg-pair0 */;
4022 uint32_t regpair0_hi /* high word for reg-pair0 */;
4023 uint32_t regpair1_lo /* low word for reg-pair1 */;
4024 uint32_t regpair1_hi /* high word for reg-pair1 */;
4029 * Ethernet address types used in ethernet tx BDs
4042 * $$KEEP_ENDIANNESS$$
4044 struct eth_classify_cmd_header
4046 uint8_t cmd_general_data;
4047 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */
4048 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
4049 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */
4050 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
4051 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) /* BitField cmd_general_data command opcode for MAC/VLAN/PAIR (use enum classify_rule) */
4052 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
4053 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) /* BitField cmd_general_data (use enum classify_rule_action_type) */
4054 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
4055 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) /* BitField cmd_general_data */
4056 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
4057 uint8_t func_id /* the function id */;
4064 * header for eth classification config ramrod $$KEEP_ENDIANNESS$$
4066 struct eth_classify_header
4068 uint8_t rule_cnt /* number of rules in classification config ramrod */;
4071 uint32_t echo /* echo value to be sent to driver on event ring */;
4076 * Command for adding/removing a MAC classification rule $$KEEP_ENDIANNESS$$
4078 struct eth_classify_mac_cmd
4080 struct eth_classify_cmd_header header;
4091 * Command for adding/removing a MAC-VLAN pair classification rule $$KEEP_ENDIANNESS$$
4093 struct eth_classify_pair_cmd
4095 struct eth_classify_cmd_header header;
4106 * Command for adding/removing a VLAN classification rule $$KEEP_ENDIANNESS$$
4108 struct eth_classify_vlan_cmd
4110 struct eth_classify_cmd_header header;
4118 * union for eth classification rule $$KEEP_ENDIANNESS$$
4120 union eth_classify_rule_cmd
4122 struct eth_classify_mac_cmd mac;
4123 struct eth_classify_vlan_cmd vlan;
4124 struct eth_classify_pair_cmd pair;
4128 * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$
4130 struct eth_classify_rules_ramrod_data
4132 struct eth_classify_header header;
4133 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
4138 * The data contain client ID need to the ramrod $$KEEP_ENDIANNESS$$
4140 struct eth_common_ramrod_data
4142 uint32_t client_id /* id of this client. (5 bits are used) */;
4148 * The eth storm context of Ustorm
4150 struct ustorm_eth_st_context
4152 uint32_t reserved0[52];
4156 * The eth storm context of Tstorm
4158 struct tstorm_eth_st_context
4160 uint32_t __reserved0[28];
4164 * The eth storm context of Xstorm
4166 struct xstorm_eth_st_context
4168 uint32_t reserved0[60];
4172 * Ethernet connection context
4176 struct ustorm_eth_st_context ustorm_st_context /* Ustorm storm context */;
4177 struct tstorm_eth_st_context tstorm_st_context /* Tstorm storm context */;
4178 struct xstorm_eth_ag_context xstorm_ag_context /* Xstorm aggregative context */;
4179 struct tstorm_eth_ag_context tstorm_ag_context /* Tstorm aggregative context */;
4180 struct cstorm_eth_ag_context cstorm_ag_context /* Cstorm aggregative context */;
4181 struct ustorm_eth_ag_context ustorm_ag_context /* Ustorm aggregative context */;
4182 struct timers_block_context timers_context /* Timers block context */;
4183 struct xstorm_eth_st_context xstorm_st_context /* Xstorm storm context */;
4184 struct cstorm_eth_st_context cstorm_st_context /* Cstorm storm context */;
4189 * union for sgl and raw data.
4191 union eth_sgl_or_raw_data
4193 uint16_t sgl[8] /* Scatter-gather list of SGEs used by this packet. This list includes the indices of the SGEs. */;
4194 uint32_t raw_data[4] /* raw data from Tstorm to the driver. */;
4198 * eth FP end aggregation CQE parameters struct $$KEEP_ENDIANNESS$$
4200 struct eth_end_agg_rx_cqe
4202 uint8_t type_error_flags;
4203 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */
4204 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
4205 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */
4206 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
4207 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) /* BitField type_error_flags */
4208 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
4210 uint8_t queue_index /* The aggregation queue index of this packet */;
4212 uint32_t timestamp_delta /* timestamp delta between first packet to last packet in aggregation */;
4213 uint16_t num_of_coalesced_segs /* Num of coalesced segments. */;
4214 uint16_t pkt_len /* Packet length */;
4215 uint8_t pure_ack_count /* Number of pure acks coalesced. */;
4218 union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */;
4219 uint32_t reserved5[8];
4224 * regular eth FP CQE parameters struct $$KEEP_ENDIANNESS$$
4226 struct eth_fast_path_rx_cqe
4228 uint8_t type_error_flags;
4229 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */
4230 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
4231 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */
4232 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
4233 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) /* BitField type_error_flags Physical layer errors */
4234 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
4235 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) /* BitField type_error_flags IP checksum error */
4236 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
4237 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) /* BitField type_error_flags TCP/UDP checksum error */
4238 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
4239 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) /* BitField type_error_flags */
4240 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
4241 uint8_t status_flags;
4242 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) /* BitField status_flags (use enum eth_rss_hash_type) */
4243 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
4244 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) /* BitField status_flags RSS hashing on/off */
4245 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
4246 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) /* BitField status_flags if set to 1, this is a broadcast packet */
4247 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
4248 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) /* BitField status_flags if set to 1, the MAC address was matched in the tstorm CAM search */
4249 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
4250 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) /* BitField status_flags IP checksum validation was not performed (if packet is not IPv4) */
4251 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
4252 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) /* BitField status_flags TCP/UDP checksum validation was not performed (if packet is not TCP/UDP or IPv6 extheaders exist) */
4253 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
4254 uint8_t queue_index /* The aggregation queue index of this packet */;
4255 uint8_t placement_offset /* Placement offset from the start of the BD, in bytes */;
4256 uint32_t rss_hash_result /* RSS toeplitz hash result */;
4257 uint16_t vlan_tag /* Ethernet VLAN tag field */;
4258 uint16_t pkt_len_or_gro_seg_len /* Packet length (for non-TPA CQE) or GRO Segment Length (for TPA in GRO Mode) otherwise 0 */;
4259 uint16_t len_on_bd /* Number of bytes placed on the BD */;
4260 struct parsing_flags pars_flags;
4261 union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */;
4262 uint32_t reserved1[8];
4267 * Command for setting classification flags for a client $$KEEP_ENDIANNESS$$
4269 struct eth_filter_rules_cmd
4271 uint8_t cmd_general_data;
4272 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */
4273 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
4274 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */
4275 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
4276 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) /* BitField cmd_general_data */
4277 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
4278 uint8_t func_id /* the function id */;
4279 uint8_t client_id /* the client id */;
4282 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) /* BitField state drop all unicast packets */
4283 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
4284 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) /* BitField state accept all unicast packets (subject to vlan) */
4285 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
4286 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField state accept all unmatched unicast packets */
4287 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
4288 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) /* BitField state drop all multicast packets */
4289 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
4290 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) /* BitField state accept all multicast packets (subject to vlan) */
4291 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
4292 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) /* BitField state accept all broadcast packets (subject to vlan) */
4293 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
4294 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) /* BitField state accept packets matched only by MAC (without checking vlan) */
4295 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
4296 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) /* BitField state */
4297 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
4299 struct regpair reserved4;
4304 * parameters for eth classification filters ramrod $$KEEP_ENDIANNESS$$
4306 struct eth_filter_rules_ramrod_data
4308 struct eth_classify_header header;
4309 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
4314 * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$
4316 struct eth_general_rules_ramrod_data
4318 struct eth_classify_header header;
4319 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
4324 * The data for Halt ramrod
4326 struct eth_halt_ramrod_data
4328 uint32_t client_id /* id of this client. (5 bits are used) */;
4334 * destination and source mac address.
4336 struct eth_mac_addresses
4338 #if defined(__BIG_ENDIAN)
4339 uint16_t dst_mid /* destination mac address 16 middle bits */;
4340 uint16_t dst_lo /* destination mac address 16 low bits */;
4341 #elif defined(__LITTLE_ENDIAN)
4342 uint16_t dst_lo /* destination mac address 16 low bits */;
4343 uint16_t dst_mid /* destination mac address 16 middle bits */;
4345 #if defined(__BIG_ENDIAN)
4346 uint16_t src_lo /* source mac address 16 low bits */;
4347 uint16_t dst_hi /* destination mac address 16 high bits */;
4348 #elif defined(__LITTLE_ENDIAN)
4349 uint16_t dst_hi /* destination mac address 16 high bits */;
4350 uint16_t src_lo /* source mac address 16 low bits */;
4352 #if defined(__BIG_ENDIAN)
4353 uint16_t src_hi /* source mac address 16 high bits */;
4354 uint16_t src_mid /* source mac address 16 middle bits */;
4355 #elif defined(__LITTLE_ENDIAN)
4356 uint16_t src_mid /* source mac address 16 middle bits */;
4357 uint16_t src_hi /* source mac address 16 high bits */;
4363 * tunneling related data.
4365 struct eth_tunnel_data
4367 #if defined(__BIG_ENDIAN)
4368 uint16_t dst_mid /* destination mac address 16 middle bits */;
4369 uint16_t dst_lo /* destination mac address 16 low bits */;
4370 #elif defined(__LITTLE_ENDIAN)
4371 uint16_t dst_lo /* destination mac address 16 low bits */;
4372 uint16_t dst_mid /* destination mac address 16 middle bits */;
4374 #if defined(__BIG_ENDIAN)
4375 uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */;
4376 uint16_t dst_hi /* destination mac address 16 high bits */;
4377 #elif defined(__LITTLE_ENDIAN)
4378 uint16_t dst_hi /* destination mac address 16 high bits */;
4379 uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */;
4381 #if defined(__BIG_ENDIAN)
4383 #define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */
4384 #define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0
4385 #define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */
4386 #define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
4387 uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */;
4388 uint16_t pseudo_csum /* Pseudo checksum with length field=0 */;
4389 #elif defined(__LITTLE_ENDIAN)
4390 uint16_t pseudo_csum /* Pseudo checksum with length field=0 */;
4391 uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */;
4393 #define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */
4394 #define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0
4395 #define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */
4396 #define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
4401 * union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1).
4403 union eth_mac_addr_or_tunnel_data
4405 struct eth_mac_addresses mac_addr /* destination and source mac addresses. */;
4406 struct eth_tunnel_data tunnel_data /* tunneling related data. */;
4411 * Command for setting multicast classification for a client $$KEEP_ENDIANNESS$$
4413 struct eth_multicast_rules_cmd
4415 uint8_t cmd_general_data;
4416 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */
4417 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
4418 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */
4419 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
4420 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) /* BitField cmd_general_data 1 for add rule, 0 for remove rule */
4421 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
4422 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) /* BitField cmd_general_data */
4423 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
4424 uint8_t func_id /* the function id */;
4425 uint8_t bin_id /* the bin to add this function to (0-255) */;
4426 uint8_t engine_id /* the approximate multicast engine id */;
4428 struct regpair reserved3;
4433 * parameters for multicast classification ramrod $$KEEP_ENDIANNESS$$
4435 struct eth_multicast_rules_ramrod_data
4437 struct eth_classify_header header;
4438 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
4443 * Place holder for ramrods protocol specific data
4452 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
4454 union eth_ramrod_data
4456 struct ramrod_data general;
4461 * RSS toeplitz hash type, as reported in CQE
4463 enum eth_rss_hash_type
4471 E1HOV_PRI_HASH_TYPE,
4473 MAX_ETH_RSS_HASH_TYPE};
4481 ETH_RSS_MODE_DISABLED,
4482 ETH_RSS_MODE_ESX51 /* RSS mode for Vmware ESX 5.1 (Only do RSS if packet is UDP with dst port that matches the UDP 4-tuble Destination Port mask and value) */,
4483 ETH_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */,
4484 ETH_RSS_MODE_VLAN_PRI /* RSS based on inner-vlan priority field */,
4485 ETH_RSS_MODE_E1HOV_PRI /* RSS based on outer-vlan priority field */,
4486 ETH_RSS_MODE_IP_DSCP /* RSS based on IPv4 DSCP field */,
4491 * parameters for RSS update ramrod (E2) $$KEEP_ENDIANNESS$$
4493 struct eth_rss_update_ramrod_data
4495 uint8_t rss_engine_id;
4496 uint8_t capabilities;
4497 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 2-tupple capability */
4498 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
4499 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tupple capability for TCP */
4500 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
4501 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tupple capability for UDP */
4502 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
4503 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 2-tupple capability */
4504 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3
4505 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tupple capability for TCP */
4506 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
4507 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tupple capability for UDP */
4508 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
4509 #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6) /* BitField capabilitiesFunction RSS capabilities configuration of the 5-tupple capability */
4510 #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6
4511 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) /* BitField capabilitiesFunction RSS capabilities if set update the rss keys */
4512 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7
4513 uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */;
4514 uint8_t rss_mode /* The RSS mode for this function */;
4515 uint16_t udp_4tuple_dst_port_mask /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */;
4516 uint16_t udp_4tuple_dst_port_value /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */;
4517 uint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE] /* RSS indirection table */;
4518 uint32_t rss_key[T_ETH_RSS_KEY] /* RSS key supplied as by OS */;
4525 * The eth Rx Buffer Descriptor
4529 uint32_t addr_lo /* Single continuous buffer low pointer */;
4530 uint32_t addr_hi /* Single continuous buffer high pointer */;
4535 * Eth Rx Cqe structure- general structure for ramrods $$KEEP_ENDIANNESS$$
4537 struct common_ramrod_eth_rx_cqe
4539 uint8_t ramrod_type;
4540 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) /* BitField ramrod_type (use enum eth_rx_cqe_type) */
4541 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
4542 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) /* BitField ramrod_type */
4543 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
4544 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) /* BitField ramrod_type */
4545 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
4546 uint8_t conn_type /* only 3 bits are used */;
4547 uint16_t reserved1 /* protocol specific data */;
4548 uint32_t conn_and_cmd_data;
4549 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */
4550 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
4551 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use RamrodCommandIdEnum */
4552 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
4553 struct ramrod_data protocol_data /* protocol specific data */;
4555 uint32_t reserved2[11];
4559 * Rx Last CQE in page (in ETH)
4561 struct eth_rx_cqe_next_page
4563 uint32_t addr_lo /* Next page low pointer */;
4564 uint32_t addr_hi /* Next page high pointer */;
4565 uint32_t reserved[14];
4569 * union for all eth rx cqe types (fix their sizes)
4573 struct eth_fast_path_rx_cqe fast_path_cqe;
4574 struct common_ramrod_eth_rx_cqe ramrod_cqe;
4575 struct eth_rx_cqe_next_page next_page_cqe;
4576 struct eth_end_agg_rx_cqe end_agg_cqe;
4581 * Values for RX ETH CQE type field
4583 enum eth_rx_cqe_type
4585 RX_ETH_CQE_TYPE_ETH_FASTPATH /* Fast path CQE */,
4586 RX_ETH_CQE_TYPE_ETH_RAMROD /* Slow path CQE */,
4587 RX_ETH_CQE_TYPE_ETH_START_AGG /* Fast path CQE */,
4588 RX_ETH_CQE_TYPE_ETH_STOP_AGG /* Slow path CQE */,
4589 MAX_ETH_RX_CQE_TYPE};
4593 * Type of SGL/Raw field in ETH RX fast path CQE
4597 ETH_FP_CQE_REGULAR /* Regular CQE- no extra data */,
4598 ETH_FP_CQE_RAW /* Extra data is raw data- iscsi OOO */,
4603 * The eth Rx SGE Descriptor
4607 uint32_t addr_lo /* Single continuous buffer low pointer */;
4608 uint32_t addr_hi /* Single continuous buffer high pointer */;
4613 * common data for all protocols $$KEEP_ENDIANNESS$$
4617 uint32_t conn_and_cmd_data;
4618 #define SPE_HDR_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */
4619 #define SPE_HDR_CID_SHIFT 0
4620 #define SPE_HDR_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use enum common_spqe_cmd_id/eth_spqe_cmd_id/toe_spqe_cmd_id */
4621 #define SPE_HDR_CMD_ID_SHIFT 24
4623 #define SPE_HDR_CONN_TYPE (0xFF<<0) /* BitField type connection type. (3 bits are used) (use enum connection_type) */
4624 #define SPE_HDR_CONN_TYPE_SHIFT 0
4625 #define SPE_HDR_FUNCTION_ID (0xFF<<8) /* BitField type */
4626 #define SPE_HDR_FUNCTION_ID_SHIFT 8
4631 * specific data for ethernet slow path element
4633 union eth_specific_data
4635 uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */;
4636 struct regpair client_update_ramrod_data /* The address of the data for client update ramrod */;
4637 struct regpair client_init_ramrod_init_data /* The data for client setup ramrod */;
4638 struct eth_halt_ramrod_data halt_ramrod_data /* Includes the client id to be deleted */;
4639 struct regpair update_data_addr /* physical address of the eth_rss_update_ramrod_data struct, as allocated by the driver */;
4640 struct eth_common_ramrod_data common_ramrod_data /* The data contain client ID need to the ramrod */;
4641 struct regpair classify_cfg_addr /* physical address of the eth_classify_rules_ramrod_data struct, as allocated by the driver */;
4642 struct regpair filter_cfg_addr /* physical address of the eth_filter_cfg_ramrod_data struct, as allocated by the driver */;
4643 struct regpair mcast_cfg_addr /* physical address of the eth_mcast_cfg_ramrod_data struct, as allocated by the driver */;
4647 * Ethernet slow path element
4651 struct spe_hdr hdr /* common data for all protocols */;
4652 union eth_specific_data data /* data specific to ethernet protocol */;
4657 * Ethernet command ID for slow path elements
4659 enum eth_spqe_cmd_id
4661 RAMROD_CMD_ID_ETH_UNUSED,
4662 RAMROD_CMD_ID_ETH_CLIENT_SETUP /* Setup a new L2 client */,
4663 RAMROD_CMD_ID_ETH_HALT /* Halt an L2 client */,
4664 RAMROD_CMD_ID_ETH_FORWARD_SETUP /* Setup a new FW channel */,
4665 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP /* Setup a new Tx only queue */,
4666 RAMROD_CMD_ID_ETH_CLIENT_UPDATE /* Update an L2 client configuration */,
4667 RAMROD_CMD_ID_ETH_EMPTY /* Empty ramrod - used to synchronize iSCSI OOO */,
4668 RAMROD_CMD_ID_ETH_TERMINATE /* Terminate an L2 client */,
4669 RAMROD_CMD_ID_ETH_TPA_UPDATE /* update the tpa roles in L2 client */,
4670 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,
4671 RAMROD_CMD_ID_ETH_FILTER_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,
4672 RAMROD_CMD_ID_ETH_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */,
4673 RAMROD_CMD_ID_ETH_RSS_UPDATE /* Update RSS configuration */,
4674 RAMROD_CMD_ID_ETH_SET_MAC /* Update RSS configuration */,
4675 MAX_ETH_SPQE_CMD_ID};
4679 * eth tpa update command
4681 enum eth_tpa_update_command
4683 TPA_UPDATE_NONE_COMMAND /* nop command */,
4684 TPA_UPDATE_ENABLE_COMMAND /* enable command */,
4685 TPA_UPDATE_DISABLE_COMMAND /* disable command */,
4686 MAX_ETH_TPA_UPDATE_COMMAND};
4690 * In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header
4692 enum eth_tunnel_lso_inc_ip_id
4694 EXT_HEADER /* Increment IP ID of external header (HW works on external, FW works on internal */,
4695 INT_HEADER /* Increment IP ID of internal header (HW works on internal, FW works on external */,
4696 MAX_ETH_TUNNEL_LSO_INC_IP_ID};
4700 * In case tunnel exist and L4 checksum offload (or outer ip header checksum), the pseudo checksum location, on packet or on BD.
4702 enum eth_tunnel_non_lso_csum_location
4704 CSUM_ON_PKT /* checksum is on the packet. */,
4705 CSUM_ON_BD /* checksum is on the BD. */,
4706 MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION};
4710 * Tx regular BD structure $$KEEP_ENDIANNESS$$
4714 uint32_t addr_lo /* Single continuous buffer low pointer */;
4715 uint32_t addr_hi /* Single continuous buffer high pointer */;
4716 uint16_t total_pkt_bytes /* Size of the entire packet, valid for non-LSO packets */;
4717 uint16_t nbytes /* Size of the data represented by the BD */;
4718 uint8_t reserved[4] /* keeps same size as other eth tx bd types */;
4723 * structure for easy accessibility to assembler
4725 struct eth_tx_bd_flags
4727 uint8_t as_bitfield;
4728 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) /* BitField as_bitfield IP CKSUM flag,Relevant in START */
4729 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
4730 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) /* BitField as_bitfield L4 CKSUM flag,Relevant in START */
4731 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
4732 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) /* BitField as_bitfield 00 - no vlan; 01 - inband Vlan; 10 outband Vlan (use enum eth_tx_vlan_type) */
4733 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
4734 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4) /* BitField as_bitfield Start of packet BD */
4735 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
4736 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) /* BitField as_bitfield flag that indicates that the current packet is a udp packet */
4737 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
4738 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) /* BitField as_bitfield LSO flag, Relevant in START */
4739 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
4740 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) /* BitField as_bitfield set in case ipV6 packet, Relevant in START */
4741 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
4745 * The eth Tx Buffer Descriptor $$KEEP_ENDIANNESS$$
4747 struct eth_tx_start_bd
4750 uint16_t nbd /* Num of BDs in packet: include parsInfoBD, Relevant in START(only in Everest) */;
4751 uint16_t nbytes /* Size of the data represented by the BD */;
4752 uint16_t vlan_or_ethertype /* Vlan structure: vlan_id is in lsb, then cfi and then priority vlan_id 12 bits (lsb), cfi 1 bit, priority 3 bits. In E2, this field should be set with etherType for VFs with no vlan */;
4753 struct eth_tx_bd_flags bd_flags;
4754 uint8_t general_data;
4755 #define ETH_TX_START_BD_HDR_NBDS (0xF<<0) /* BitField general_data contains the number of BDs that contain Ethernet/IP/TCP headers, for full/partial LSO modes */
4756 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
4757 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) /* BitField general_data force vlan mode according to bds (vlan mode can change accroding to global configuration) */
4758 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
4759 #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) /* BitField general_data Determines the number of parsing BDs in packet. Number of parsing BDs in packet is (parse_nbds+1). */
4760 #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5
4761 #define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) /* BitField general_data set in case of tunneling encapsulated packet */
4762 #define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7
4766 * Tx parsing BD structure for ETH E1h $$KEEP_ENDIANNESS$$
4768 struct eth_tx_parse_bd_e1x
4770 uint16_t global_data;
4771 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) /* BitField global_data IP header Offset in WORDs from start of packet */
4772 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
4773 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) /* BitField global_data marks ethernet address type (use enum eth_addr_type) */
4774 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4
4775 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) /* BitField global_data */
4776 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6
4777 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) /* BitField global_data */
4778 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7
4779 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */
4780 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8
4781 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) /* BitField global_data reserved bit, should be set with 0 */
4782 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9
4784 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */
4785 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
4786 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */
4787 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
4788 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */
4789 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
4790 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */
4791 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
4792 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */
4793 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
4794 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */
4795 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
4796 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */
4797 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
4798 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */
4799 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
4800 uint8_t ip_hlen_w /* IP header length in WORDs */;
4801 uint16_t total_hlen_w /* IP+TCP+ETH */;
4802 uint16_t tcp_pseudo_csum /* Checksum of pseudo header with length field=0 */;
4803 uint16_t lso_mss /* for LSO mode */;
4804 uint16_t ip_id /* for LSO mode */;
4805 uint32_t tcp_send_seq /* for LSO mode */;
4809 * Tx parsing BD structure for ETH E2 $$KEEP_ENDIANNESS$$
4811 struct eth_tx_parse_bd_e2
4813 union eth_mac_addr_or_tunnel_data data /* union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). */;
4814 uint32_t parsing_data;
4815 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) /* BitField parsing_data TCP/UDP header Offset in WORDs from start of packet */
4816 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0
4817 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) /* BitField parsing_data TCP header size in DOUBLE WORDS */
4818 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11
4819 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) /* BitField parsing_data a flag to indicate an ipv6 packet with extension headers. If set on LSO packet, pseudo CS should be placed in TCP CS field without length field */
4820 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15
4821 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) /* BitField parsing_data for LSO mode */
4822 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16
4823 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) /* BitField parsing_data marks ethernet address type (use enum eth_addr_type) */
4824 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30
4828 * Tx 2nd parsing BD structure for ETH packet $$KEEP_ENDIANNESS$$
4830 struct eth_tx_parse_2nd_bd
4832 uint16_t global_data;
4833 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) /* BitField global_data Outer IP header offset in WORDs (16-bit) from start of packet */
4834 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0
4835 #define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4) /* BitField global_data should be set with 0 */
4836 #define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4
4837 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) /* BitField global_data */
4838 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5
4839 #define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */
4840 #define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6
4841 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) /* BitField global_data Set in case UDP header exists in tunnel outer hedears. */
4842 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7
4843 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) /* BitField global_data Outer IP header length in WORDs (16-bit). Valid only for IpV4. */
4844 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8
4845 #define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13) /* BitField global_data should be set with 0 */
4846 #define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13
4849 #define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */
4850 #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0
4851 #define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */
4852 #define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1
4853 #define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */
4854 #define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2
4855 #define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */
4856 #define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3
4857 #define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */
4858 #define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4
4859 #define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */
4860 #define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5
4861 #define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */
4862 #define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6
4863 #define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */
4864 #define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7
4866 uint8_t tunnel_udp_hdr_start_w /* Offset (in WORDs) from start of packet to tunnel UDP header. (if exist) */;
4867 uint8_t fw_ip_hdr_to_payload_w /* In IpV4, the length (in WORDs) from the FW IpV4 header start to the payload start. In IpV6, the length (in WORDs) from the FW IpV6 header end to the payload start. However, if extension headers are included, their length is counted here as well. */;
4868 uint16_t fw_ip_csum_wo_len_flags_frag /* For the IP header which is set by the FW, the IP checksum without length, flags and fragment offset. */;
4869 uint16_t hw_ip_id /* The IP ID to be set by HW for LSO packets in tunnel mode. */;
4870 uint32_t tcp_send_seq /* The TCP sequence number for LSO packets. */;
4874 * The last BD in the BD memory will hold a pointer to the next BD memory
4876 struct eth_tx_next_bd
4878 uint32_t addr_lo /* Single continuous buffer low pointer */;
4879 uint32_t addr_hi /* Single continuous buffer high pointer */;
4880 uint8_t reserved[8] /* keeps same size as other eth tx bd types */;
4884 * union for 4 Bd types
4886 union eth_tx_bd_types
4888 struct eth_tx_start_bd start_bd /* the first bd in a packets */;
4889 struct eth_tx_bd reg_bd /* the common bd */;
4890 struct eth_tx_parse_bd_e1x parse_bd_e1x /* parsing info BD for e1/e1h */;
4891 struct eth_tx_parse_bd_e2 parse_bd_e2 /* parsing info BD for e2 */;
4892 struct eth_tx_parse_2nd_bd parse_2nd_bd /* 2nd parsing info BD */;
4893 struct eth_tx_next_bd next_bd /* Bd that contains the address of the next page */;
4897 * array of 13 bds as appears in the eth xstorm context
4899 struct eth_tx_bds_array
4901 union eth_tx_bd_types bds[13];
4906 * VLAN mode on TX BDs
4908 enum eth_tx_vlan_type
4913 X_ETH_FW_ADDED_VLAN /* Driver should not use this! */,
4914 MAX_ETH_TX_VLAN_TYPE};
4918 * Ethernet VLAN filtering mode in E1x
4920 enum eth_vlan_filter_mode
4922 ETH_VLAN_FILTER_ANY_VLAN /* Don't filter by vlan */,
4923 ETH_VLAN_FILTER_SPECIFIC_VLAN /* Only the vlan_id is allowed */,
4924 ETH_VLAN_FILTER_CLASSIFY /* Vlan will be added to CAM for classification */,
4925 MAX_ETH_VLAN_FILTER_MODE};
4929 * MAC filtering configuration command header $$KEEP_ENDIANNESS$$
4931 struct mac_configuration_hdr
4933 uint8_t length /* number of entries valid in this command (6 bits) */;
4934 uint8_t offset /* offset of the first entry in the list */;
4935 uint16_t client_id /* the client id which this ramrod is sent on. 5b is used. */;
4936 uint32_t echo /* echo value to be sent to driver on event ring */;
4940 * MAC address in list for ramrod $$KEEP_ENDIANNESS$$
4942 struct mac_configuration_entry
4944 uint16_t lsb_mac_addr /* 2 LSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */;
4945 uint16_t middle_mac_addr /* 2 middle bytes of MAC address (should be given in big endien - driver should do hton to this number!!!) */;
4946 uint16_t msb_mac_addr /* 2 MSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */;
4947 uint16_t vlan_id /* The inner vlan id (12b). Used either in vlan_in_cam for mac_valn pair or for vlan filtering */;
4948 uint8_t pf_id /* The pf id, for multi function mode */;
4950 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) /* BitField flags configures the action to be done in cam (used only is slow path handlers) (use enum set_mac_action_type) */
4951 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
4952 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) /* BitField flags If set, this MAC also belongs to RDMA client */
4953 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
4954 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) /* BitField flags (use enum eth_vlan_filter_mode) */
4955 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
4956 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) /* BitField flags BitField flags 0 - can't remove vlan 1 - can remove vlan. relevant only to everest1 */
4957 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
4958 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) /* BitField flags BitField flags 0 - not broadcast 1 - broadcast. relevant only to everest1 */
4959 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
4960 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) /* BitField flags */
4961 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
4963 uint32_t clients_bit_vector /* Bit vector for the clients which should receive this MAC. */;
4967 * MAC filtering configuration command
4969 struct mac_configuration_cmd
4971 struct mac_configuration_hdr hdr /* header */;
4972 struct mac_configuration_entry config_table[64] /* table of 64 MAC configuration entries: addresses and target table entries */;
4977 * Set-MAC command type (in E1x)
4979 enum set_mac_action_type
4981 T_ETH_MAC_COMMAND_INVALIDATE,
4982 T_ETH_MAC_COMMAND_SET,
4983 MAX_SET_MAC_ACTION_TYPE};
4987 * Ethernet TPA Modes
4991 TPA_LRO /* LRO mode TPA */,
4992 TPA_GRO /* GRO mode TPA */,
4997 * tpa update ramrod data $$KEEP_ENDIANNESS$$
4999 struct tpa_update_ramrod_data
5001 uint8_t update_ipv4 /* none, enable or disable */;
5002 uint8_t update_ipv6 /* none, enable or disable */;
5003 uint8_t client_id /* client init flow control data */;
5004 uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */;
5005 uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */;
5006 uint8_t complete_on_both_clients /* If set and the client has different sp_client, completion will be sent to both rings */;
5007 uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */;
5008 uint8_t tpa_mode /* TPA mode to use (LRO or GRO) */;
5009 uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */;
5010 uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */;
5011 uint32_t sge_page_base_lo /* The address to fetch the next sges from (low) */;
5012 uint32_t sge_page_base_hi /* The address to fetch the next sges from (high) */;
5013 uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */;
5014 uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */;
5019 * approximate-match multicast filtering for E1H per function in Tstorm
5021 struct tstorm_eth_approximate_match_multicast_filtering
5023 uint32_t mcast_add_hash_bit_array[8] /* Bit array for multicast hash filtering.Each bit supports a hash function result if to accept this multicast dst address. */;
5028 * Common configuration parameters per function in Tstorm $$KEEP_ENDIANNESS$$
5030 struct tstorm_eth_function_common_config
5032 uint16_t config_flags;
5033 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */
5034 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
5035 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 4-tupple capability */
5036 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
5037 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */
5038 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
5039 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV6 4-tupple capability */
5040 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
5041 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) /* BitField config_flagsGeneral configuration flags RSS mode of operation (use enum eth_rss_mode) */
5042 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
5043 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) /* BitField config_flagsGeneral configuration flags 0 - Don't filter by vlan, 1 - Filter according to the vlans specificied in mac_filter_config */
5044 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
5045 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) /* BitField config_flagsGeneral configuration flags */
5046 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
5047 uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */;
5049 uint16_t vlan_id[2] /* VLANs of this function. VLAN filtering is determine according to vlan_filtering_enable. */;
5054 * MAC filtering configuration parameters per port in Tstorm $$KEEP_ENDIANNESS$$
5056 struct tstorm_eth_mac_filter_config
5058 uint32_t ucast_drop_all /* bit vector in which the clients which drop all unicast packets are set */;
5059 uint32_t ucast_accept_all /* bit vector in which clients that accept all unicast packets are set */;
5060 uint32_t mcast_drop_all /* bit vector in which the clients which drop all multicast packets are set */;
5061 uint32_t mcast_accept_all /* bit vector in which clients that accept all multicast packets are set */;
5062 uint32_t bcast_accept_all /* bit vector in which clients that accept all broadcast packets are set */;
5063 uint32_t vlan_filter[2] /* bit vector for VLAN filtering. Clients which enforce filtering of vlan[x] should be marked in vlan_filter[x]. The primary vlan is taken from the CAM target table. */;
5064 uint32_t unmatched_unicast /* bit vector in which clients that accept unmatched unicast packets are set */;
5069 * tx only queue init ramrod data $$KEEP_ENDIANNESS$$
5071 struct tx_queue_init_ramrod_data
5073 struct client_init_general_data general /* client init general data */;
5074 struct client_init_tx_data tx /* client init tx data */;
5079 * Three RX producers for ETH
5081 union ustorm_eth_rx_producers
5084 #if defined(__BIG_ENDIAN)
5085 uint16_t bd_prod /* Producer of the RX BD ring */;
5086 uint16_t cqe_prod /* Producer of the RX CQE ring */;
5087 #elif defined(__LITTLE_ENDIAN)
5088 uint16_t cqe_prod /* Producer of the RX CQE ring */;
5089 uint16_t bd_prod /* Producer of the RX BD ring */;
5091 #if defined(__BIG_ENDIAN)
5093 uint16_t sge_prod /* Producer of the RX SGE ring */;
5094 #elif defined(__LITTLE_ENDIAN)
5095 uint16_t sge_prod /* Producer of the RX SGE ring */;
5099 uint32_t raw_data[2];
5104 * The data afex vif list ramrod need $$KEEP_ENDIANNESS$$
5106 struct afex_vif_list_ramrod_data
5108 uint8_t afex_vif_list_command /* set get, clear all a VIF list id defined by enum vif_list_rule_kind */;
5109 uint8_t func_bit_map /* the function bit map to set */;
5110 uint16_t vif_list_index /* the VIF list, in a per pf vector to add this function to */;
5111 uint8_t func_to_clear /* the func id to clear in case of clear func mode */;
5118 * cfc delete event data $$KEEP_ENDIANNESS$$
5120 struct cfc_del_event_data
5122 uint32_t cid /* cid of deleted connection */;
5129 * per-port SAFC demo variables
5131 struct cmng_flags_per_port
5133 uint32_t cmng_enables;
5134 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between vnics */
5135 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
5136 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable rate shaping between vnics */
5137 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
5138 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between COSes */
5139 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
5140 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes (use enum fairness_mode) */
5141 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
5142 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes reserved */
5143 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
5144 uint32_t __reserved1;
5149 * per-port rate shaping variables
5151 struct rate_shaping_vars_per_port
5153 uint32_t rs_periodic_timeout /* timeout of periodic timer */;
5154 uint32_t rs_threshold /* threshold, below which we start to stop queues */;
5158 * per-port fairness variables
5160 struct fairness_vars_per_port
5162 uint32_t upper_bound /* Quota for a protocol/vnic */;
5163 uint32_t fair_threshold /* almost-empty threshold */;
5164 uint32_t fairness_timeout /* timeout of fairness timer */;
5169 * per-port SAFC variables
5171 struct safc_struct_per_port
5173 #if defined(__BIG_ENDIAN)
5174 uint16_t __reserved1;
5175 uint8_t __reserved0;
5176 uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */;
5177 #elif defined(__LITTLE_ENDIAN)
5178 uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */;
5179 uint8_t __reserved0;
5180 uint16_t __reserved1;
5182 uint8_t cos_to_traffic_types[MAX_COS_NUMBER] /* translate cos to service traffics types */;
5183 uint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS] /* QM pause mask for each class of service in the SAFC frame */;
5187 * Per-port congestion management variables
5189 struct cmng_struct_per_port
5191 struct rate_shaping_vars_per_port rs_vars;
5192 struct fairness_vars_per_port fair_vars;
5193 struct safc_struct_per_port safc_vars;
5194 struct cmng_flags_per_port flags;
5198 * a single rate shaping counter. can be used as protocol or vnic counter
5200 struct rate_shaping_counter
5202 uint32_t quota /* Quota for a protocol/vnic */;
5203 #if defined(__BIG_ENDIAN)
5204 uint16_t __reserved0;
5205 uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */;
5206 #elif defined(__LITTLE_ENDIAN)
5207 uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */;
5208 uint16_t __reserved0;
5213 * per-vnic rate shaping variables
5215 struct rate_shaping_vars_per_vn
5217 struct rate_shaping_counter vn_counter /* per-vnic counter */;
5221 * per-vnic fairness variables
5223 struct fairness_vars_per_vn
5225 uint32_t cos_credit_delta[MAX_COS_NUMBER] /* used for incrementing the credit */;
5226 uint32_t vn_credit_delta /* used for incrementing the credit */;
5227 uint32_t __reserved0;
5231 * cmng port init state
5235 struct rate_shaping_vars_per_vn vnic_max_rate[4];
5236 struct fairness_vars_per_vn vnic_min_rate[4];
5240 * cmng port init state
5244 struct cmng_struct_per_port port;
5245 struct cmng_vnic vnic;
5250 * driver parameters for congestion management init, all rates are in Mbps
5252 struct cmng_init_input
5255 uint16_t vnic_min_rate[4] /* rates are in Mbps */;
5256 uint16_t vnic_max_rate[4] /* rates are in Mbps */;
5257 uint16_t cos_min_rate[MAX_COS_NUMBER] /* rates are in Mbps */;
5258 uint16_t cos_to_pause_mask[MAX_COS_NUMBER];
5259 struct cmng_flags_per_port flags;
5264 * Protocol-common command ID for slow path elements
5266 enum common_spqe_cmd_id
5268 RAMROD_CMD_ID_COMMON_UNUSED,
5269 RAMROD_CMD_ID_COMMON_FUNCTION_START /* Start a function (for PFs only) */,
5270 RAMROD_CMD_ID_COMMON_FUNCTION_STOP /* Stop a function (for PFs only) */,
5271 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE /* niv update function */,
5272 RAMROD_CMD_ID_COMMON_CFC_DEL /* Delete a connection from CFC */,
5273 RAMROD_CMD_ID_COMMON_CFC_DEL_WB /* Delete a connection from CFC (with write back) */,
5274 RAMROD_CMD_ID_COMMON_STAT_QUERY /* Collect statistics counters */,
5275 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */,
5276 RAMROD_CMD_ID_COMMON_START_TRAFFIC /* Start Tx traffic (after DCB updates) */,
5277 RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS /* niv vif lists */,
5278 RAMROD_CMD_ID_COMMON_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */,
5279 MAX_COMMON_SPQE_CMD_ID};
5283 * Per-protocol connection types
5285 enum connection_type
5287 ETH_CONNECTION_TYPE /* Ethernet */,
5288 TOE_CONNECTION_TYPE /* TOE */,
5289 RDMA_CONNECTION_TYPE /* RDMA */,
5290 ISCSI_CONNECTION_TYPE /* iSCSI */,
5291 FCOE_CONNECTION_TYPE /* FCoE */,
5292 RESERVED_CONNECTION_TYPE_0,
5293 RESERVED_CONNECTION_TYPE_1,
5294 RESERVED_CONNECTION_TYPE_2,
5295 NONE_CONNECTION_TYPE /* General- used for common slow path */,
5296 MAX_CONNECTION_TYPE};
5304 OVERRIDE_COS /* Firmware deduce cos according to DCB */,
5305 STATIC_COS /* Firmware has constant queues per CoS */,
5306 FW_WRR /* Firmware keep fairness between different CoSes */,
5311 * Dynamic HC counters set by the driver
5313 struct hc_dynamic_drv_counter
5315 uint32_t val[HC_SB_MAX_DYNAMIC_INDICES] /* 4 bytes * 4 indices = 2 lines */;
5319 * zone A per-queue data
5321 struct cstorm_queue_zone_data
5323 struct hc_dynamic_drv_counter hc_dyn_drv_cnt /* 4 bytes * 4 indices = 2 lines */;
5324 struct regpair reserved[2];
5329 * Vf-PF channel data in cstorm ram (non-triggered zone)
5331 struct vf_pf_channel_zone_data
5333 uint32_t msg_addr_lo /* the message address on VF memory */;
5334 uint32_t msg_addr_hi /* the message address on VF memory */;
5338 * zone for VF non-triggered data
5340 struct non_trigger_vf_zone
5342 struct vf_pf_channel_zone_data vf_pf_channel /* vf-pf channel zone data */;
5346 * Vf-PF channel trigger zone in cstorm ram
5348 struct vf_pf_channel_zone_trigger
5350 uint8_t addr_valid /* indicates that a vf-pf message is pending. MUST be set AFTER the message address. */;
5354 * zone that triggers the in-bound interrupt
5356 struct trigger_vf_zone
5358 #if defined(__BIG_ENDIAN)
5361 struct vf_pf_channel_zone_trigger vf_pf_channel;
5362 #elif defined(__LITTLE_ENDIAN)
5363 struct vf_pf_channel_zone_trigger vf_pf_channel;
5371 * zone B per-VF data
5373 struct cstorm_vf_zone_data
5375 struct non_trigger_vf_zone non_trigger /* zone for VF non-triggered data */;
5376 struct trigger_vf_zone trigger /* zone that triggers the in-bound interrupt */;
5381 * Dynamic host coalescing init parameters, per state machine
5383 struct dynamic_hc_sm_config
5385 uint32_t threshold[3] /* thresholds of number of outstanding bytes */;
5386 uint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES] /* bytes difference of each protocol is shifted right by this value */;
5387 uint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 0 for each protocol, in units of usec */;
5388 uint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 1 for each protocol, in units of usec */;
5389 uint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 2 for each protocol, in units of usec */;
5390 uint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 3 for each protocol, in units of usec */;
5394 * Dynamic host coalescing init parameters
5396 struct dynamic_hc_config
5398 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM] /* Configuration per state machine */;
5402 struct e2_integ_data
5404 #if defined(__BIG_ENDIAN)
5406 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */
5407 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
5408 #define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */
5409 #define E2_INTEG_DATA_LB_TX_SHIFT 1
5410 #define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */
5411 #define E2_INTEG_DATA_COS_TX_SHIFT 2
5412 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */
5413 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
5414 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */
5415 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
5416 #define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */
5417 #define E2_INTEG_DATA_RESERVED_SHIFT 5
5418 uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */;
5419 uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
5420 uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
5421 #elif defined(__LITTLE_ENDIAN)
5422 uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
5423 uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
5424 uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */;
5426 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */
5427 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
5428 #define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */
5429 #define E2_INTEG_DATA_LB_TX_SHIFT 1
5430 #define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */
5431 #define E2_INTEG_DATA_COS_TX_SHIFT 2
5432 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */
5433 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
5434 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */
5435 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
5436 #define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */
5437 #define E2_INTEG_DATA_RESERVED_SHIFT 5
5439 #if defined(__BIG_ENDIAN)
5442 uint8_t ramEn /* context area reserved for reading enable bit from ram */;
5443 #elif defined(__LITTLE_ENDIAN)
5444 uint8_t ramEn /* context area reserved for reading enable bit from ram */;
5452 * set mac event data $$KEEP_ENDIANNESS$$
5454 struct eth_event_data
5456 uint32_t echo /* set mac echo data to return to driver */;
5463 * pf-vf event data $$KEEP_ENDIANNESS$$
5465 struct vf_pf_event_data
5467 uint8_t vf_id /* VF ID (0-63) */;
5470 uint32_t msg_addr_lo /* message address on Vf (low 32 bits) */;
5471 uint32_t msg_addr_hi /* message address on Vf (high 32 bits) */;
5475 * VF FLR event data $$KEEP_ENDIANNESS$$
5477 struct vf_flr_event_data
5479 uint8_t vf_id /* VF ID (0-63) */;
5487 * malicious VF event data $$KEEP_ENDIANNESS$$
5489 struct malicious_vf_event_data
5491 uint8_t vf_id /* VF ID (0-63) */;
5492 uint8_t err_id /* reason for malicious notification */;
5499 * vif list event data $$KEEP_ENDIANNESS$$
5501 struct vif_list_event_data
5503 uint8_t func_bit_map /* bit map of pf indice */;
5511 * function update event data $$KEEP_ENDIANNESS$$
5513 struct function_update_event_data
5523 * union for all event ring message types
5527 struct vf_pf_event_data vf_pf_event /* vf-pf event data */;
5528 struct eth_event_data eth_event /* set mac event data */;
5529 struct cfc_del_event_data cfc_del_event /* cfc delete event data */;
5530 struct vf_flr_event_data vf_flr_event /* vf flr event data */;
5531 struct malicious_vf_event_data malicious_vf_event /* malicious vf event data */;
5532 struct vif_list_event_data vif_list_event /* vif list event data */;
5533 struct function_update_event_data function_update_event /* function update event data */;
5538 * per PF event ring data
5540 struct event_ring_data
5542 struct regpair_native base_addr /* ring base address */;
5543 #if defined(__BIG_ENDIAN)
5544 uint8_t index_id /* index ID within the status block */;
5545 uint8_t sb_id /* status block ID */;
5546 uint16_t producer /* event ring producer */;
5547 #elif defined(__LITTLE_ENDIAN)
5548 uint16_t producer /* event ring producer */;
5549 uint8_t sb_id /* status block ID */;
5550 uint8_t index_id /* index ID within the status block */;
5557 * event ring message element (each element is 128 bits) $$KEEP_ENDIANNESS$$
5559 struct event_ring_msg
5562 uint8_t error /* error on the mesasage */;
5564 union event_data data /* message data (96 bits data) */;
5568 * event ring next page element (128 bits)
5570 struct event_ring_next
5572 struct regpair addr /* Address of the next page of the ring */;
5573 uint32_t reserved[2];
5577 * union for event ring element types (each element is 128 bits)
5579 union event_ring_elem
5581 struct event_ring_msg message /* event ring message */;
5582 struct event_ring_next next_page /* event ring next page */;
5587 * Common event ring opcodes
5589 enum event_ring_opcode
5591 EVENT_RING_OPCODE_VF_PF_CHANNEL,
5592 EVENT_RING_OPCODE_FUNCTION_START /* Start a function (for PFs only) */,
5593 EVENT_RING_OPCODE_FUNCTION_STOP /* Stop a function (for PFs only) */,
5594 EVENT_RING_OPCODE_CFC_DEL /* Delete a connection from CFC */,
5595 EVENT_RING_OPCODE_CFC_DEL_WB /* Delete a connection from CFC (with write back) */,
5596 EVENT_RING_OPCODE_STAT_QUERY /* Collect statistics counters */,
5597 EVENT_RING_OPCODE_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */,
5598 EVENT_RING_OPCODE_START_TRAFFIC /* Start Tx traffic (after DCB updates) */,
5599 EVENT_RING_OPCODE_VF_FLR /* VF FLR indication for PF */,
5600 EVENT_RING_OPCODE_MALICIOUS_VF /* Malicious VF operation detected */,
5601 EVENT_RING_OPCODE_FORWARD_SETUP /* Initialize forward channel */,
5602 EVENT_RING_OPCODE_RSS_UPDATE_RULES /* Update RSS configuration */,
5603 EVENT_RING_OPCODE_FUNCTION_UPDATE /* function update */,
5604 EVENT_RING_OPCODE_AFEX_VIF_LISTS /* event ring opcode niv vif lists */,
5605 EVENT_RING_OPCODE_SET_MAC /* Add/remove MAC (in E1x only) */,
5606 EVENT_RING_OPCODE_CLASSIFICATION_RULES /* Add/remove MAC or VLAN (in E2/E3 only) */,
5607 EVENT_RING_OPCODE_FILTERS_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,
5608 EVENT_RING_OPCODE_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */,
5609 EVENT_RING_OPCODE_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */,
5610 MAX_EVENT_RING_OPCODE};
5614 * Modes for fairness algorithm
5618 FAIRNESS_COS_WRR_MODE /* Weighted round robin mode (used in Google) */,
5619 FAIRNESS_COS_ETS_MODE /* ETS mode (used in FCoE) */,
5624 * Priority and cos $$KEEP_ENDIANNESS$$
5628 uint8_t priority /* Priority */;
5629 uint8_t cos /* Cos */;
5634 * The data for flow control configuration $$KEEP_ENDIANNESS$$
5636 struct flow_control_configuration
5638 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES] /* traffic_type to priority cos */;
5639 uint8_t dcb_enabled /* If DCB mode is enabled then traffic class to priority array is fully initialized and there must be inner VLAN */;
5640 uint8_t dcb_version /* DCB version Increase by one on each DCB update */;
5641 uint8_t dont_add_pri_0 /* In case, the priority is 0, and the packet has no vlan, the firmware wont add vlan */;
5648 * $$KEEP_ENDIANNESS$$
5650 struct function_start_data
5652 uint8_t function_mode /* the function mode */;
5653 uint8_t allow_npar_tx_switching /* If set, inter-pf tx switching is allowed in Switch Independent function mode. (E2/E3 Only) */;
5654 uint16_t sd_vlan_tag /* value of Vlan in case of switch depended multi-function mode */;
5655 uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */;
5657 uint8_t network_cos_mode /* The cos mode for network traffic. */;
5658 uint8_t dmae_cmd_id /* The DMAE command id to use for FW DMAE transactions */;
5659 uint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */;
5660 uint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */;
5661 uint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */;
5662 uint16_t reserved1[2];
5667 * $$KEEP_ENDIANNESS$$
5669 struct function_update_data
5671 uint8_t vif_id_change_flg /* If set, vif_id will be checked */;
5672 uint8_t afex_default_vlan_change_flg /* If set, afex_default_vlan will be checked */;
5673 uint8_t allowed_priorities_change_flg /* If set, allowed_priorities will be checked */;
5674 uint8_t network_cos_mode_change_flg /* If set, network_cos_mode will be checked */;
5675 uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */;
5676 uint16_t afex_default_vlan /* value of default Vlan in case of NIV mf */;
5677 uint8_t allowed_priorities /* bit vector of allowed Vlan priorities for this VIF */;
5678 uint8_t network_cos_mode /* The cos mode for network traffic. */;
5679 uint8_t lb_mode_en_change_flg /* If set, lb_mode_en will be checked */;
5680 uint8_t lb_mode_en /* If set, niv loopback mode will be enabled */;
5681 uint8_t tx_switch_suspend_change_flg /* If set, tx_switch_suspend will be checked */;
5682 uint8_t tx_switch_suspend /* If set, TX switching TO this function will be disabled and packets will be dropped */;
5685 uint8_t update_gre_cfg_flg /* If set, GRE config for the function will be updated according to the gre_tunnel_rss and nvgre_clss_en fields */;
5686 uint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */;
5687 uint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */;
5688 uint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */;
5694 * FW version stored in the Xstorm RAM
5698 #if defined(__BIG_ENDIAN)
5699 uint8_t engineering /* firmware current engineering version */;
5700 uint8_t revision /* firmware current revision version */;
5701 uint8_t minor /* firmware current minor version */;
5702 uint8_t major /* firmware current major version */;
5703 #elif defined(__LITTLE_ENDIAN)
5704 uint8_t major /* firmware current major version */;
5705 uint8_t minor /* firmware current minor version */;
5706 uint8_t revision /* firmware current revision version */;
5707 uint8_t engineering /* firmware current engineering version */;
5710 #define FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */
5711 #define FW_VERSION_OPTIMIZED_SHIFT 0
5712 #define FW_VERSION_BIG_ENDIEN (0x1<<1) /* BitField flags if set, this is big-endien ASM */
5713 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
5714 #define FW_VERSION_CHIP_VERSION (0x3<<2) /* BitField flags 1 - E1H */
5715 #define FW_VERSION_CHIP_VERSION_SHIFT 2
5716 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4) /* BitField flags */
5717 #define __FW_VERSION_RESERVED_SHIFT 4
5726 GRE_OUTER_HEADERS_RSS /* RSS for GRE Packets is performed on the outer headers */,
5727 GRE_INNER_HEADERS_RSS /* RSS for GRE Packets is performed on the inner headers */,
5728 NVGRE_KEY_ENTROPY_RSS /* RSS for NVGRE Packets is done based on a hash containing the entropy bits from the GRE Key Field (gre_tunnel must be NVGRE_TUNNEL) */,
5735 enum gre_tunnel_type
5738 NVGRE_TUNNEL /* NV-GRE Tunneling Microsoft L2 over GRE. GRE header contains mandatory Key Field. */,
5739 L2GRE_TUNNEL /* L2-GRE Tunneling General L2 over GRE. GRE can contain Key field with Tenant ID and Sequence Field */,
5740 IPGRE_TUNNEL /* IP-GRE Tunneling IP over GRE. GRE may contain Key field with Tenant ID, Sequence Field and/or Checksum Field */,
5741 MAX_GRE_TUNNEL_TYPE};
5745 * Dynamic Host-Coalescing - Driver(host) counters
5747 struct hc_dynamic_sb_drv_counters
5749 uint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES] /* Dynamic HC counters written by drivers */;
5754 * 2 bytes. configuration/state parameters for a single protocol index
5756 struct hc_index_data
5758 #if defined(__BIG_ENDIAN)
5760 #define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */
5761 #define HC_INDEX_DATA_SM_ID_SHIFT 0
5762 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */
5763 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5764 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */
5765 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5766 #define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */
5767 #define HC_INDEX_DATA_RESERVE_SHIFT 3
5768 uint8_t timeout /* the timeout values for this index. Units are 4 usec */;
5769 #elif defined(__LITTLE_ENDIAN)
5770 uint8_t timeout /* the timeout values for this index. Units are 4 usec */;
5772 #define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */
5773 #define HC_INDEX_DATA_SM_ID_SHIFT 0
5774 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */
5775 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5776 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */
5777 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5778 #define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */
5779 #define HC_INDEX_DATA_RESERVE_SHIFT 3
5787 struct hc_status_block_sm
5789 #if defined(__BIG_ENDIAN)
5791 uint8_t igu_sb_id /* sb_id within the IGU */;
5792 uint8_t timer_value /* Determines the time_to_expire */;
5794 #elif defined(__LITTLE_ENDIAN)
5796 uint8_t timer_value /* Determines the time_to_expire */;
5797 uint8_t igu_sb_id /* sb_id within the IGU */;
5800 uint32_t time_to_expire /* The time in which it expects to wake up */;
5804 * hold PCI identification variables- used in various places in firmware
5808 #if defined(__BIG_ENDIAN)
5809 uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */;
5810 uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */;
5811 uint8_t vnic_id /* Virtual NIC ID (0-3) */;
5812 uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */;
5813 #elif defined(__LITTLE_ENDIAN)
5814 uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */;
5815 uint8_t vnic_id /* Virtual NIC ID (0-3) */;
5816 uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */;
5817 uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */;
5822 * The fast-path status block meta-data, common to all chips
5826 struct regpair_native host_sb_addr /* Host status block address */;
5827 struct hc_status_block_sm state_machine[HC_SB_MAX_SM] /* Holds the state machines of the status block */;
5828 struct pci_entity p_func /* vnic / port of the status block to be set by the driver */;
5829 #if defined(__BIG_ENDIAN)
5832 uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */;
5833 uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */;
5834 #elif defined(__LITTLE_ENDIAN)
5835 uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */;
5836 uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */;
5840 struct regpair_native rsrv1[2];
5845 * Segment types for host coaslescing
5855 * The fast-path status block meta-data
5857 struct hc_sp_status_block_data
5859 struct regpair_native host_sb_addr /* Host status block address */;
5860 #if defined(__BIG_ENDIAN)
5863 uint8_t igu_seg_id /* segment id of the IGU */;
5864 uint8_t igu_sb_id /* sb_id within the IGU */;
5865 #elif defined(__LITTLE_ENDIAN)
5866 uint8_t igu_sb_id /* sb_id within the IGU */;
5867 uint8_t igu_seg_id /* segment id of the IGU */;
5871 struct pci_entity p_func /* vnic / port of the status block to be set by the driver */;
5876 * The fast-path status block meta-data
5878 struct hc_status_block_data_e1x
5880 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X] /* configuration/state parameters for a single protocol index */;
5881 struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */;
5886 * The fast-path status block meta-data
5888 struct hc_status_block_data_e2
5890 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2] /* configuration/state parameters for a single protocol index */;
5891 struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */;
5896 * IGU block operartion modes (in Everest2)
5900 HC_IGU_BC_MODE /* Backward compatible mode */,
5901 HC_IGU_NBC_MODE /* Non-backward compatible mode */,
5916 * Malicious VF error ID
5918 enum malicious_vf_error_id
5920 VF_PF_CHANNEL_NOT_READY /* Writing to VF/PF channel when it is not ready */,
5921 ETH_ILLEGAL_BD_LENGTHS /* TX BD lengths error was detected */,
5922 ETH_PACKET_TOO_SHORT /* TX packet is shorter then reported on BDs */,
5923 ETH_PAYLOAD_TOO_BIG /* TX packet is greater then MTU */,
5924 ETH_ILLEGAL_ETH_TYPE /* TX packet reported without VLAN but eth type is 0x8100 */,
5925 ETH_ILLEGAL_LSO_HDR_LEN /* LSO header length on BDs and on hdr_nbd do not match */,
5926 ETH_TOO_MANY_BDS /* Tx packet has too many BDs */,
5927 ETH_ZERO_HDR_NBDS /* hdr_nbds field is zero */,
5928 ETH_START_BD_NOT_SET /* start_bd should be set on first TX BD in packet */,
5929 ETH_ILLEGAL_PARSE_NBDS /* Tx packet with parse_nbds field which is not legal */,
5930 ETH_IPV6_AND_CHECKSUM /* Tx packet with IP checksum on IPv6 */,
5931 ETH_VLAN_FLG_INCORRECT /* Tx packet with incorrect VLAN flag */,
5932 ETH_ILLEGAL_LSO_MSS /* Tx LSO packet with illegal MSS value */,
5933 ETH_TUNNEL_NOT_SUPPORTED /* Tunneling packets are not supported in current connection */,
5934 MAX_MALICIOUS_VF_ERROR_ID};
5938 * Multi-function modes
5943 MULTI_FUNCTION_SD /* Switch dependent (vlan based) */,
5944 MULTI_FUNCTION_SI /* Switch independent (mac based) */,
5945 MULTI_FUNCTION_AFEX /* Switch dependent (niv based) */,
5950 * Protocol-common statistics collected by the Tstorm (per pf) $$KEEP_ENDIANNESS$$
5952 struct tstorm_per_pf_stats
5954 struct regpair rcv_error_bytes /* number of bytes received with errors */;
5958 * $$KEEP_ENDIANNESS$$
5962 struct tstorm_per_pf_stats tstorm_pf_statistics;
5967 * Protocol-common statistics collected by the Tstorm (per port) $$KEEP_ENDIANNESS$$
5969 struct tstorm_per_port_stats
5971 uint32_t mac_discard /* number of packets with mac errors */;
5972 uint32_t mac_filter_discard /* the number of good frames dropped because of no perfect match to MAC/VLAN address */;
5973 uint32_t brb_truncate_discard /* the number of packtes that were dropped because they were truncated in BRB */;
5974 uint32_t mf_tag_discard /* the number of good frames dropped because of no match to the outer vlan/VNtag */;
5975 uint32_t packet_drop /* general packet drop conter- incremented for every packet drop */;
5980 * $$KEEP_ENDIANNESS$$
5982 struct per_port_stats
5984 struct tstorm_per_port_stats tstorm_port_statistics;
5989 * Protocol-common statistics collected by the Tstorm (per client) $$KEEP_ENDIANNESS$$
5991 struct tstorm_per_queue_stats
5993 struct regpair rcv_ucast_bytes /* number of bytes in unicast packets received without errors and pass the filter */;
5994 uint32_t rcv_ucast_pkts /* number of unicast packets received without errors and pass the filter */;
5995 uint32_t checksum_discard /* number of total packets received with checksum error */;
5996 struct regpair rcv_bcast_bytes /* number of bytes in broadcast packets received without errors and pass the filter */;
5997 uint32_t rcv_bcast_pkts /* number of packets in broadcast packets received without errors and pass the filter */;
5998 uint32_t pkts_too_big_discard /* number of too long packets received */;
5999 struct regpair rcv_mcast_bytes /* number of bytes in multicast packets received without errors and pass the filter */;
6000 uint32_t rcv_mcast_pkts /* number of packets in multicast packets received without errors and pass the filter */;
6001 uint32_t ttl0_discard /* the number of good frames dropped because of TTL=0 */;
6002 uint16_t no_buff_discard;
6008 * Protocol-common statistics collected by the Ustorm (per client) $$KEEP_ENDIANNESS$$
6010 struct ustorm_per_queue_stats
6012 struct regpair ucast_no_buff_bytes /* the number of unicast bytes received from network dropped because of no buffer at host */;
6013 struct regpair mcast_no_buff_bytes /* the number of multicast bytes received from network dropped because of no buffer at host */;
6014 struct regpair bcast_no_buff_bytes /* the number of broadcast bytes received from network dropped because of no buffer at host */;
6015 uint32_t ucast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;
6016 uint32_t mcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;
6017 uint32_t bcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;
6018 uint32_t coalesced_pkts /* the number of packets coalesced in all aggregations */;
6019 struct regpair coalesced_bytes /* the number of bytes coalesced in all aggregations */;
6020 uint32_t coalesced_events /* the number of aggregations */;
6021 uint32_t coalesced_aborts /* the number of exception which avoid aggregation */;
6025 * Protocol-common statistics collected by the Xstorm (per client) $$KEEP_ENDIANNESS$$
6027 struct xstorm_per_queue_stats
6029 struct regpair ucast_bytes_sent /* number of total bytes sent without errors */;
6030 struct regpair mcast_bytes_sent /* number of total bytes sent without errors */;
6031 struct regpair bcast_bytes_sent /* number of total bytes sent without errors */;
6032 uint32_t ucast_pkts_sent /* number of total packets sent without errors */;
6033 uint32_t mcast_pkts_sent /* number of total packets sent without errors */;
6034 uint32_t bcast_pkts_sent /* number of total packets sent without errors */;
6035 uint32_t error_drop_pkts /* number of total packets drooped due to errors */;
6039 * $$KEEP_ENDIANNESS$$
6041 struct per_queue_stats
6043 struct tstorm_per_queue_stats tstorm_queue_statistics;
6044 struct ustorm_per_queue_stats ustorm_queue_statistics;
6045 struct xstorm_per_queue_stats xstorm_queue_statistics;
6050 * FW version stored in first line of pram $$KEEP_ENDIANNESS$$
6052 struct pram_fw_version
6054 uint8_t major /* firmware current major version */;
6055 uint8_t minor /* firmware current minor version */;
6056 uint8_t revision /* firmware current revision version */;
6057 uint8_t engineering /* firmware current engineering version */;
6059 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */
6060 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
6061 #define PRAM_FW_VERSION_STORM_ID (0x3<<1) /* BitField flags storm_id identification */
6062 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
6063 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) /* BitField flags if set, this is big-endien ASM */
6064 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
6065 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) /* BitField flags 1 - E1H */
6066 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
6067 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) /* BitField flags */
6068 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
6073 * Ethernet slow path element
6075 union protocol_common_specific_data
6077 uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */;
6078 struct regpair phy_address /* SPE physical address */;
6079 struct regpair mac_config_addr /* physical address of the MAC configuration command, as allocated by the driver */;
6080 struct afex_vif_list_ramrod_data afex_vif_list_data /* The data afex vif list ramrod need */;
6084 * The send queue element
6086 struct protocol_common_spe
6088 struct spe_hdr hdr /* SPE header */;
6089 union protocol_common_specific_data data /* data specific to common protocol */;
6094 * The data for the Set Timesync Ramrod $$KEEP_ENDIANNESS$$
6096 struct set_timesync_ramrod_data
6098 uint8_t drift_adjust_cmd /* Timesync Drift Adjust Command */;
6099 uint8_t offset_cmd /* Timesync Offset Command */;
6100 uint8_t add_sub_drift_adjust_value /* Whether to add(1)/subtract(0) Drift Adjust Value from the Offset */;
6101 uint8_t drift_adjust_value /* Drift Adjust Value (in ns) */;
6102 uint32_t drift_adjust_period /* Drift Adjust Period (in us) */;
6103 struct regpair offset_delta /* Timesync Offset Delta (in ns) */;
6108 * The send queue element
6110 struct slow_path_element
6112 struct spe_hdr hdr /* common data for all protocols */;
6113 struct regpair protocol_data /* additional data specific to the protocol */;
6118 * Protocol-common statistics counter $$KEEP_ENDIANNESS$$
6120 struct stats_counter
6122 uint16_t xstats_counter /* xstorm statistics counter */;
6125 uint16_t tstats_counter /* tstorm statistics counter */;
6128 uint16_t ustats_counter /* ustorm statistics counter */;
6131 uint16_t cstats_counter /* ustorm statistics counter */;
6138 * $$KEEP_ENDIANNESS$$
6140 struct stats_query_entry
6143 uint8_t index /* queue index */;
6144 uint16_t funcID /* the func the statistic will send to */;
6146 struct regpair address /* pxp address */;
6150 * statistic command $$KEEP_ENDIANNESS$$
6152 struct stats_query_cmd_group
6154 struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
6159 * statistic command header $$KEEP_ENDIANNESS$$
6161 struct stats_query_header
6163 uint8_t cmd_num /* command number */;
6165 uint16_t drv_stats_counter;
6167 struct regpair stats_counters_addrs /* stats counter */;
6172 * Types of statistcis query entry
6174 enum stats_query_type
6181 MAX_STATS_QUERY_TYPE};
6185 * Indicate of the function status block state
6187 enum status_block_state
6192 MAX_STATUS_BLOCK_STATE};
6196 * Storm IDs (including attentions for IGU related enums)
6209 * Taffic types used in ETS and flow control algorithms
6213 LLFC_TRAFFIC_TYPE_NW /* Networking */,
6214 LLFC_TRAFFIC_TYPE_FCOE /* FCoE */,
6215 LLFC_TRAFFIC_TYPE_ISCSI /* iSCSI */,
6220 * zone A per-queue data
6222 struct tstorm_queue_zone_data
6224 struct regpair reserved[4];
6229 * zone B per-VF data
6231 struct tstorm_vf_zone_data
6233 struct regpair reserved;
6238 * Add or Subtract Value for Set Timesync Ramrod
6240 enum ts_add_sub_value
6242 TS_SUB_VALUE /* Subtract Value */,
6243 TS_ADD_VALUE /* Add Value */,
6244 MAX_TS_ADD_SUB_VALUE};
6248 * Drift-Adjust Commands for Set Timesync Ramrod
6250 enum ts_drift_adjust_cmd
6252 TS_DRIFT_ADJUST_KEEP /* Keep Drift-Adjust at current values */,
6253 TS_DRIFT_ADJUST_SET /* Set Drift-Adjust */,
6254 TS_DRIFT_ADJUST_RESET /* Reset Drift-Adjust */,
6255 MAX_TS_DRIFT_ADJUST_CMD};
6259 * Offset Commands for Set Timesync Ramrod
6263 TS_OFFSET_KEEP /* Keep Offset at current values */,
6264 TS_OFFSET_INC /* Increase Offset by Offset Delta */,
6265 TS_OFFSET_DEC /* Decrease Offset by Offset Delta */,
6270 * zone A per-queue data
6272 struct ustorm_queue_zone_data
6274 union ustorm_eth_rx_producers eth_rx_producers /* ETH RX rings producers */;
6275 struct regpair reserved[3];
6280 * zone B per-VF data
6282 struct ustorm_vf_zone_data
6284 struct regpair reserved;
6289 * data per VF-PF channel
6291 struct vf_pf_channel_data
6293 #if defined(__BIG_ENDIAN)
6295 uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */;
6296 uint8_t state /* channel state (ready / waiting for ack) */;
6297 #elif defined(__LITTLE_ENDIAN)
6298 uint8_t state /* channel state (ready / waiting for ack) */;
6299 uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */;
6307 * State of VF-PF channel
6309 enum vf_pf_channel_state
6311 VF_PF_CHANNEL_STATE_READY /* Channel is ready to accept a message from VF */,
6312 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK /* Channel waits for an ACK from PF */,
6313 MAX_VF_PF_CHANNEL_STATE};
6317 * vif_list_rule_kind
6319 enum vif_list_rule_kind
6323 VIF_LIST_RULE_CLEAR_ALL,
6324 VIF_LIST_RULE_CLEAR_FUNC,
6325 MAX_VIF_LIST_RULE_KIND};
6329 * zone A per-queue data
6331 struct xstorm_queue_zone_data
6333 struct regpair reserved[4];
6338 * zone B per-VF data
6340 struct xstorm_vf_zone_data
6342 struct regpair reserved;
6346 #endif /* ECORE_HSI_H */