1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
7 #ifndef __ECORE_HSI_DEBUG_TOOLS__
8 #define __ECORE_HSI_DEBUG_TOOLS__
9 /****************************************/
10 /* Debug Tools HSI constants and macros */
11 /****************************************/
102 BLOCK_NIG_LB_FC_PLLH,
103 BLOCK_NIG_TX_FC_PLLH,
105 BLOCK_NIG_RX_FC_PLLH,
112 * binary debug buffer types
114 enum bin_dbg_buffer_type {
115 BIN_BUF_DBG_MODE_TREE /* init modes tree */,
116 BIN_BUF_DBG_DUMP_REG /* GRC Dump registers */,
117 BIN_BUF_DBG_DUMP_MEM /* GRC Dump memories */,
118 BIN_BUF_DBG_IDLE_CHK_REGS /* Idle Check registers */,
119 BIN_BUF_DBG_IDLE_CHK_IMMS /* Idle Check immediates */,
120 BIN_BUF_DBG_IDLE_CHK_RULES /* Idle Check rules */,
121 BIN_BUF_DBG_IDLE_CHK_PARSING_DATA /* Idle Check parsing data */,
122 BIN_BUF_DBG_ATTN_BLOCKS /* Attention blocks */,
123 BIN_BUF_DBG_ATTN_REGS /* Attention registers */,
124 BIN_BUF_DBG_ATTN_INDEXES /* Attention indexes */,
125 BIN_BUF_DBG_ATTN_NAME_OFFSETS /* Attention name offsets */,
126 BIN_BUF_DBG_BLOCKS /* Blocks debug data */,
127 BIN_BUF_DBG_BLOCKS_CHIP_DATA /* Blocks debug chip data */,
128 BIN_BUF_DBG_BUS_LINES /* Blocks debug bus lines */,
129 BIN_BUF_DBG_BLOCKS_USER_DATA /* Blocks debug user data */,
130 BIN_BUF_DBG_BLOCKS_CHIP_USER_DATA /* Blocks debug chip user data */,
131 BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS /* Debug Bus line name offsets */,
132 BIN_BUF_DBG_RESET_REGS /* Reset registers */,
133 BIN_BUF_DBG_PARSING_STRINGS /* Debug Tools parsing strings */,
134 MAX_BIN_DBG_BUFFER_TYPE
139 * Attention bit mapping
141 struct dbg_attn_bit_mapping {
143 /* The index of an attention in the blocks attentions list
144 * (if is_unused_bit_cnt=0), or a number of consecutive unused attention bits
145 * (if is_unused_bit_cnt=1)
147 #define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF
148 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0
149 /* if set, the val field indicates the number of consecutive unused attention
152 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1
153 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15
158 * Attention block per-type data
160 struct dbg_attn_block_type_data {
161 /* Offset of this block attention names in the debug attention name offsets
166 u8 num_regs /* Number of attention registers in this block */;
168 /* Offset of this blocks attention registers in the attention registers array
169 * (in dbg_attn_reg units)
177 struct dbg_attn_block {
178 /* attention block per-type data. Count must match the number of elements in
181 struct dbg_attn_block_type_data per_type_data[2];
186 * Attention register result
188 struct dbg_attn_reg_result {
190 /* STS attention register GRC address (in dwords) */
191 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF
192 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0
193 /* Number of attention indexes in this register */
194 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF
195 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT 24
196 /* The offset of this registers attentions within the blocks attentions list
197 * (a value in the range 0..number of block attentions-1)
199 u16 block_attn_offset;
201 u32 sts_val /* Value read from the STS attention register */;
202 u32 mask_val /* Value read from the MASK attention register */;
206 * Attention block result
208 struct dbg_attn_block_result {
209 u8 block_id /* Registers block ID */;
211 /* Value from dbg_attn_type enum */
212 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3
213 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0
214 /* Number of registers in block in which at least one attention bit is set */
215 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F
216 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2
217 /* Offset of this registers block attention names in the attention name offsets
221 /* result data for each register in the block in which at least one attention
224 struct dbg_attn_reg_result reg_results[15];
232 struct dbg_mode_hdr {
234 /* indicates if a mode expression should be evaluated (0/1) */
235 #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1
236 #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0
237 /* offset (in bytes) in modes expression buffer. valid only if eval_mode is
240 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF
241 #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1
247 struct dbg_attn_reg {
248 struct dbg_mode_hdr mode /* Mode header */;
249 /* The offset of this registers attentions within the blocks attentions list
250 * (a value in the range 0..number of block attentions-1)
252 u16 block_attn_offset;
254 /* STS attention register GRC address (in dwords) */
255 #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF
256 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0
257 /* Number of attention in this register */
258 #define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF
259 #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24
260 /* STS_CLR attention register GRC address (in dwords) */
262 u32 mask_address /* MASK attention register GRC address (in dwords) */;
281 u8 name[15] /* Block name */;
282 /* The letter (char) of the associated Storm, or 0 if no associated Storm. */
283 u8 associated_storm_letter;
288 * Chip-specific block debug data
290 struct dbg_block_chip {
292 /* Indicates if the block is removed in this chip (0/1). */
293 #define DBG_BLOCK_CHIP_IS_REMOVED_MASK 0x1
294 #define DBG_BLOCK_CHIP_IS_REMOVED_SHIFT 0
295 /* Indicates if this block has a reset register (0/1). */
296 #define DBG_BLOCK_CHIP_HAS_RESET_REG_MASK 0x1
297 #define DBG_BLOCK_CHIP_HAS_RESET_REG_SHIFT 1
298 /* Indicates if this block should be taken out of reset before GRC Dump (0/1).
299 * Valid only if has_reset_reg is set.
301 #define DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP_MASK 0x1
302 #define DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP_SHIFT 2
303 /* Indicates if this block has a debug bus (0/1). */
304 #define DBG_BLOCK_CHIP_HAS_DBG_BUS_MASK 0x1
305 #define DBG_BLOCK_CHIP_HAS_DBG_BUS_SHIFT 3
306 /* Indicates if this block has a latency events debug line (0/1). Valid only
307 * if has_dbg_bus is set.
309 #define DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS_MASK 0x1
310 #define DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS_SHIFT 4
311 #define DBG_BLOCK_CHIP_RESERVED0_MASK 0x7
312 #define DBG_BLOCK_CHIP_RESERVED0_SHIFT 5
313 /* The DBG block client ID of this block/chip. Valid only if has_dbg_bus is
317 /* The ID of the reset register of this block/chip in the dbg_reset_reg
321 /* The bit offset of this block/chip in the reset register. Valid only if
322 * has_reset_reg is set.
324 u8 reset_reg_bit_offset;
325 struct dbg_mode_hdr dbg_bus_mode /* Mode header */;
328 /* Number of Debug Bus lines in this block/chip (excluding signature and latency
329 * events). Valid only if has_dbg_bus is set.
331 u8 num_of_dbg_bus_lines;
332 /* Offset of this block/chip Debug Bus lines in the Debug Bus lines array. Valid
333 * only if has_dbg_bus is set.
335 u16 dbg_bus_lines_offset;
336 /* GRC address of the Debug Bus dbg_select register (in dwords). Valid only if
337 * has_dbg_bus is set.
339 u32 dbg_select_reg_addr;
340 /* GRC address of the Debug Bus dbg_dword_enable register (in dwords). Valid
341 * only if has_dbg_bus is set.
343 u32 dbg_dword_enable_reg_addr;
344 /* GRC address of the Debug Bus dbg_shift register (in dwords). Valid only if
345 * has_dbg_bus is set.
347 u32 dbg_shift_reg_addr;
348 /* GRC address of the Debug Bus dbg_force_valid register (in dwords). Valid only
349 * if has_dbg_bus is set.
351 u32 dbg_force_valid_reg_addr;
352 /* GRC address of the Debug Bus dbg_force_frame register (in dwords). Valid only
353 * if has_dbg_bus is set.
355 u32 dbg_force_frame_reg_addr;
360 * Chip-specific block user debug data
362 struct dbg_block_chip_user {
363 /* Number of debug bus lines in this block (excluding signature and latency
366 u8 num_of_dbg_bus_lines;
367 /* Indicates if this block has a latency events debug line (0/1). */
368 u8 has_latency_events;
369 /* Offset of this blocks lines in the debug bus line name offsets array. */
375 * Block user debug data
377 struct dbg_block_user {
378 u8 name[16] /* Block name */;
383 * Block Debug line data
385 struct dbg_bus_line {
387 /* Number of groups in the line (0-3) */
388 #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF
389 #define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0
390 /* Indicates if this is a 128b line (0) or a 256b line (1). */
391 #define DBG_BUS_LINE_IS_256B_MASK 0x1
392 #define DBG_BUS_LINE_IS_256B_SHIFT 4
393 #define DBG_BUS_LINE_RESERVED_MASK 0x7
394 #define DBG_BUS_LINE_RESERVED_SHIFT 5
395 /* Four 2-bit values, indicating the size of each group minus 1 (i.e.
396 * value=0 means size=1, value=1 means size=2, etc), starting from lsb.
397 * The sizes are in dwords (if is_256b=0) or in qwords (if is_256b=1).
404 * condition header for registers dump
406 struct dbg_dump_cond_hdr {
407 struct dbg_mode_hdr mode /* Mode header */;
408 u8 block_id /* block ID */;
409 u8 data_size /* size in dwords of the data following this header */;
414 * memory data for registers dump
416 struct dbg_dump_mem {
418 /* register address (in dwords) */
419 #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF
420 #define DBG_DUMP_MEM_ADDRESS_SHIFT 0
421 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF /* memory group ID */
422 #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24
424 /* register size (in dwords) */
425 #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF
426 #define DBG_DUMP_MEM_LENGTH_SHIFT 0
427 /* indicates if the register is wide-bus */
428 #define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1
429 #define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24
430 #define DBG_DUMP_MEM_RESERVED_MASK 0x7F
431 #define DBG_DUMP_MEM_RESERVED_SHIFT 25
436 * register data for registers dump
438 struct dbg_dump_reg {
440 /* register address (in dwords) */
441 #define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF /* register address (in dwords) */
442 #define DBG_DUMP_REG_ADDRESS_SHIFT 0
443 /* indicates if the register is wide-bus */
444 #define DBG_DUMP_REG_WIDE_BUS_MASK 0x1
445 #define DBG_DUMP_REG_WIDE_BUS_SHIFT 23
446 #define DBG_DUMP_REG_LENGTH_MASK 0xFF /* register size (in dwords) */
447 #define DBG_DUMP_REG_LENGTH_SHIFT 24
452 * split header for registers dump
454 struct dbg_dump_split_hdr {
456 /* size in dwords of the data following this header */
457 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF
458 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0
459 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF /* split type ID */
460 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24
465 * condition header for idle check
467 struct dbg_idle_chk_cond_hdr {
468 struct dbg_mode_hdr mode /* Mode header */;
469 u16 data_size /* size in dwords of the data following this header */;
474 * Idle Check condition register
476 struct dbg_idle_chk_cond_reg {
478 /* Register GRC address (in dwords) */
479 #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF
480 #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0
481 /* indicates if the register is wide-bus */
482 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1
483 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23
484 /* value from block_id enum */
485 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF
486 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24
487 u16 num_entries /* number of registers entries to check */;
488 u8 entry_size /* size of registers entry (in dwords) */;
489 u8 start_entry /* index of the first entry to check */;
494 * Idle Check info register
496 struct dbg_idle_chk_info_reg {
498 /* Register GRC address (in dwords) */
499 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF
500 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0
501 /* indicates if the register is wide-bus */
502 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1
503 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23
504 /* value from block_id enum */
505 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF
506 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24
507 u16 size /* register size in dwords */;
508 struct dbg_mode_hdr mode /* Mode header */;
513 * Idle Check register
515 union dbg_idle_chk_reg {
516 struct dbg_idle_chk_cond_reg cond_reg /* condition register */;
517 struct dbg_idle_chk_info_reg info_reg /* info register */;
522 * Idle Check result header
524 struct dbg_idle_chk_result_hdr {
525 u16 rule_id /* Failing rule index */;
526 u16 mem_entry_id /* Failing memory entry index */;
527 u8 num_dumped_cond_regs /* number of dumped condition registers */;
528 u8 num_dumped_info_regs /* number of dumped condition registers */;
529 u8 severity /* from dbg_idle_chk_severity_types enum */;
535 * Idle Check result register header
537 struct dbg_idle_chk_result_reg_hdr {
539 /* indicates if this register is a memory */
540 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1
541 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0
542 /* register index within the failing rule */
543 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F
544 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1
545 u8 start_entry /* index of the first checked entry */;
546 u16 size /* register size in dwords */;
553 struct dbg_idle_chk_rule {
554 u16 rule_id /* Idle Check rule ID */;
555 u8 severity /* value from dbg_idle_chk_severity_types enum */;
556 u8 cond_id /* Condition ID */;
557 u8 num_cond_regs /* number of condition registers */;
558 u8 num_info_regs /* number of info registers */;
559 u8 num_imms /* number of immediates in the condition */;
561 /* offset of this rules registers in the idle check register array
562 * (in dbg_idle_chk_reg units)
565 /* offset of this rules immediate values in the immediate values array
573 * Idle Check rule parsing data
575 struct dbg_idle_chk_rule_parsing_data {
577 /* indicates if this register has a FW message */
578 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1
579 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0
580 /* Offset of this rules strings in the debug strings array (in bytes) */
581 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF
582 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1
587 * idle check severity types
589 enum dbg_idle_chk_severity_types {
590 /* idle check failure should cause an error */
591 IDLE_CHK_SEVERITY_ERROR,
592 /* idle check failure should cause an error only if theres no traffic */
593 IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
594 /* idle check failure should cause a warning */
595 IDLE_CHK_SEVERITY_WARNING,
596 MAX_DBG_IDLE_CHK_SEVERITY_TYPES
604 struct dbg_reset_reg {
606 #define DBG_RESET_REG_ADDR_MASK 0xFFFFFF /* GRC address (in dwords) */
607 #define DBG_RESET_REG_ADDR_SHIFT 0
608 /* indicates if this register is removed (0/1). */
609 #define DBG_RESET_REG_IS_REMOVED_MASK 0x1
610 #define DBG_RESET_REG_IS_REMOVED_SHIFT 24
611 #define DBG_RESET_REG_RESERVED_MASK 0x7F
612 #define DBG_RESET_REG_RESERVED_SHIFT 25
617 * Debug Bus block data
619 struct dbg_bus_block_data {
620 /* 4 bit value, bit i set -> dword/qword i is enabled in block. */
622 /* Number of dwords/qwords to cyclically right the blocks output (0-3). */
624 /* 4 bit value, bit i set -> dword/qword i is forced valid in block. */
626 /* 4 bit value, bit i set -> dword/qword i frame bit is forced in block. */
628 /* bit i set -> dword i contains this blocks data (after shifting). */
630 u8 line_num /* Debug line number to select */;
631 u8 hw_id /* HW ID associated with the block */;
633 /* 0/1. If 1, the debug line is 256b, otherwise its 128b. */
634 #define DBG_BUS_BLOCK_DATA_IS_256B_LINE_MASK 0x1
635 #define DBG_BUS_BLOCK_DATA_IS_256B_LINE_SHIFT 0
636 #define DBG_BUS_BLOCK_DATA_RESERVED_MASK 0x7F
637 #define DBG_BUS_BLOCK_DATA_RESERVED_SHIFT 1
642 * Debug Bus constraint operation types
644 enum dbg_bus_constraint_ops {
645 DBG_BUS_CONSTRAINT_OP_EQ /* equal */,
646 DBG_BUS_CONSTRAINT_OP_NE /* not equal */,
647 DBG_BUS_CONSTRAINT_OP_LT /* less than */,
648 DBG_BUS_CONSTRAINT_OP_LTC /* less than (cyclic) */,
649 DBG_BUS_CONSTRAINT_OP_LE /* less than or equal */,
650 DBG_BUS_CONSTRAINT_OP_LEC /* less than or equal (cyclic) */,
651 DBG_BUS_CONSTRAINT_OP_GT /* greater than */,
652 DBG_BUS_CONSTRAINT_OP_GTC /* greater than (cyclic) */,
653 DBG_BUS_CONSTRAINT_OP_GE /* greater than or equal */,
654 DBG_BUS_CONSTRAINT_OP_GEC /* greater than or equal (cyclic) */,
655 MAX_DBG_BUS_CONSTRAINT_OPS
660 * Debug Bus trigger state data
662 struct dbg_bus_trigger_state_data {
663 /* Message length (in cycles) to be used for message-based trigger constraints.
664 * If set to 0, message length is based only on frame bit received from HW.
667 /* A bit for each dword in the debug bus cycle, indicating if this dword appears
668 * in a trigger constraint (1) or not (0)
670 u8 constraint_dword_mask;
671 /* Storm ID to trigger on. Valid only when triggering on Storm data.
672 * (use enum dbg_storms)
679 * Debug Bus memory address
681 struct dbg_bus_mem_addr {
687 * Debug Bus PCI buffer data
689 struct dbg_bus_pci_buf_data {
690 struct dbg_bus_mem_addr phys_addr /* PCI buffer physical address */;
691 struct dbg_bus_mem_addr virt_addr /* PCI buffer virtual address */;
692 u32 size /* PCI buffer size in bytes */;
696 * Debug Bus Storm EID range filter params
698 struct dbg_bus_storm_eid_range_params {
699 u8 min /* Minimal event ID to filter on */;
700 u8 max /* Maximal event ID to filter on */;
704 * Debug Bus Storm EID mask filter params
706 struct dbg_bus_storm_eid_mask_params {
707 u8 val /* Event ID value */;
708 u8 mask /* Event ID mask. 1s in the mask = dont care bits. */;
712 * Debug Bus Storm EID filter params
714 union dbg_bus_storm_eid_params {
715 /* EID range filter params */
716 struct dbg_bus_storm_eid_range_params range;
717 /* EID mask filter params */
718 struct dbg_bus_storm_eid_mask_params mask;
722 * Debug Bus Storm data
724 struct dbg_bus_storm_data {
725 u8 enabled /* indicates if the Storm is enabled for recording */;
726 u8 mode /* Storm debug mode, valid only if the Storm is enabled */;
727 u8 hw_id /* HW ID associated with the Storm */;
728 u8 eid_filter_en /* Indicates if EID filtering is performed (0/1) */;
729 /* 1 = EID range filter, 0 = EID mask filter. Valid only if eid_filter_en is
732 u8 eid_range_not_mask;
733 u8 cid_filter_en /* Indicates if CID filtering is performed (0/1) */;
734 /* EID filter params to filter on. Valid only if eid_filter_en is set. */
735 union dbg_bus_storm_eid_params eid_filter_params;
736 u32 cid /* CID to filter on. Valid only if cid_filter_en is set. */;
742 struct dbg_bus_data {
743 u32 app_version /* The tools version number of the application */;
744 u8 state /* The current debug bus state */;
745 u8 mode_256b_en /* Indicates if the 256 bit mode is enabled */;
746 u8 num_enabled_blocks /* Number of blocks enabled for recording */;
747 u8 num_enabled_storms /* Number of Storms enabled for recording */;
748 u8 target /* Output target */;
749 u8 one_shot_en /* Indicates if one-shot mode is enabled (0/1) */;
750 u8 grc_input_en /* Indicates if GRC recording is enabled (0/1) */;
751 /* Indicates if timestamp recording is enabled (0/1) */
752 u8 timestamp_input_en;
753 u8 filter_en /* Indicates if the recording filter is enabled (0/1) */;
754 /* If true, the next added constraint belong to the filter. Otherwise,
755 * it belongs to the last added trigger state. Valid only if either filter or
756 * triggers are enabled.
759 /* Indicates if the recording filter should be applied before the trigger.
760 * Valid only if both filter and trigger are enabled (0/1)
762 u8 filter_pre_trigger;
763 /* Indicates if the recording filter should be applied after the trigger.
764 * Valid only if both filter and trigger are enabled (0/1)
766 u8 filter_post_trigger;
767 /* Indicates if the recording trigger is enabled (0/1) */
769 /* A bit for each dword in the debug bus cycle, indicating if this dword
770 * appears in a filter constraint (1) or not (0)
772 u8 filter_constraint_dword_mask;
773 u8 next_trigger_state /* ID of next trigger state to be added */;
774 /* ID of next filter/trigger constraint to be added */
775 u8 next_constraint_id;
776 /* trigger states data */
777 struct dbg_bus_trigger_state_data trigger_states[3];
778 /* Message length (in cycles) to be used for message-based filter constraints.
779 * If set to 0 message length is based only on frame bit received from HW.
782 /* Indicates if the other engine sends it NW recording to this engine (0/1) */
783 u8 rcv_from_other_engine;
784 /* A bit for each dword in the debug bus cycle, indicating if this dword is
785 * recorded (1) or not (0)
787 u8 blocks_dword_mask;
788 /* Indicates if there are dwords in the debug bus cycle which are recorded
789 * by more tan one block (0/1)
791 u8 blocks_dword_overlap;
792 /* The HW IDs of the recorded HW blocks, where bits i*3..i*3+2 contain the
793 * HW ID of dword/qword i
796 /* Debug Bus PCI buffer data. Valid only when the target is
797 * DBG_BUS_TARGET_ID_PCI.
799 struct dbg_bus_pci_buf_data pci_buf;
800 /* Debug Bus data for each block */
801 struct dbg_bus_block_data blocks[132];
802 /* Debug Bus data for each block */
803 struct dbg_bus_storm_data storms[6];
810 enum dbg_bus_states {
811 DBG_BUS_STATE_IDLE /* debug bus idle state (not recording) */,
812 /* debug bus is ready for configuration and recording */
814 DBG_BUS_STATE_RECORDING /* debug bus is currently recording */,
815 DBG_BUS_STATE_STOPPED /* debug bus recording has stopped */,
825 * Debug Bus Storm modes
827 enum dbg_bus_storm_modes {
828 DBG_BUS_STORM_MODE_PRINTF /* store data (fast debug) */,
829 DBG_BUS_STORM_MODE_PRAM_ADDR /* pram address (fast debug) */,
830 DBG_BUS_STORM_MODE_DRA_RW /* DRA read/write data (fast debug) */,
831 DBG_BUS_STORM_MODE_DRA_W /* DRA write data (fast debug) */,
832 DBG_BUS_STORM_MODE_LD_ST_ADDR /* load/store address (fast debug) */,
833 DBG_BUS_STORM_MODE_DRA_FSM /* DRA state machines (fast debug) */,
834 DBG_BUS_STORM_MODE_RH /* recording handlers (fast debug) */,
835 /* recording handlers with store messages (fast debug) */
836 DBG_BUS_STORM_MODE_RH_WITH_STORE,
837 DBG_BUS_STORM_MODE_FOC /* FOC: FIN + DRA Rd (slow debug) */,
838 DBG_BUS_STORM_MODE_EXT_STORE /* FOC: External Store (slow) */,
839 MAX_DBG_BUS_STORM_MODES
844 * Debug bus target IDs
846 enum dbg_bus_targets {
847 /* records debug bus to DBG block internal buffer */
848 DBG_BUS_TARGET_ID_INT_BUF,
849 DBG_BUS_TARGET_ID_NIG /* records debug bus to the NW */,
850 DBG_BUS_TARGET_ID_PCI /* records debug bus to a PCI buffer */,
859 struct dbg_grc_data {
860 /* Indicates if the GRC parameters were initialized */
861 u8 params_initialized;
864 /* Value of each GRC parameter. Array size must match the enum dbg_grc_params.
873 enum dbg_grc_params {
874 DBG_GRC_PARAM_DUMP_TSTORM /* dump Tstorm memories (0/1) */,
875 DBG_GRC_PARAM_DUMP_MSTORM /* dump Mstorm memories (0/1) */,
876 DBG_GRC_PARAM_DUMP_USTORM /* dump Ustorm memories (0/1) */,
877 DBG_GRC_PARAM_DUMP_XSTORM /* dump Xstorm memories (0/1) */,
878 DBG_GRC_PARAM_DUMP_YSTORM /* dump Ystorm memories (0/1) */,
879 DBG_GRC_PARAM_DUMP_PSTORM /* dump Pstorm memories (0/1) */,
880 DBG_GRC_PARAM_DUMP_REGS /* dump non-memory registers (0/1) */,
881 DBG_GRC_PARAM_DUMP_RAM /* dump Storm internal RAMs (0/1) */,
882 DBG_GRC_PARAM_DUMP_PBUF /* dump Storm passive buffer (0/1) */,
883 DBG_GRC_PARAM_DUMP_IOR /* dump Storm IORs (0/1) */,
884 DBG_GRC_PARAM_DUMP_VFC /* dump VFC memories (0/1) */,
885 DBG_GRC_PARAM_DUMP_CM_CTX /* dump CM contexts (0/1) */,
886 DBG_GRC_PARAM_DUMP_PXP /* dump PXP memories (0/1) */,
887 DBG_GRC_PARAM_DUMP_RSS /* dump RSS memories (0/1) */,
888 DBG_GRC_PARAM_DUMP_CAU /* dump CAU memories (0/1) */,
889 DBG_GRC_PARAM_DUMP_QM /* dump QM memories (0/1) */,
890 DBG_GRC_PARAM_DUMP_MCP /* dump MCP memories (0/1) */,
891 DBG_GRC_PARAM_DUMP_DORQ /* dump DORQ memories (0/1) */,
892 DBG_GRC_PARAM_DUMP_CFC /* dump CFC memories (0/1) */,
893 DBG_GRC_PARAM_DUMP_IGU /* dump IGU memories (0/1) */,
894 DBG_GRC_PARAM_DUMP_BRB /* dump BRB memories (0/1) */,
895 DBG_GRC_PARAM_DUMP_BTB /* dump BTB memories (0/1) */,
896 DBG_GRC_PARAM_DUMP_BMB /* dump BMB memories (0/1) */,
897 DBG_GRC_PARAM_RESERVD1 /* reserved */,
898 DBG_GRC_PARAM_DUMP_MULD /* dump MULD memories (0/1) */,
899 DBG_GRC_PARAM_DUMP_PRS /* dump PRS memories (0/1) */,
900 DBG_GRC_PARAM_DUMP_DMAE /* dump PRS memories (0/1) */,
901 DBG_GRC_PARAM_DUMP_TM /* dump TM (timers) memories (0/1) */,
902 DBG_GRC_PARAM_DUMP_SDM /* dump SDM memories (0/1) */,
903 DBG_GRC_PARAM_DUMP_DIF /* dump DIF memories (0/1) */,
904 DBG_GRC_PARAM_DUMP_STATIC /* dump static debug data (0/1) */,
905 DBG_GRC_PARAM_UNSTALL /* un-stall Storms after dump (0/1) */,
906 DBG_GRC_PARAM_RESERVED2 /* reserved */,
907 /* MCP Trace meta data size in bytes */
908 DBG_GRC_PARAM_MCP_TRACE_META_SIZE,
909 /* preset: exclude all memories from dump (1 only) */
910 DBG_GRC_PARAM_EXCLUDE_ALL,
911 /* preset: include memories for crash dump (1 only) */
913 /* perform dump only if MFW is responding (0/1) */
914 DBG_GRC_PARAM_PARITY_SAFE,
915 DBG_GRC_PARAM_DUMP_CM /* dump CM memories (0/1) */,
916 DBG_GRC_PARAM_DUMP_PHY /* dump PHY memories (0/1) */,
917 DBG_GRC_PARAM_NO_MCP /* dont perform MCP commands (0/1) */,
918 DBG_GRC_PARAM_NO_FW_VER /* dont read FW/MFW version (0/1) */,
919 DBG_GRC_PARAM_RESERVED3 /* reserved */,
920 DBG_GRC_PARAM_DUMP_MCP_HW_DUMP /* dump MCP HW Dump (0/1) */,
921 DBG_GRC_PARAM_DUMP_ILT_CDUC /* dump ILT CDUC client (0/1) */,
922 DBG_GRC_PARAM_DUMP_ILT_CDUT /* dump ILT CDUT client (0/1) */,
923 DBG_GRC_PARAM_DUMP_CAU_EXT /* dump CAU extended memories (0/1) */,
933 DBG_STATUS_APP_VERSION_NOT_SET,
934 DBG_STATUS_UNSUPPORTED_APP_VERSION,
935 DBG_STATUS_DBG_BLOCK_NOT_RESET,
936 DBG_STATUS_INVALID_ARGS,
937 DBG_STATUS_OUTPUT_ALREADY_SET,
938 DBG_STATUS_INVALID_PCI_BUF_SIZE,
939 DBG_STATUS_PCI_BUF_ALLOC_FAILED,
940 DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
941 DBG_STATUS_INVALID_FILTER_TRIGGER_DWORDS,
942 DBG_STATUS_NO_MATCHING_FRAMING_MODE,
943 DBG_STATUS_VFC_READ_ERROR,
944 DBG_STATUS_STORM_ALREADY_ENABLED,
945 DBG_STATUS_STORM_NOT_ENABLED,
946 DBG_STATUS_BLOCK_ALREADY_ENABLED,
947 DBG_STATUS_BLOCK_NOT_ENABLED,
948 DBG_STATUS_NO_INPUT_ENABLED,
949 DBG_STATUS_NO_FILTER_TRIGGER_256B,
950 DBG_STATUS_FILTER_ALREADY_ENABLED,
951 DBG_STATUS_TRIGGER_ALREADY_ENABLED,
952 DBG_STATUS_TRIGGER_NOT_ENABLED,
953 DBG_STATUS_CANT_ADD_CONSTRAINT,
954 DBG_STATUS_TOO_MANY_TRIGGER_STATES,
955 DBG_STATUS_TOO_MANY_CONSTRAINTS,
956 DBG_STATUS_RECORDING_NOT_STARTED,
957 DBG_STATUS_DATA_DIDNT_TRIGGER,
958 DBG_STATUS_NO_DATA_RECORDED,
959 DBG_STATUS_DUMP_BUF_TOO_SMALL,
960 DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
961 DBG_STATUS_UNKNOWN_CHIP,
962 DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
963 DBG_STATUS_BLOCK_IN_RESET,
964 DBG_STATUS_INVALID_TRACE_SIGNATURE,
965 DBG_STATUS_INVALID_NVRAM_BUNDLE,
966 DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
967 DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
968 DBG_STATUS_NVRAM_READ_FAILED,
969 DBG_STATUS_IDLE_CHK_PARSE_FAILED,
970 DBG_STATUS_MCP_TRACE_BAD_DATA,
971 DBG_STATUS_MCP_TRACE_NO_META,
972 DBG_STATUS_MCP_COULD_NOT_HALT,
973 DBG_STATUS_MCP_COULD_NOT_RESUME,
974 DBG_STATUS_RESERVED0,
975 DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
976 DBG_STATUS_IGU_FIFO_BAD_DATA,
977 DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
978 DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
979 DBG_STATUS_REG_FIFO_BAD_DATA,
980 DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
981 DBG_STATUS_DBG_ARRAY_NOT_SET,
982 DBG_STATUS_RESERVED1,
983 DBG_STATUS_NON_MATCHING_LINES,
984 DBG_STATUS_INSUFFICIENT_HW_IDS,
985 DBG_STATUS_DBG_BUS_IN_USE,
986 DBG_STATUS_INVALID_STORM_DBG_MODE,
987 DBG_STATUS_OTHER_ENGINE_BB_ONLY,
988 DBG_STATUS_FILTER_SINGLE_HW_ID,
989 DBG_STATUS_TRIGGER_SINGLE_HW_ID,
990 DBG_STATUS_MISSING_TRIGGER_STATE_STORM,
1012 struct idle_chk_data {
1013 u32 buf_size /* Idle check buffer size in dwords */;
1014 /* Indicates if the idle check buffer size was set (0/1) */
1021 * Pretend parameters
1023 struct pretend_params {
1024 u8 split_type /* Pretend split type (from enum init_split_types) */;
1026 u16 split_id /* Preted split ID (within the pretend split type) */;
1030 * Debug Tools data (per HW function)
1032 struct dbg_tools_data {
1033 struct dbg_grc_data grc /* GRC Dump data */;
1034 struct dbg_bus_data bus /* Debug Bus data */;
1035 struct idle_chk_data idle_chk /* Idle Check data */;
1036 u8 mode_enable[40] /* Indicates if a mode is enabled (0/1) */;
1037 /* Indicates if a block is in reset state (0/1) */
1038 u8 block_in_reset[132];
1039 u8 chip_id /* Chip ID (from enum chip_ids) */;
1040 u8 hw_type /* HW Type */;
1041 u8 num_ports /* Number of ports in the chip */;
1042 u8 num_pfs_per_port /* Number of PFs in each port */;
1043 u8 num_vfs /* Number of VFs in the chip */;
1044 u8 initialized /* Indicates if the data was initialized */;
1045 u8 use_dmae /* Indicates if DMAE should be used */;
1047 struct pretend_params pretend /* Current pretend parameters */;
1048 /* Numbers of registers that were read since last log */
1053 #endif /* __ECORE_HSI_DEBUG_TOOLS__ */